From 8a52631189549d03e461ac4d03ba12b835cfd6c9 Mon Sep 17 00:00:00 2001 From: Rejeesh Kutty Date: Thu, 18 Jun 2015 16:07:10 -0400 Subject: [PATCH] libary: util_jesd_align- signal tap interface --- library/util_jesd_align/util_jesd_align.v | 18 +++++++++++++++++- .../util_jesd_align/util_jesd_align_hw.tcl | 19 +++++++++++++++++++ 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/library/util_jesd_align/util_jesd_align.v b/library/util_jesd_align/util_jesd_align.v index b78e5383a..b70a43f8d 100644 --- a/library/util_jesd_align/util_jesd_align.v +++ b/library/util_jesd_align/util_jesd_align.v @@ -45,11 +45,16 @@ module util_jesd_align ( rx_ip_sof, rx_ip_data, rx_sof, - rx_data); + rx_data, + + rx_st_valid, + rx_st_data); // parameters parameter NUM_OF_LANES = 2; + parameter ST_VALID_WIDTH = 1; + parameter ST_DATA_WIDTH = 128; // xcvr interface @@ -59,8 +64,19 @@ module util_jesd_align ( output [((NUM_OF_LANES* 1)-1):0] rx_sof; output [((NUM_OF_LANES*32)-1):0] rx_data; + output [(ST_VALID_WIDTH-1):0] rx_st_valid; + output [(ST_DATA_WIDTH-1):0] rx_st_data; + + // internal signals + + wire [((NUM_OF_LANES*64)+3):0] rx_st_data_s; + // only for altera, xcvr+jesd do not frame align + assign rx_st_data_s = {rx_ip_sof, rx_ip_data, rx_data}; + assign rx_st_data = rx_st_data_s[(ST_DATA_WIDTH-1):0]; + assign rx_st_valid = 'd1; + genvar n; generate for (n = 0; n < NUM_OF_LANES; n = n + 1) begin: g_lane diff --git a/library/util_jesd_align/util_jesd_align_hw.tcl b/library/util_jesd_align/util_jesd_align_hw.tcl index 82d64ded6..8c958f3fb 100644 --- a/library/util_jesd_align/util_jesd_align_hw.tcl +++ b/library/util_jesd_align/util_jesd_align_hw.tcl @@ -27,6 +27,20 @@ set_parameter_property NUM_OF_LANES TYPE INTEGER set_parameter_property NUM_OF_LANES UNITS None set_parameter_property NUM_OF_LANES HDL_PARAMETER true +add_parameter ST_VALID_WIDTH INTEGER 0 +set_parameter_property ST_VALID_WIDTH DEFAULT_VALUE 1 +set_parameter_property ST_VALID_WIDTH DISPLAY_NAME ST_VALID_WIDTH +set_parameter_property ST_VALID_WIDTH TYPE INTEGER +set_parameter_property ST_VALID_WIDTH UNITS None +set_parameter_property ST_VALID_WIDTH HDL_PARAMETER true + +add_parameter ST_DATA_WIDTH INTEGER 0 +set_parameter_property ST_DATA_WIDTH DEFAULT_VALUE 32 +set_parameter_property ST_DATA_WIDTH DISPLAY_NAME ST_DATA_WIDTH +set_parameter_property ST_DATA_WIDTH TYPE INTEGER +set_parameter_property ST_DATA_WIDTH UNITS None +set_parameter_property ST_DATA_WIDTH HDL_PARAMETER true + # transceiver interface add_interface if_rx_clk clock end @@ -41,6 +55,11 @@ add_interface_port if_rx_data rx_data data Output 32*NUM_OF_LANES ad_alt_intf signal rx_ip_sof input 4 export ad_alt_intf signal rx_sof output NUM_OF_LANES export +add_interface if_rx_st conduit end +set_interface_property if_rx_st associatedClock if_rx_clk +add_interface_port if_rx_st rx_st_valid acq_trigger_in output ST_VALID_WIDTH +add_interface_port if_rx_st rx_st_data acq_data_in output ST_DATA_WIDTH + proc p_util_jesd_align {} { set p_num_of_lanes [get_parameter_value "NUM_OF_LANES"]