up_adc_common: Update custom RD/WR mechanism
alin724
Alin-Tudor Sferle
parent
4257a47b7a
commit
8ad959c16f
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@ -1,6 +1,6 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014 - 2022 (c) Analog Devices, Inc. All rights reserved.
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// Copyright 2014 - 2023 (c) Analog Devices, Inc. All rights reserved.
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//
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// In this HDL repository, there are many different and unique modules, consisting
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// of various HDL (Verilog or VHDL) components. The individual modules are
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@ -103,11 +103,10 @@ module up_adc_common #(
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// ADC custom read/write interface
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output [31:0] adc_custom_wr,
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output adc_write_req,
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input [31:0] adc_custom_rd,
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input adc_read_valid,
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output adc_read_req,
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output [31:0] adc_config_wr,
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output [31:0] adc_config_ctrl,
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input [31:0] adc_config_rd,
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input adc_ctrl_status,
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// user channel control
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@ -164,7 +163,8 @@ module up_adc_common #(
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reg [31:0] up_rdata_int = 'd0;
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reg [ 7:0] up_adc_custom_control = 'd0;
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reg up_adc_crc_enable = 'd0;
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reg [31:0] up_adc_custom_wr = 'd0;
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reg [31:0] up_adc_config_wr = 'd0;
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reg [31:0] up_adc_config_ctrl = 'd0;
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// internal signals
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@ -181,8 +181,8 @@ module up_adc_common #(
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wire up_drp_status_s;
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wire up_drp_rwn_s;
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wire [31:0] up_drp_rdata_hold_s;
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wire up_adc_read_valid;
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wire [31:0] up_adc_custom_rd;
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wire [31:0] up_adc_config_rd;
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wire up_adc_ctrl_status;
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wire adc_rst_n;
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wire adc_rst_s;
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@ -191,9 +191,6 @@ module up_adc_common #(
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assign up_wreq_s = (up_waddr[13:7] == {COMMON_ID,1'b0}) ? up_wreq : 1'b0;
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assign up_rreq_s = (up_raddr[13:7] == {COMMON_ID,1'b0}) ? up_rreq : 1'b0;
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assign up_rack_s = (up_raddr[6:0] == 7'h21) ? up_adc_read_valid : up_rreq_s;
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assign up_write_req = (up_waddr[6:0] == 7'h20) ? up_wreq : 1'b0;
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assign up_read_req = (up_raddr[6:0] == 7'h21) ? up_rreq : 1'b0;
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// processor write interface
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@ -354,10 +351,20 @@ module up_adc_common #(
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_custom_wr <= 'd0;
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up_adc_config_wr <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h20)) begin
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up_adc_custom_wr <= up_wdata;
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up_adc_config_wr <= up_wdata;
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end
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end
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end
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always @(posedge up_clk) begin
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if (up_rstn == 0) begin
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up_adc_config_ctrl <= 'd0;
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end else begin
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if ((up_wreq_s == 1'b1) && (up_waddr[6:0] == 7'h23)) begin
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up_adc_config_ctrl <= up_wdata;
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end
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end
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end
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@ -456,8 +463,8 @@ module up_adc_common #(
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up_rack_int <= 'd0;
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up_rdata_int <= 'd0;
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end else begin
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up_rack_int <= up_rack_s;
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if (up_rack_s == 1'b1) begin
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up_rack_int <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr[6:0])
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7'h00: up_rdata_int <= VERSION;
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7'h01: up_rdata_int <= ID;
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@ -478,16 +485,16 @@ module up_adc_common #(
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7'h13: up_rdata_int <= {23'd0, up_adc_crc_enable, up_adc_custom_control};
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7'h15: up_rdata_int <= up_adc_clk_count_s;
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7'h16: up_rdata_int <= adc_clk_ratio;
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7'h17: up_rdata_int <= {28'd0, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
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7'h17: up_rdata_int <= {27'd0, up_adc_ctrl_status, up_status_pn_err, up_status_pn_oos, up_status_or, up_status_s};
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7'h1a: up_rdata_int <= {31'd0, up_sync_status_s};
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7'h1c: up_rdata_int <= {3'd0, up_drp_rwn_s, up_drp_addr, 16'b0};
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7'h1d: up_rdata_int <= {14'd0, up_drp_locked, up_drp_status_s, 16'b0};
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7'h1e: up_rdata_int <= up_drp_wdata;
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7'h1f: up_rdata_int <= up_drp_rdata_hold_s;
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7'h20: up_rdata_int <= up_adc_custom_wr;
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7'h21: up_rdata_int <= up_adc_custom_rd;
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7'h20: up_rdata_int <= up_adc_config_wr;
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7'h21: up_rdata_int <= up_adc_config_rd;
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7'h22: up_rdata_int <= {29'd0, up_status_ovf, 2'b0};
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7'h23: up_rdata_int <= 32'd8;
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7'h23: up_rdata_int <= up_adc_config_ctrl;
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7'h28: up_rdata_int <= {24'd0, up_usr_chanmax_in};
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7'h29: up_rdata_int <= up_adc_start_code;
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7'h2e: up_rdata_int <= up_adc_gpio_in;
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@ -520,7 +527,7 @@ module up_adc_common #(
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// adc control & status
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up_xfer_cntrl #(
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.DATA_WIDTH(92)
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.DATA_WIDTH(122)
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) i_xfer_cntrl (
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.up_rstn (up_rstn),
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.up_clk (up_clk),
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@ -535,9 +542,8 @@ module up_adc_common #(
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up_adc_ext_sync_disarm,
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up_adc_ext_sync_manual_req,
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up_adc_sync,
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up_write_req,
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up_read_req,
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up_adc_custom_wr,
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up_adc_config_ctrl,
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up_adc_config_wr,
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up_adc_start_code,
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up_adc_r1_mode,
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up_adc_ddr_edgesel,
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@ -557,9 +563,8 @@ module up_adc_common #(
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adc_ext_sync_disarm,
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adc_ext_sync_manual_req,
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adc_sync,
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adc_write_req,
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adc_read_req,
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adc_custom_wr,
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adc_config_ctrl,
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adc_config_wr,
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adc_start_code,
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adc_r1_mode,
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adc_ddr_edgesel,
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@ -580,15 +585,15 @@ module up_adc_common #(
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.up_data_status ({up_sync_status_s,
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up_status_s,
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up_status_ovf_s,
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up_adc_read_valid,
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up_adc_custom_rd}),
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up_adc_config_rd,
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up_adc_ctrl_status}),
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.d_rst (adc_rst_s),
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.d_clk (adc_clk),
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.d_data_status ({ adc_sync_status,
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adc_status,
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adc_status_ovf,
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adc_read_valid,
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adc_custom_rd}));
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adc_config_rd,
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adc_ctrl_status}));
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// adc clock monitor
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