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axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin

main
Adrian Costina 2017-04-03 15:07:56 +03:00 committed by Lars-Peter Clausen
parent 07e52b4566
commit 8ba86cb75c
1 changed files with 16 additions and 7 deletions
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23
library/axi_logic_analyzer/axi_logic_analyzer.v
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@ -94,6 +94,8 @@ module axi_logic_analyzer (
reg adc_valid_d1 = 'd0;
reg adc_valid_d2 = 'd0;
reg [15:0] io_selection; // 1 - input, 0 - output
// internal signals
wire up_clk;
@ -121,7 +123,7 @@ module axi_logic_analyzer (
wire [15:0] overwrite_enable;
wire [15:0] overwrite_data;
wire [15:0] io_selection;
wire [15:0] io_selection_s; // 1 - input, 0 - output
wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
genvar i;
@ -139,6 +141,18 @@ module axi_logic_analyzer (
always @(posedge clk_out) begin
data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
end
always @(posedge clk_out) begin
if(dac_valid == 1'b1) begin
data_r[i] <= dac_data[i];
end
if (io_selection_s[i] == 1'b1) begin
io_selection[i] <= 1'b1;
end else begin
if(dac_valid == 1'b1 || overwrite_data[i] == 1'b1) begin
io_selection[i] <= 1'b0;
end
end
end
end
endgenerate
@ -204,11 +218,6 @@ module axi_logic_analyzer (
end
end
always @(posedge clk_out) begin
if (dac_valid == 1'b1) begin
data_r <= dac_data;
end
end
axi_logic_analyzer_trigger i_trigger (
.clk (clk_out),
@ -233,7 +242,7 @@ module axi_logic_analyzer (
.divider_counter_la (divider_counter_la),
.divider_counter_pg (divider_counter_pg),
.io_selection (io_selection),
.io_selection (io_selection_s),
.edge_detect_enable (edge_detect_enable),
.rise_edge_enable (rise_edge_enable),