axi_logic_analyzer: Allow changing data pins direction to output only after data is available from the DMA or if the output is set from a register for that specific pin
parent
07e52b4566
commit
8ba86cb75c
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@ -94,6 +94,8 @@ module axi_logic_analyzer (
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reg adc_valid_d1 = 'd0;
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reg adc_valid_d1 = 'd0;
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reg adc_valid_d2 = 'd0;
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reg adc_valid_d2 = 'd0;
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reg [15:0] io_selection; // 1 - input, 0 - output
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// internal signals
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// internal signals
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wire up_clk;
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wire up_clk;
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@ -121,7 +123,7 @@ module axi_logic_analyzer (
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wire [15:0] overwrite_enable;
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wire [15:0] overwrite_enable;
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wire [15:0] overwrite_data;
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wire [15:0] overwrite_data;
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wire [15:0] io_selection;
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wire [15:0] io_selection_s; // 1 - input, 0 - output
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wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
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wire [15:0] od_pp_n; // 0 - push/pull, 1 - open drain
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genvar i;
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genvar i;
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@ -139,6 +141,18 @@ module axi_logic_analyzer (
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always @(posedge clk_out) begin
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always @(posedge clk_out) begin
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data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
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data_o[i] <= overwrite_enable[i] ? overwrite_data[i] : data_r[i];
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end
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end
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always @(posedge clk_out) begin
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if(dac_valid == 1'b1) begin
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data_r[i] <= dac_data[i];
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end
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if (io_selection_s[i] == 1'b1) begin
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io_selection[i] <= 1'b1;
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end else begin
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if(dac_valid == 1'b1 || overwrite_data[i] == 1'b1) begin
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io_selection[i] <= 1'b0;
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end
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end
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end
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end
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end
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endgenerate
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endgenerate
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@ -204,11 +218,6 @@ module axi_logic_analyzer (
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end
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end
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end
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end
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always @(posedge clk_out) begin
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if (dac_valid == 1'b1) begin
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data_r <= dac_data;
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end
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end
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axi_logic_analyzer_trigger i_trigger (
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axi_logic_analyzer_trigger i_trigger (
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.clk (clk_out),
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.clk (clk_out),
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@ -233,7 +242,7 @@ module axi_logic_analyzer (
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.divider_counter_la (divider_counter_la),
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.divider_counter_la (divider_counter_la),
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.divider_counter_pg (divider_counter_pg),
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.divider_counter_pg (divider_counter_pg),
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.io_selection (io_selection),
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.io_selection (io_selection_s),
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.edge_detect_enable (edge_detect_enable),
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.edge_detect_enable (edge_detect_enable),
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.rise_edge_enable (rise_edge_enable),
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.rise_edge_enable (rise_edge_enable),
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