From 8bce4c5b0a19243bcfd879110ac757558c12af46 Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Tue, 20 Nov 2018 14:02:02 +0000 Subject: [PATCH] jesd204_tpl: update address widths of TPL instances --- library/axi_ad6676/axi_ad6676.v | 4 ++-- library/axi_ad9144/axi_ad9144.v | 4 ++-- library/axi_ad9144/axi_ad9144_hw.tcl | 2 +- library/axi_ad9152/axi_ad9152.v | 4 ++-- library/axi_ad9152/axi_ad9152_hw.tcl | 2 +- library/axi_ad9250/axi_ad9250.v | 4 ++-- library/axi_ad9680/axi_ad9680.v | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/library/axi_ad6676/axi_ad6676.v b/library/axi_ad6676/axi_ad6676.v index 1ba389cc0..69b2d7905 100644 --- a/library/axi_ad6676/axi_ad6676.v +++ b/library/axi_ad6676/axi_ad6676.v @@ -65,7 +65,7 @@ module axi_ad6676 #( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [15:0] s_axi_awaddr, + input [11:0] s_axi_awaddr, output s_axi_awready, input s_axi_wvalid, input [31:0] s_axi_wdata, @@ -75,7 +75,7 @@ module axi_ad6676 #( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [15:0] s_axi_araddr, + input [11:0] s_axi_araddr, output s_axi_arready, output s_axi_rvalid, output [ 1:0] s_axi_rresp, diff --git a/library/axi_ad9144/axi_ad9144.v b/library/axi_ad9144/axi_ad9144.v index 9c4ceaff9..0775331b1 100644 --- a/library/axi_ad9144/axi_ad9144.v +++ b/library/axi_ad9144/axi_ad9144.v @@ -74,7 +74,7 @@ module axi_ad9144 #( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [ 15:0] s_axi_awaddr, + input [ 11:0] s_axi_awaddr, input [ 2:0] s_axi_awprot, output s_axi_awready, input s_axi_wvalid, @@ -85,7 +85,7 @@ module axi_ad9144 #( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [ 15:0] s_axi_araddr, + input [ 11:0] s_axi_araddr, input [ 2:0] s_axi_arprot, output s_axi_arready, output s_axi_rvalid, diff --git a/library/axi_ad9144/axi_ad9144_hw.tcl b/library/axi_ad9144/axi_ad9144_hw.tcl index 48ff9157b..e95051860 100644 --- a/library/axi_ad9144/axi_ad9144_hw.tcl +++ b/library/axi_ad9144/axi_ad9144_hw.tcl @@ -62,7 +62,7 @@ set_parameter_property QUAD_OR_DUAL_N HDL_PARAMETER true # axi4 slave -ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 # transceiver interface diff --git a/library/axi_ad9152/axi_ad9152.v b/library/axi_ad9152/axi_ad9152.v index 702d13dc3..259ffe02d 100644 --- a/library/axi_ad9152/axi_ad9152.v +++ b/library/axi_ad9152/axi_ad9152.v @@ -67,7 +67,7 @@ module axi_ad9152 #( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [ 15:0] s_axi_awaddr, + input [ 11:0] s_axi_awaddr, input [ 2:0] s_axi_awprot, output s_axi_awready, input s_axi_wvalid, @@ -78,7 +78,7 @@ module axi_ad9152 #( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [ 15:0] s_axi_araddr, + input [ 11:0] s_axi_araddr, input [ 2:0] s_axi_arprot, output s_axi_arready, output s_axi_rvalid, diff --git a/library/axi_ad9152/axi_ad9152_hw.tcl b/library/axi_ad9152/axi_ad9152_hw.tcl index 912f1de59..dadc5f8c5 100644 --- a/library/axi_ad9152/axi_ad9152_hw.tcl +++ b/library/axi_ad9152/axi_ad9152_hw.tcl @@ -54,7 +54,7 @@ set_parameter_property ID HDL_PARAMETER true # axi4 slave -ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn +ad_ip_intf_s_axi s_axi_aclk s_axi_aresetn 12 # transceiver interface diff --git a/library/axi_ad9250/axi_ad9250.v b/library/axi_ad9250/axi_ad9250.v index 3684e029b..d2113ada2 100644 --- a/library/axi_ad9250/axi_ad9250.v +++ b/library/axi_ad9250/axi_ad9250.v @@ -64,7 +64,7 @@ module axi_ad9250 #( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [15:0] s_axi_awaddr, + input [11:0] s_axi_awaddr, input [ 2:0] s_axi_awprot, output s_axi_awready, input s_axi_wvalid, @@ -75,7 +75,7 @@ module axi_ad9250 #( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [15:0] s_axi_araddr, + input [11:0] s_axi_araddr, input [ 2:0] s_axi_arprot, output s_axi_arready, output s_axi_rvalid, diff --git a/library/axi_ad9680/axi_ad9680.v b/library/axi_ad9680/axi_ad9680.v index 1e0bac650..5b0b1236c 100644 --- a/library/axi_ad9680/axi_ad9680.v +++ b/library/axi_ad9680/axi_ad9680.v @@ -64,7 +64,7 @@ module axi_ad9680 #( input s_axi_aclk, input s_axi_aresetn, input s_axi_awvalid, - input [15:0] s_axi_awaddr, + input [11:0] s_axi_awaddr, input [ 2:0] s_axi_awprot, output s_axi_awready, input s_axi_wvalid, @@ -75,7 +75,7 @@ module axi_ad9680 #( output [ 1:0] s_axi_bresp, input s_axi_bready, input s_axi_arvalid, - input [15:0] s_axi_araddr, + input [11:0] s_axi_araddr, input [ 2:0] s_axi_arprot, output s_axi_arready, output s_axi_rvalid,