From 8c08c5a65afacb63fbafb3deec50ba0e4d428c55 Mon Sep 17 00:00:00 2001 From: AndreiGrozav Date: Thu, 18 Apr 2024 19:58:40 +0300 Subject: [PATCH] axi_pwm_gen: Update constraint file This change will fix the timing closure for designs where the external clock is not a submultiple of the s_axi_clk. Signed-off-by: AndreiGrozav --- library/axi_pwm_gen/axi_pwm_gen_constr.ttcl | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl b/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl index e8ad6baee..da0422eb7 100644 --- a/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl +++ b/library/axi_pwm_gen/axi_pwm_gen_constr.ttcl @@ -34,4 +34,16 @@ set_property ASYNC_REG TRUE \ -from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \ -to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}] + set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/cdc_hold_reg*}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_data_reg*}] + + set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/in_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_out/cdc_sync_stage1_reg[*]}] + + set_false_path \ + -from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_toggle_d1_reg}] \ + -to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_in/cdc_sync_stage1_reg[*]}] + <: } :>