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axi_pwm_gen: Update constraint file 

This change will fix the timing closure for designs where the external
clock is not a submultiple of the s_axi_clk.

Signed-off-by: AndreiGrozav <andrei.grozav@analog.com>
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AndreiGrozav 2024-04-18 19:58:40 +03:00 committed by AndreiGrozav
parent e79091eecd
commit 8c08c5a65a
1 changed files with 12 additions and 0 deletions
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12
library/axi_pwm_gen/axi_pwm_gen_constr.ttcl
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@ -34,4 +34,16 @@ set_property ASYNC_REG TRUE \
-from [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/in_toggle_d1_reg/C}] \
-to [get_pins -hierarchical * -filter {NAME=~*i_load_config_sync/i_sync_out/cdc_sync_stage1_reg[0]/D}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/cdc_hold_reg*}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_data_reg*}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/in_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_out/cdc_sync_stage1_reg[*]}]
set_false_path \
-from [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/out_toggle_d1_reg}] \
-to [get_cells -hierarchical * -filter {NAME=~*i_regmap/*i_pwm_controls/i_sync_in/cdc_sync_stage1_reg[*]}]
<: } :>