From 8c4279f618af33406a1921f1dbe916107dabf5c7 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Tue, 22 Nov 2016 16:58:34 +0200 Subject: [PATCH] pzsdr1: Added ccusb_lvds initial project --- projects/pzsdr1/Makefile | 3 + projects/pzsdr1/ccusb_lvds/system_bd.tcl | 6 + projects/pzsdr1/ccusb_lvds/system_project.tcl | 20 ++ projects/pzsdr1/ccusb_lvds/system_top.v | 238 ++++++++++++++++++ projects/pzsdr1/common/ccusb_bd.tcl | 71 ++++++ projects/pzsdr1/common/ccusb_constr.xdc | 71 ++++++ 6 files changed, 409 insertions(+) create mode 100644 projects/pzsdr1/ccusb_lvds/system_bd.tcl create mode 100644 projects/pzsdr1/ccusb_lvds/system_project.tcl create mode 100644 projects/pzsdr1/ccusb_lvds/system_top.v create mode 100644 projects/pzsdr1/common/ccusb_bd.tcl create mode 100644 projects/pzsdr1/common/ccusb_constr.xdc diff --git a/projects/pzsdr1/Makefile b/projects/pzsdr1/Makefile index d31684d1c..a7e5f4320 100644 --- a/projects/pzsdr1/Makefile +++ b/projects/pzsdr1/Makefile @@ -10,18 +10,21 @@ all: -make -C ccbox_lvds all -make -C ccbrk_cmos all -make -C ccbrk_lvds all + -make -C ccusb_lvds all clean: make -C ccbox_lvds clean make -C ccbrk_cmos clean make -C ccbrk_lvds clean + make -C ccusb_lvds clean clean-all: make -C ccbox_lvds clean-all make -C ccbrk_cmos clean-all make -C ccbrk_lvds clean-all + make -C ccusb_lvds clean-all #################################################################################### #################################################################################### diff --git a/projects/pzsdr1/ccusb_lvds/system_bd.tcl b/projects/pzsdr1/ccusb_lvds/system_bd.tcl new file mode 100644 index 000000000..4b0e97a6d --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_bd.tcl @@ -0,0 +1,6 @@ + +source ../common/pzsdr1_bd.tcl +source ../common/ccusb_bd.tcl + +cfg_ad9361_interface LVDS + diff --git a/projects/pzsdr1/ccusb_lvds/system_project.tcl b/projects/pzsdr1/ccusb_lvds/system_project.tcl new file mode 100644 index 000000000..5567bd97b --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_project.tcl @@ -0,0 +1,20 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +set p_device "xc7z020clg400-1" +adi_project_create pzsdr1_ccusb_lvds +adi_project_files pzsdr1_ccusb_lvds [list \ + "system_top.v" \ + "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \ + "../common/pzsdr1_constr.xdc" \ + "../common/pzsdr1_constr_lvds.xdc" \ + "../common/ccusb_constr.xdc" ] + +set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr1_constr.xdc] +set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc] + +adi_project_run pzsdr1_ccusb_lvds + + diff --git a/projects/pzsdr1/ccusb_lvds/system_top.v b/projects/pzsdr1/ccusb_lvds/system_top.v new file mode 100644 index 000000000..7b136adf6 --- /dev/null +++ b/projects/pzsdr1/ccusb_lvds/system_top.v @@ -0,0 +1,238 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + inout [14:0] ddr_addr, + inout [ 2:0] ddr_ba, + inout ddr_cas_n, + inout ddr_ck_n, + inout ddr_ck_p, + inout ddr_cke, + inout ddr_cs_n, + inout [ 3:0] ddr_dm, + inout [31:0] ddr_dq, + inout [ 3:0] ddr_dqs_n, + inout [ 3:0] ddr_dqs_p, + inout ddr_odt, + inout ddr_ras_n, + inout ddr_reset_n, + inout ddr_we_n, + + inout fixed_io_ddr_vrn, + inout fixed_io_ddr_vrp, + inout [53:0] fixed_io_mio, + inout fixed_io_ps_clk, + inout fixed_io_ps_porb, + inout fixed_io_ps_srstb, + + inout iic_scl, + inout iic_sda, + + input rx_clk_in_p, + input rx_clk_in_n, + input rx_frame_in_p, + input rx_frame_in_n, + input [ 5:0] rx_data_in_p, + input [ 5:0] rx_data_in_n, + output tx_clk_out_p, + output tx_clk_out_n, + output tx_frame_out_p, + output tx_frame_out_n, + output [ 5:0] tx_data_out_p, + output [ 5:0] tx_data_out_n, + + output enable, + output txnrx, + input clk_out, + + inout gpio_clksel, + inout gpio_resetb, + inout gpio_sync, + inout gpio_en_agc, + inout [ 3:0] gpio_ctl, + inout [ 7:0] gpio_status, + + input usb_fx3_uart_tx, + output usb_fx3_uart_rx, + + input [ 7:0] fifo_rdy, + + inout [31:0] data, + output [ 4:0] addr, + output pclk, + output slcs_n, + output slrd_n, + output sloe_n, + output slwr_n, + output pktend_n, + output epswitch_n, + + output reset_n, + + output [ 2:0] pmode, + + output spi_csn, + output spi_clk, + output spi_mosi, + input spi_miso); + + // internal signals + + wire [63:0] gpio_i; + wire [63:0] gpio_o; + wire [63:0] gpio_t; + + // assignments + + assign pmode = 3'b111; + assign addr[4:2] = 3'b000; + + assign epswitch_n = 1'b1; + assign reset_n = 1'b1; + + // instantiations + + ad_iobuf #(.DATA_WIDTH(16)) i_iobuf ( + .dio_t ({gpio_t[51], gpio_t[46:32]}), + .dio_i ({gpio_o[51], gpio_o[46:32]}), + .dio_o ({gpio_i[51], gpio_i[46:32]}), + .dio_p ({ gpio_clksel, // 51:51 + gpio_resetb, // 46:46 + gpio_sync, // 45:45 + gpio_en_agc, // 44:44 + gpio_ctl, // 43:40 + gpio_status})); // 39:32 + + system_wrapper i_system_wrapper ( + .ddr_addr (ddr_addr), + .ddr_ba (ddr_ba), + .ddr_cas_n (ddr_cas_n), + .ddr_ck_n (ddr_ck_n), + .ddr_ck_p (ddr_ck_p), + .ddr_cke (ddr_cke), + .ddr_cs_n (ddr_cs_n), + .ddr_dm (ddr_dm), + .ddr_dq (ddr_dq), + .ddr_dqs_n (ddr_dqs_n), + .ddr_dqs_p (ddr_dqs_p), + .ddr_odt (ddr_odt), + .ddr_ras_n (ddr_ras_n), + .ddr_reset_n (ddr_reset_n), + .ddr_we_n (ddr_we_n), + .enable (enable), + .fixed_io_ddr_vrn (fixed_io_ddr_vrn), + .fixed_io_ddr_vrp (fixed_io_ddr_vrp), + .fixed_io_mio (fixed_io_mio), + .fixed_io_ps_clk (fixed_io_ps_clk), + .fixed_io_ps_porb (fixed_io_ps_porb), + .fixed_io_ps_srstb (fixed_io_ps_srstb), + .gpio_i (gpio_i), + .gpio_o (gpio_o), + .gpio_t (gpio_t), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + .otg_vbusoc (1'b0), + .ps_intr_00 (1'b0), + .ps_intr_01 (1'b0), + .ps_intr_02 (1'b0), + .ps_intr_03 (1'b0), + .ps_intr_04 (1'b0), + .ps_intr_05 (1'b0), + .ps_intr_06 (1'b0), + .ps_intr_07 (1'b0), + .ps_intr_08 (1'b0), + .ps_intr_09 (1'b0), + .ps_intr_15 (1'b0), + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + .spi0_clk_i (1'b0), + .spi0_clk_o (spi_clk), + .spi0_csn_0_o (spi_csn), + .spi0_csn_1_o (), + .spi0_csn_2_o (), + .spi0_csn_i (1'b1), + .spi0_sdi_i (spi_miso), + .spi0_sdo_i (1'b0), + .spi0_sdo_o (spi_mosi), + .spi1_clk_i (1'b0), + .spi1_clk_o (), + .spi1_csn_0_o (), + .spi1_csn_1_o (), + .spi1_csn_2_o (), + .spi1_csn_i (1'b1), + .spi1_sdi_i (1'b0), + .spi1_sdo_i (1'b0), + .spi1_sdo_o (), + .tdd_sync_i (1'b0), + .tdd_sync_o (), + .tdd_sync_t (), + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + .txnrx (txnrx), + .up_enable (gpio_o[47]), + .up_txnrx (gpio_o[48]), + .usb_fx3_uart_tx(usb_fx3_uart_tx), + .usb_fx3_uart_rx(usb_fx3_uart_rx), + .dma_rdy(), + .dma_wmk(), + .fifo_rdy(fifo_rdy[3:0]), + .pclk(pclk), + .data(data), + .addr(addr[1:0]), + .slcs_n(slcs_n), + .slrd_n(slrd_n), + .sloe_n(sloe_n), + .slwr_n(slwr_n), + // .epswitch_n(epswitch_n), + .pktend_n(pktend_n) + ); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/pzsdr1/common/ccusb_bd.tcl b/projects/pzsdr1/common/ccusb_bd.tcl new file mode 100644 index 000000000..dee7493c1 --- /dev/null +++ b/projects/pzsdr1/common/ccusb_bd.tcl @@ -0,0 +1,71 @@ + +create_bd_port -dir I usb_fx3_uart_tx +create_bd_port -dir O usb_fx3_uart_rx + +create_bd_port -dir I dma_rdy +create_bd_port -dir I dma_wmk +create_bd_port -dir I -from 3 -to 0 fifo_rdy +create_bd_port -dir O pclk +create_bd_port -dir IO -from 31 -to 0 data +create_bd_port -dir O -from 1 -to 0 addr +create_bd_port -dir O slcs_n +create_bd_port -dir O slrd_n +create_bd_port -dir O sloe_n +create_bd_port -dir O slwr_n +create_bd_port -dir O pktend_n +create_bd_port -dir O epswitch_n + +set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart] +set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart + +set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3] + +set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma] +set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma +set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma + +set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ] + +ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S + +ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk +ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn + +ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS +ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS + +ad_connect axi_uart/rx usb_fx3_uart_tx +ad_connect axi_uart/tx usb_fx3_uart_rx + +ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk +ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn + +ad_connect axi_usb_fx3/dma_rdy dma_rdy +ad_connect axi_usb_fx3/dma_wmk dma_wmk +ad_connect axi_usb_fx3/fifo_rdy fifo_rdy +ad_connect axi_usb_fx3/pclk pclk +ad_connect axi_usb_fx3/data data +ad_connect axi_usb_fx3/addr addr +ad_connect axi_usb_fx3/slcs_n slcs_n +ad_connect axi_usb_fx3/slrd_n slrd_n +ad_connect axi_usb_fx3/sloe_n sloe_n +ad_connect axi_usb_fx3/slwr_n slwr_n +ad_connect axi_usb_fx3/pktend_n pktend_n +ad_connect axi_usb_fx3/epswitch_n epswitch_n + + +ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq +ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut +ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut +ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt + +ad_cpu_interconnect 0x50000000 axi_usb_fx3 +ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma +ad_cpu_interconnect 0x40600000 axi_uart + +ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3 +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S +ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM diff --git a/projects/pzsdr1/common/ccusb_constr.xdc b/projects/pzsdr1/common/ccusb_constr.xdc new file mode 100644 index 000000000..de25d854d --- /dev/null +++ b/projects/pzsdr1/common/ccusb_constr.xdc @@ -0,0 +1,71 @@ +# Default constraints have LVCMOS25, overwite it +#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ; +#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ; + +# USB_FX3 + +set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports data[30]] ; +set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports data[31]] ; +set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports data[24]] ; +set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports data[27]] ; +set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports data[26]] ; +set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports data[21]] ; +set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports data[18]] ; +set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports data[19]] ; +set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports data[23]] ; +set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports data[20]] ; +set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports data[2]] ; +set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports data[14]] ; +set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports data[13]] ; +set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports data[9]] ; +set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports data[12]] ; +set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports data[8]] ; +set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports data[7]] ; +set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports data[3]] ; +set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports data[0]] ; +set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports data[4]] ; +set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports data[5]] ; +set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports data[28]] ; +set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports data[29]] ; +set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports data[25]] ; +set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports data[22]] ; +set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports data[16]] ; +set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports data[17]] ; +set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports data[15]] ; +set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports data[11]] ; +set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports data[10]] ; +set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports data[6]] ; +set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports data[1]] ; + +set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports pclk] ; + +set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports addr[0]] ; +set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports addr[1]] ; +set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports addr[2]] ; +set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports addr[3]] ; +set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports addr[4]] ; + +set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports slcs_n] ; +set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports slwr_n] ; +set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports sloe_n] ; +set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports slrd_n] ; +set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports pktend_n] ; + +set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ; +set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ; + +set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]] ; +set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]] ; +set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]] ; +set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]] ; +set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[4]] ; +set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[5]] ; +set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[6]] ; +set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[7]] ; + +set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pmode[0]] ; +set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports pmode[1]] ; +set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports pmode[2]] ; + +set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports reset_n] ; +set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports epswitch_n] ;