pzsdr1: Added ccusb_lvds initial project
Adrian Costina
parent
3d0049d274
commit
8c4279f618
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@ -10,18 +10,21 @@ all:
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-make -C ccbox_lvds all
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-make -C ccbrk_cmos all
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-make -C ccbrk_lvds all
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-make -C ccusb_lvds all
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clean:
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make -C ccbox_lvds clean
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make -C ccbrk_cmos clean
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make -C ccbrk_lvds clean
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make -C ccusb_lvds clean
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clean-all:
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make -C ccbox_lvds clean-all
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make -C ccbrk_cmos clean-all
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make -C ccbrk_lvds clean-all
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make -C ccusb_lvds clean-all
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####################################################################################
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####################################################################################
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@ -0,0 +1,6 @@
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source ../common/pzsdr1_bd.tcl
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source ../common/ccusb_bd.tcl
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cfg_ad9361_interface LVDS
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@ -0,0 +1,20 @@
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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source $ad_hdl_dir/projects/scripts/adi_board.tcl
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set p_device "xc7z020clg400-1"
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adi_project_create pzsdr1_ccusb_lvds
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adi_project_files pzsdr1_ccusb_lvds [list \
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"system_top.v" \
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"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
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"../common/pzsdr1_constr.xdc" \
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"../common/pzsdr1_constr_lvds.xdc" \
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"../common/ccusb_constr.xdc" ]
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set_property PROCESSING_ORDER EARLY [get_files ../common/pzsdr1_constr.xdc]
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set_property PROCESSING_ORDER LATE [get_files ../common/ccusb_constr.xdc]
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adi_project_run pzsdr1_ccusb_lvds
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@ -0,0 +1,238 @@
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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inout [14:0] ddr_addr,
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inout [ 2:0] ddr_ba,
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inout ddr_cas_n,
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inout ddr_ck_n,
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inout ddr_ck_p,
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inout ddr_cke,
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inout ddr_cs_n,
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inout [ 3:0] ddr_dm,
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inout [31:0] ddr_dq,
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inout [ 3:0] ddr_dqs_n,
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inout [ 3:0] ddr_dqs_p,
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inout ddr_odt,
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inout ddr_ras_n,
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inout ddr_reset_n,
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inout ddr_we_n,
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inout fixed_io_ddr_vrn,
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inout fixed_io_ddr_vrp,
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inout [53:0] fixed_io_mio,
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inout fixed_io_ps_clk,
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inout fixed_io_ps_porb,
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inout fixed_io_ps_srstb,
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inout iic_scl,
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inout iic_sda,
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input rx_clk_in_p,
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input rx_clk_in_n,
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input rx_frame_in_p,
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input rx_frame_in_n,
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input [ 5:0] rx_data_in_p,
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input [ 5:0] rx_data_in_n,
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output tx_clk_out_p,
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output tx_clk_out_n,
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output tx_frame_out_p,
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output tx_frame_out_n,
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output [ 5:0] tx_data_out_p,
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output [ 5:0] tx_data_out_n,
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output enable,
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output txnrx,
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input clk_out,
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inout gpio_clksel,
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inout gpio_resetb,
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inout gpio_sync,
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inout gpio_en_agc,
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inout [ 3:0] gpio_ctl,
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inout [ 7:0] gpio_status,
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input usb_fx3_uart_tx,
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output usb_fx3_uart_rx,
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input [ 7:0] fifo_rdy,
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inout [31:0] data,
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output [ 4:0] addr,
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output pclk,
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output slcs_n,
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output slrd_n,
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output sloe_n,
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output slwr_n,
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output pktend_n,
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output epswitch_n,
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output reset_n,
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output [ 2:0] pmode,
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output spi_csn,
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output spi_clk,
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output spi_mosi,
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input spi_miso);
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// internal signals
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wire [63:0] gpio_i;
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wire [63:0] gpio_o;
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wire [63:0] gpio_t;
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// assignments
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assign pmode = 3'b111;
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assign addr[4:2] = 3'b000;
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assign epswitch_n = 1'b1;
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assign reset_n = 1'b1;
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// instantiations
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ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
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.dio_t ({gpio_t[51], gpio_t[46:32]}),
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.dio_i ({gpio_o[51], gpio_o[46:32]}),
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.dio_o ({gpio_i[51], gpio_i[46:32]}),
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.dio_p ({ gpio_clksel, // 51:51
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gpio_resetb, // 46:46
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gpio_sync, // 45:45
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gpio_en_agc, // 44:44
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gpio_ctl, // 43:40
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gpio_status})); // 39:32
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system_wrapper i_system_wrapper (
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.ddr_addr (ddr_addr),
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.ddr_ba (ddr_ba),
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.ddr_cas_n (ddr_cas_n),
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.ddr_ck_n (ddr_ck_n),
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.ddr_ck_p (ddr_ck_p),
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.ddr_cke (ddr_cke),
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.ddr_cs_n (ddr_cs_n),
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.ddr_dm (ddr_dm),
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.ddr_dq (ddr_dq),
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.ddr_dqs_n (ddr_dqs_n),
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.ddr_dqs_p (ddr_dqs_p),
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.ddr_odt (ddr_odt),
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.ddr_ras_n (ddr_ras_n),
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.ddr_reset_n (ddr_reset_n),
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.ddr_we_n (ddr_we_n),
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.enable (enable),
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.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
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.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
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.fixed_io_mio (fixed_io_mio),
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.fixed_io_ps_clk (fixed_io_ps_clk),
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.fixed_io_ps_porb (fixed_io_ps_porb),
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.fixed_io_ps_srstb (fixed_io_ps_srstb),
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.gpio_i (gpio_i),
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.gpio_o (gpio_o),
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.gpio_t (gpio_t),
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.iic_main_scl_io (iic_scl),
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.iic_main_sda_io (iic_sda),
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.otg_vbusoc (1'b0),
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.ps_intr_00 (1'b0),
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.ps_intr_01 (1'b0),
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.ps_intr_02 (1'b0),
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.ps_intr_03 (1'b0),
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.ps_intr_04 (1'b0),
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.ps_intr_05 (1'b0),
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.ps_intr_06 (1'b0),
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.ps_intr_07 (1'b0),
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.ps_intr_08 (1'b0),
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.ps_intr_09 (1'b0),
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.ps_intr_15 (1'b0),
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.rx_clk_in_n (rx_clk_in_n),
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.rx_clk_in_p (rx_clk_in_p),
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.rx_data_in_n (rx_data_in_n),
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.rx_data_in_p (rx_data_in_p),
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.rx_frame_in_n (rx_frame_in_n),
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.rx_frame_in_p (rx_frame_in_p),
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.spi0_clk_i (1'b0),
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.spi0_clk_o (spi_clk),
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.spi0_csn_0_o (spi_csn),
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.spi0_csn_1_o (),
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.spi0_csn_2_o (),
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.spi0_csn_i (1'b1),
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.spi0_sdi_i (spi_miso),
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.spi0_sdo_i (1'b0),
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.spi0_sdo_o (spi_mosi),
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.spi1_clk_i (1'b0),
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.spi1_clk_o (),
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.spi1_csn_0_o (),
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.spi1_csn_1_o (),
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.spi1_csn_2_o (),
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.spi1_csn_i (1'b1),
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.spi1_sdi_i (1'b0),
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.spi1_sdo_i (1'b0),
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.spi1_sdo_o (),
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.tdd_sync_i (1'b0),
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.tdd_sync_o (),
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.tdd_sync_t (),
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.tx_clk_out_n (tx_clk_out_n),
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.tx_clk_out_p (tx_clk_out_p),
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.tx_data_out_n (tx_data_out_n),
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.tx_data_out_p (tx_data_out_p),
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.tx_frame_out_n (tx_frame_out_n),
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.tx_frame_out_p (tx_frame_out_p),
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.txnrx (txnrx),
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.up_enable (gpio_o[47]),
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.up_txnrx (gpio_o[48]),
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.usb_fx3_uart_tx(usb_fx3_uart_tx),
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.usb_fx3_uart_rx(usb_fx3_uart_rx),
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.dma_rdy(),
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.dma_wmk(),
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.fifo_rdy(fifo_rdy[3:0]),
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.pclk(pclk),
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.data(data),
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.addr(addr[1:0]),
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.slcs_n(slcs_n),
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.slrd_n(slrd_n),
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.sloe_n(sloe_n),
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.slwr_n(slwr_n),
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// .epswitch_n(epswitch_n),
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.pktend_n(pktend_n)
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);
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,71 @@
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create_bd_port -dir I usb_fx3_uart_tx
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create_bd_port -dir O usb_fx3_uart_rx
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create_bd_port -dir I dma_rdy
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create_bd_port -dir I dma_wmk
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create_bd_port -dir I -from 3 -to 0 fifo_rdy
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create_bd_port -dir O pclk
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create_bd_port -dir IO -from 31 -to 0 data
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create_bd_port -dir O -from 1 -to 0 addr
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create_bd_port -dir O slcs_n
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create_bd_port -dir O slrd_n
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create_bd_port -dir O sloe_n
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create_bd_port -dir O slwr_n
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create_bd_port -dir O pktend_n
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create_bd_port -dir O epswitch_n
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set axi_uart [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uart]
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set_property -dict [list CONFIG.C_BAUDRATE {115200}] $axi_uart
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set axi_usb_fx3 [create_bd_cell -type ip -vlnv analog.com:user:axi_usb_fx3:1.0 axi_usb_fx3]
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set axi_usb_fx3_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_dma:7.1 axi_usb_fx3_dma]
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set_property -dict [list CONFIG.c_sg_include_stscntrl_strm {0}] $axi_usb_fx3_dma
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set_property -dict [list CONFIG.c_mm2s_burst_size {256}] $axi_usb_fx3_dma
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set_property -dict [list CONFIG.c_s2mm_burst_size {256}] $axi_usb_fx3_dma
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set_property -dict [list CONFIG.c_sg_length_width {16}] $axi_usb_fx3_dma
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set usb_fx3_rx_axis_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:1.1 usb_fx3_rx_axis_fifo ]
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ad_connect axi_usb_fx3/s_axis axi_usb_fx3_dma/M_AXIS_MM2S
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ad_connect sys_cpu_clk usb_fx3_rx_axis_fifo/s_axis_aclk
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ad_connect sys_cpu_resetn usb_fx3_rx_axis_fifo/s_axis_aresetn
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ad_connect axi_usb_fx3/m_axis usb_fx3_rx_axis_fifo/S_AXIS
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ad_connect axi_usb_fx3_dma/S_AXIS_S2MM usb_fx3_rx_axis_fifo/M_AXIS
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ad_connect axi_uart/rx usb_fx3_uart_tx
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ad_connect axi_uart/tx usb_fx3_uart_rx
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ad_connect sys_cpu_clk axi_usb_fx3/s_axi_aclk
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ad_connect sys_cpu_resetn axi_usb_fx3/s_axi_aresetn
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ad_connect axi_usb_fx3/dma_rdy dma_rdy
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ad_connect axi_usb_fx3/dma_wmk dma_wmk
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ad_connect axi_usb_fx3/fifo_rdy fifo_rdy
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ad_connect axi_usb_fx3/pclk pclk
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ad_connect axi_usb_fx3/data data
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ad_connect axi_usb_fx3/addr addr
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ad_connect axi_usb_fx3/slcs_n slcs_n
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ad_connect axi_usb_fx3/slrd_n slrd_n
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ad_connect axi_usb_fx3/sloe_n sloe_n
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ad_connect axi_usb_fx3/slwr_n slwr_n
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ad_connect axi_usb_fx3/pktend_n pktend_n
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ad_connect axi_usb_fx3/epswitch_n epswitch_n
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ad_cpu_interrupt ps-13 mb-12 axi_usb_fx3/irq
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ad_cpu_interrupt ps-12 mb-13 axi_usb_fx3_dma/mm2s_introut
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ad_cpu_interrupt ps-11 mb-14 axi_usb_fx3_dma/s2mm_introut
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ad_cpu_interrupt ps-10 mb-15 axi_uart/interrupt
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ad_cpu_interconnect 0x50000000 axi_usb_fx3
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ad_cpu_interconnect 0x40400000 axi_usb_fx3_dma
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ad_cpu_interconnect 0x40600000 axi_uart
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ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
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ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_SG
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ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_MM2S
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ad_mem_hp3_interconnect sys_cpu_clk axi_usb_fx3_dma/M_AXI_S2MM
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@ -0,0 +1,71 @@
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# Default constraints have LVCMOS25, overwite it
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#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_scl] ;
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#set_property -dict {IOSTANDARD LVCMOS18} [get_ports iic_sda] ;
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# USB_FX3
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set_property -dict {PACKAGE_PIN T11 IOSTANDARD LVCMOS25} [get_ports data[30]] ;
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set_property -dict {PACKAGE_PIN T10 IOSTANDARD LVCMOS25} [get_ports data[31]] ;
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set_property -dict {PACKAGE_PIN U13 IOSTANDARD LVCMOS25} [get_ports data[24]] ;
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set_property -dict {PACKAGE_PIN V13 IOSTANDARD LVCMOS25} [get_ports data[27]] ;
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set_property -dict {PACKAGE_PIN T14 IOSTANDARD LVCMOS25} [get_ports data[26]] ;
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set_property -dict {PACKAGE_PIN T15 IOSTANDARD LVCMOS25} [get_ports data[21]] ;
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set_property -dict {PACKAGE_PIN Y16 IOSTANDARD LVCMOS25} [get_ports data[18]] ;
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set_property -dict {PACKAGE_PIN Y17 IOSTANDARD LVCMOS25} [get_ports data[19]] ;
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set_property -dict {PACKAGE_PIN T16 IOSTANDARD LVCMOS25} [get_ports data[23]] ;
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set_property -dict {PACKAGE_PIN U17 IOSTANDARD LVCMOS25} [get_ports data[20]] ;
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set_property -dict {PACKAGE_PIN U15 IOSTANDARD LVCMOS25} [get_ports data[2]] ;
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set_property -dict {PACKAGE_PIN N18 IOSTANDARD LVCMOS25} [get_ports data[14]] ;
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set_property -dict {PACKAGE_PIN P19 IOSTANDARD LVCMOS25} [get_ports data[13]] ;
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set_property -dict {PACKAGE_PIN T20 IOSTANDARD LVCMOS25} [get_ports data[9]] ;
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set_property -dict {PACKAGE_PIN U20 IOSTANDARD LVCMOS25} [get_ports data[12]] ;
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set_property -dict {PACKAGE_PIN Y18 IOSTANDARD LVCMOS25} [get_ports data[8]] ;
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set_property -dict {PACKAGE_PIN Y19 IOSTANDARD LVCMOS25} [get_ports data[7]] ;
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set_property -dict {PACKAGE_PIN R16 IOSTANDARD LVCMOS25} [get_ports data[3]] ;
|
||||
set_property -dict {PACKAGE_PIN R17 IOSTANDARD LVCMOS25} [get_ports data[0]] ;
|
||||
set_property -dict {PACKAGE_PIN V17 IOSTANDARD LVCMOS25} [get_ports data[4]] ;
|
||||
set_property -dict {PACKAGE_PIN V18 IOSTANDARD LVCMOS25} [get_ports data[5]] ;
|
||||
set_property -dict {PACKAGE_PIN T12 IOSTANDARD LVCMOS25} [get_ports data[28]] ;
|
||||
set_property -dict {PACKAGE_PIN V12 IOSTANDARD LVCMOS25} [get_ports data[29]] ;
|
||||
set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS25} [get_ports data[25]] ;
|
||||
set_property -dict {PACKAGE_PIN W14 IOSTANDARD LVCMOS25} [get_ports data[22]] ;
|
||||
set_property -dict {PACKAGE_PIN V15 IOSTANDARD LVCMOS25} [get_ports data[16]] ;
|
||||
set_property -dict {PACKAGE_PIN U18 IOSTANDARD LVCMOS25} [get_ports data[17]] ;
|
||||
set_property -dict {PACKAGE_PIN N20 IOSTANDARD LVCMOS25} [get_ports data[15]] ;
|
||||
set_property -dict {PACKAGE_PIN V20 IOSTANDARD LVCMOS25} [get_ports data[11]] ;
|
||||
set_property -dict {PACKAGE_PIN V16 IOSTANDARD LVCMOS25} [get_ports data[10]] ;
|
||||
set_property -dict {PACKAGE_PIN T17 IOSTANDARD LVCMOS25} [get_ports data[6]] ;
|
||||
set_property -dict {PACKAGE_PIN W18 IOSTANDARD LVCMOS25} [get_ports data[1]] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN U14 IOSTANDARD LVCMOS25} [get_ports pclk] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN W16 IOSTANDARD LVCMOS25} [get_ports addr[0]] ;
|
||||
set_property -dict {PACKAGE_PIN W19 IOSTANDARD LVCMOS25} [get_ports addr[1]] ;
|
||||
set_property -dict {PACKAGE_PIN U8 IOSTANDARD LVCMOS25} [get_ports addr[2]] ;
|
||||
set_property -dict {PACKAGE_PIN Y7 IOSTANDARD LVCMOS25} [get_ports addr[3]] ;
|
||||
set_property -dict {PACKAGE_PIN Y8 IOSTANDARD LVCMOS25} [get_ports addr[4]] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN Y6 IOSTANDARD LVCMOS25} [get_ports slcs_n] ;
|
||||
set_property -dict {PACKAGE_PIN W8 IOSTANDARD LVCMOS25} [get_ports slwr_n] ;
|
||||
set_property -dict {PACKAGE_PIN V7 IOSTANDARD LVCMOS25} [get_ports sloe_n] ;
|
||||
set_property -dict {PACKAGE_PIN U7 IOSTANDARD LVCMOS25} [get_ports slrd_n] ;
|
||||
set_property -dict {PACKAGE_PIN W11 IOSTANDARD LVCMOS25} [get_ports pktend_n] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_tx] ;
|
||||
set_property -dict {PACKAGE_PIN U10 IOSTANDARD LVCMOS25} [get_ports usb_fx3_uart_rx] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN V8 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[0]] ;
|
||||
set_property -dict {PACKAGE_PIN Y9 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[1]] ;
|
||||
set_property -dict {PACKAGE_PIN U12 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[2]] ;
|
||||
set_property -dict {PACKAGE_PIN W13 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[3]] ;
|
||||
set_property -dict {PACKAGE_PIN Y14 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[4]] ;
|
||||
set_property -dict {PACKAGE_PIN W15 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[5]] ;
|
||||
set_property -dict {PACKAGE_PIN U19 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[6]] ;
|
||||
set_property -dict {PACKAGE_PIN P20 IOSTANDARD LVCMOS25} [get_ports fifo_rdy[7]] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS25} [get_ports pmode[0]] ;
|
||||
set_property -dict {PACKAGE_PIN T19 IOSTANDARD LVCMOS25} [get_ports pmode[1]] ;
|
||||
set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS25} [get_ports pmode[2]] ;
|
||||
|
||||
set_property -dict {PACKAGE_PIN T9 IOSTANDARD LVCMOS25} [get_ports reset_n] ;
|
||||
set_property -dict {PACKAGE_PIN U9 IOSTANDARD LVCMOS25} [get_ports epswitch_n] ;
|
||||
Loading…
Reference in New Issue