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daq1_zc706 : Update the project 

+ Add AD9684 to the block design
+ Update the IO definitions
+ Update the CPLD design
+ Add 3wire SPI logic
main
Istvan Csomortani 2016-01-19 11:20:35 +02:00
parent d1e638349b
commit 8c69c9d2ce
5 changed files with 291 additions and 513 deletions
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314
projects/daq1/common/daq1_bd.tcl
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@ -1,234 +1,138 @@
# daq1 # ad9122 interface
create_bd_port -dir I rx_ref_clk create_bd_port -dir I dac_clk_in_p
create_bd_port -dir O rx_sync create_bd_port -dir I dac_clk_in_n
create_bd_port -dir I rx_sysref create_bd_port -dir O dac_clk_out_p
create_bd_port -dir I -from 1 -to 0 rx_data_p create_bd_port -dir O dac_clk_out_n
create_bd_port -dir I -from 1 -to 0 rx_data_n create_bd_port -dir O dac_frame_out_p
create_bd_port -dir O dac_frame_out_n
create_bd_port -dir O -from 15 -to 0 dac_data_out_p
create_bd_port -dir O -from 15 -to 0 dac_data_out_n
create_bd_port -dir O dac_clk # ad9684 interface
create_bd_port -dir O dac_valid_0
create_bd_port -dir O dac_enable_0
create_bd_port -dir I -from 63 -to 0 dac_ddata_0
create_bd_port -dir O dac_valid_1
create_bd_port -dir O dac_enable_1
create_bd_port -dir I -from 63 -to 0 dac_ddata_1
create_bd_port -dir I dac_drd
create_bd_port -dir O -from 127 -to 0 dac_ddata
create_bd_port -dir O adc_clk create_bd_port -dir I adc_clk_in_p
create_bd_port -dir O adc_enable_a create_bd_port -dir I adc_clk_in_n
create_bd_port -dir O adc_valid_a create_bd_port -dir I -from 13 -to 0 adc_data_in_p
create_bd_port -dir O -from 31 -to 0 adc_data_a create_bd_port -dir I -from 13 -to 0 adc_data_in_n
create_bd_port -dir O adc_enable_b
create_bd_port -dir O adc_valid_b
create_bd_port -dir O -from 31 -to 0 adc_data_b
create_bd_port -dir I adc_dwr
create_bd_port -dir I adc_dsync
create_bd_port -dir I -from 63 -to 0 adc_ddata
create_bd_port -dir I tx_ref_clk_p # daq1 irq
create_bd_port -dir I tx_ref_clk_n
create_bd_port -dir O tx_clk_p create_bd_port -dir I daq1_irq
create_bd_port -dir O tx_clk_n
create_bd_port -dir O tx_frame_p
create_bd_port -dir O tx_frame_n
create_bd_port -dir O -from 15 -to 0 tx_data_p
create_bd_port -dir O -from 15 -to 0 tx_data_n
# dac peripherals # dac peripherals
create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core set axi_ad9122_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9122:1.0 axi_ad9122_core]
create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma set axi_ad9122_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9122_dma]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_TYPE_SRC {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {2}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_TYPE_DEST {2}] $axi_ad9122_dma
set_property -dict [list CONFIG.ID {1}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.ID {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_CYCLIC {1}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9122_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {128}] [get_bd_cells axi_ad9122_dma] set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma
set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {64}] $util_upack_ad9122
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_upack_ad9122
# adc peripherals # adc peripherals
set axi_ad9250_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9250:1.0 axi_ad9250_core] set axi_ad9684_core [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9684:1.0 axi_ad9684_core]
set_property -dict [list CONFIG.OR_STATUS {0}] $axi_ad9684_core
set axi_ad9250_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:6.0 axi_ad9250_jesd] set axi_ad9684_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9684_dma]
set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_ad9250_jesd set_property -dict [list CONFIG.DMA_TYPE_SRC {2}] $axi_ad9684_dma
set_property -dict [list CONFIG.C_LANES {2}] $axi_ad9250_jesd set_property -dict [list CONFIG.DMA_TYPE_DEST {0}] $axi_ad9684_dma
set_property -dict [list CONFIG.ID {1}] $axi_ad9684_dma
set_property -dict [list CONFIG.AXI_SLICE_SRC {0}] $axi_ad9684_dma
set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma
set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma
set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma
set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9684_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9684_dma
set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9684_dma
set axi_ad9250_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_ad9250_dma] set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684]
set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_ad9250_dma set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9684
set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_ad9250_dma set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] $util_cpack_ad9684
set_property -dict [list CONFIG.ID {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_2D_TRANSFER {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9250_dma
set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_ad9250_dma
# dac/adc common gt/gpio
set axi_daq1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_daq1_gt]
set_property -dict [list CONFIG.PCORE_NUM_OF_RX_LANES {2}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_NUM_OF_TX_LANES {2}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_CPLL_FBDIV {2}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_RX_OUT_DIV {1}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_TX_OUT_DIV {1}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_RX_CLK25_DIV {10}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_TX_CLK25_DIV {10}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_PMA_RSV {0x00018480}] $axi_daq1_gt
set_property -dict [list CONFIG.PCORE_RX_CDR_CFG {0x03000023ff20400020}] $axi_daq1_gt
# additions to default configuration
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP1 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7
set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7
# connections (gt)
ad_connect rx_ref_clk axi_daq1_gt/ref_clk_c
ad_connect rx_data_p axi_daq1_gt/rx_data_p
ad_connect rx_data_n axi_daq1_gt/rx_data_n
ad_connect rx_sync axi_daq1_gt/rx_sync
ad_connect rx_sysref axi_daq1_gt/rx_ext_sysref
ad_connect axi_daq1_gt/tx_clk axi_daq1_gt/tx_clk_g
# connections (adc)
ad_connect axi_daq1_gt/rx_clk_g axi_daq1_gt/rx_clk
ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_core/rx_clk
ad_connect axi_daq1_gt/rx_clk_g axi_ad9250_jesd/rx_core_clk
set util_bsplit_rx_gt_charisk [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_charisk]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_charisk]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_charisk]
ad_connect util_bsplit_rx_gt_charisk/data axi_daq1_gt/rx_gt_charisk
ad_connect util_bsplit_rx_gt_charisk/split_data_0 axi_ad9250_jesd/gt0_rxcharisk
ad_connect util_bsplit_rx_gt_charisk/split_data_1 axi_ad9250_jesd/gt1_rxcharisk
set util_bsplit_gt_rxdisperr [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_gt_rxdisperr]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_gt_rxdisperr]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_gt_rxdisperr]
ad_connect util_bsplit_gt_rxdisperr/data axi_daq1_gt/rx_gt_disperr
ad_connect util_bsplit_gt_rxdisperr/split_data_0 axi_ad9250_jesd/gt0_rxdisperr
ad_connect util_bsplit_gt_rxdisperr/split_data_1 axi_ad9250_jesd/gt1_rxdisperr
set util_bsplit_rx_gt_notintable [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_notintable]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {4}] [get_bd_cells util_bsplit_rx_gt_notintable]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_notintable]
ad_connect util_bsplit_rx_gt_notintable/data axi_daq1_gt/rx_gt_notintable
ad_connect util_bsplit_rx_gt_notintable/split_data_0 axi_ad9250_jesd/gt0_rxnotintable
ad_connect util_bsplit_rx_gt_notintable/split_data_1 axi_ad9250_jesd/gt1_rxnotintable
set util_bsplit_rx_gt_data [create_bd_cell -type ip -vlnv analog.com:user:util_bsplit:1.0 util_bsplit_rx_gt_data]
set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] [get_bd_cells util_bsplit_rx_gt_data]
set_property -dict [list CONFIG.NUM_OF_CHANNELS {2}] [get_bd_cells util_bsplit_rx_gt_data]
ad_connect util_bsplit_rx_gt_data/data axi_daq1_gt/rx_gt_data
ad_connect util_bsplit_rx_gt_data/split_data_0 axi_ad9250_jesd/gt0_rxdata
ad_connect util_bsplit_rx_gt_data/split_data_1 axi_ad9250_jesd/gt1_rxdata
ad_connect axi_daq1_gt/rx_jesd_rst axi_ad9250_jesd/rx_reset
ad_connect axi_daq1_gt/rx_sysref axi_ad9250_jesd/rx_sysref
ad_connect axi_daq1_gt/rx_rst_done axi_ad9250_jesd/rx_reset_done
ad_connect axi_daq1_gt/rx_ip_comma_align axi_ad9250_jesd/rxencommaalign_out
ad_connect axi_daq1_gt/rx_ip_sync axi_ad9250_jesd/rx_sync
ad_connect axi_daq1_gt/rx_ip_sof axi_ad9250_jesd/rx_start_of_frame
ad_connect axi_daq1_gt/rx_ip_data axi_ad9250_jesd/rx_tdata
ad_connect axi_daq1_gt/rx_data axi_ad9250_core/rx_data
ad_connect adc_clk axi_ad9250_core/adc_clk
ad_connect axi_ad9250_core/adc_clk axi_ad9250_dma/fifo_wr_clk
ad_connect adc_enable_a axi_ad9250_core/adc_enable_a
ad_connect adc_valid_a axi_ad9250_core/adc_valid_a
ad_connect adc_data_a axi_ad9250_core/adc_data_a
ad_connect adc_enable_b axi_ad9250_core/adc_enable_b
ad_connect adc_valid_b axi_ad9250_core/adc_valid_b
ad_connect adc_data_b axi_ad9250_core/adc_data_b
ad_connect axi_ad9250_core/adc_dovf axi_ad9250_dma/fifo_wr_overflow
ad_connect adc_dwr axi_ad9250_dma/fifo_wr_en
ad_connect adc_dsync axi_ad9250_dma/fifo_wr_sync
ad_connect adc_ddata axi_ad9250_dma/fifo_wr_din
# connections (dac) # connections (dac)
ad_connect tx_ref_clk_p axi_ad9122_core/dac_clk_in_p ad_connect dac_clk axi_ad9122_core/dac_div_clk
ad_connect tx_ref_clk_n axi_ad9122_core/dac_clk_in_n ad_connect dac_clk axi_ad9122_dma/fifo_rd_clk
ad_connect tx_clk_p axi_ad9122_core/dac_clk_out_p ad_connect dac_clk util_upack_ad9122/dac_clk
ad_connect tx_clk_n axi_ad9122_core/dac_clk_out_n
ad_connect tx_frame_p axi_ad9122_core/dac_frame_out_p
ad_connect tx_frame_n axi_ad9122_core/dac_frame_out_n
ad_connect tx_data_p axi_ad9122_core/dac_data_out_p
ad_connect tx_data_n axi_ad9122_core/dac_data_out_n
ad_connect dac_clk axi_ad9122_core/dac_div_clk
ad_connect axi_ad9122_core/dac_div_clk axi_ad9122_dma/fifo_rd_clk
ad_connect dac_valid_0 axi_ad9122_core/dac_valid_0
ad_connect dac_enable_0 axi_ad9122_core/dac_enable_0
ad_connect dac_ddata_0 axi_ad9122_core/dac_ddata_0
ad_connect dac_valid_1 axi_ad9122_core/dac_valid_1
ad_connect dac_enable_1 axi_ad9122_core/dac_enable_1
ad_connect dac_ddata_1 axi_ad9122_core/dac_ddata_1
ad_connect dac_drd axi_ad9122_dma/fifo_rd_en
ad_connect dac_ddata axi_ad9122_dma/fifo_rd_dout
ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn ad_connect dac_clk_in_p axi_ad9122_core/dac_clk_in_p
ad_connect sys_cpu_resetn axi_ad9250_dma/m_dest_axi_aresetn ad_connect dac_clk_in_n axi_ad9122_core/dac_clk_in_n
ad_connect dac_clk_out_p axi_ad9122_core/dac_clk_out_p
ad_connect dac_clk_out_n axi_ad9122_core/dac_clk_out_n
ad_connect dac_frame_out_p axi_ad9122_core/dac_frame_out_p
ad_connect dac_frame_out_n axi_ad9122_core/dac_frame_out_n
ad_connect dac_data_out_p axi_ad9122_core/dac_data_out_p
ad_connect dac_data_out_n axi_ad9122_core/dac_data_out_n
ad_connect axi_ad9122_core/dac_enable_0 util_upack_ad9122/dac_enable_0
ad_connect axi_ad9122_core/dac_ddata_0 util_upack_ad9122/dac_data_0
ad_connect axi_ad9122_core/dac_valid_0 util_upack_ad9122/dac_valid_0
ad_connect axi_ad9122_core/dac_enable_1 util_upack_ad9122/dac_enable_1
ad_connect axi_ad9122_core/dac_ddata_1 util_upack_ad9122/dac_data_1
ad_connect axi_ad9122_core/dac_valid_1 util_upack_ad9122/dac_valid_1
ad_connect axi_ad9122_core/dac_dunf axi_ad9122_dma/fifo_rd_underflow
# interconnect (cpu) ad_connect util_upack_ad9122/dac_valid axi_ad9122_dma/fifo_rd_en
ad_connect util_upack_ad9122/dac_data axi_ad9122_dma/fifo_rd_dout
ad_connect util_upack_ad9122/dac_sync axi_ad9122_core/dac_sync_in
ad_cpu_interconnect 0x44A60000 axi_daq1_gt # connections (adc)
ad_cpu_interconnect 0x44A00000 axi_ad9122_core
ad_cpu_interconnect 0x7c400000 axi_ad9122_dma
ad_cpu_interconnect 0x44A10000 axi_ad9250_core
ad_cpu_interconnect 0x7c420000 axi_ad9250_dma
ad_cpu_interconnect 0x44A91000 axi_ad9250_jesd
# memory interconnects ad_connect adc_clk axi_ad9684_core/adc_clk
ad_connect sys_200m_clk axi_ad9684_core/delay_clk
ad_connect adc_clk axi_ad9684_dma/fifo_wr_clk
ad_connect adc_clk util_cpack_ad9684/adc_clk
ad_connect adc_clk_in_p axi_ad9684_core/adc_clk_in_p
ad_connect adc_clk_in_n axi_ad9684_core/adc_clk_in_n
ad_connect axi_ad9684_core/adc_data_or_p GND
ad_connect axi_ad9684_core/adc_data_or_n GND
ad_connect adc_data_in_p axi_ad9684_core/adc_data_in_p
ad_connect adc_data_in_n axi_ad9684_core/adc_data_in_n
ad_connect axi_ad9684_core/adc_rst util_cpack_ad9684/adc_rst
ad_connect axi_ad9684_core/adc_enable_0 util_cpack_ad9684/adc_enable_0
ad_connect axi_ad9684_core/adc_valid_0 util_cpack_ad9684/adc_valid_0
ad_connect axi_ad9684_core/adc_data_0 util_cpack_ad9684/adc_data_0
ad_connect axi_ad9684_core/adc_enable_1 util_cpack_ad9684/adc_enable_1
ad_connect axi_ad9684_core/adc_valid_1 util_cpack_ad9684/adc_valid_1
ad_connect axi_ad9684_core/adc_data_1 util_cpack_ad9684/adc_data_1
ad_connect axi_ad9684_core/adc_dovf axi_ad9684_dma/fifo_wr_overflow
ad_connect util_cpack_ad9684/adc_valid axi_ad9684_dma/fifo_wr_en
ad_connect util_cpack_ad9684/adc_data axi_ad9684_dma/fifo_wr_din
ad_connect util_cpack_ad9684/adc_sync axi_ad9684_dma/fifo_wr_sync
# memory interconnect
ad_cpu_interconnect 0x44A00000 axi_ad9122_core
ad_cpu_interconnect 0x44A20000 axi_ad9684_core
ad_cpu_interconnect 0x44A40000 axi_ad9122_dma
ad_cpu_interconnect 0x44A60000 axi_ad9684_dma
ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1 ad_mem_hp1_interconnect sys_200m_clk sys_ps7/S_AXI_HP1
ad_mem_hp1_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi ad_mem_hp1_interconnect sys_200m_clk axi_ad9684_dma/m_dest_axi
ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2 ad_mem_hp2_interconnect sys_200m_clk sys_ps7/S_AXI_HP2
ad_mem_hp2_interconnect sys_200m_clk axi_ad9250_dma/m_dest_axi ad_mem_hp2_interconnect sys_200m_clk axi_ad9122_dma/m_src_axi
ad_mem_hp3_interconnect sys_cpu_clk sys_ps7/S_AXI_HP3
ad_mem_hp3_interconnect sys_cpu_clk axi_daq1_gt/m_axi ad_connect sys_cpu_resetn axi_ad9684_dma/m_dest_axi_aresetn
ad_connect sys_cpu_resetn axi_ad9122_dma/m_src_axi_aresetn
# interrupts # interrupts
ad_cpu_interrupt ps-13 mb-12 axi_ad9250_dma/irq ad_cpu_interrupt ps-13 mb-12 axi_ad9122_dma/irq
ad_cpu_interrupt ps-12 mb-13 axi_ad9122_dma/irq ad_cpu_interrupt ps-12 mb-13 axi_ad9684_dma/irq
ad_cpu_interrupt ps-11 mb-14 daq1_irq
# ila
set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:5.0 ila_jesd_rx_mon]
set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_NUM_OF_PROBES {7} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE0_WIDTH {64} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE1_WIDTH {1} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE2_WIDTH {1} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE3_WIDTH {32} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE4_WIDTH {1} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE5_WIDTH {1} ] $ila_jesd_rx_mon
set_property -dict [list CONFIG.C_PROBE6_WIDTH {32} ] $ila_jesd_rx_mon
ad_connect axi_daq1_gt/rx_clk_g ila_jesd_rx_mon/CLK
ad_connect axi_daq1_gt/rx_data ila_jesd_rx_mon/PROBE0
ad_connect axi_ad9250_core/adc_valid_a ila_jesd_rx_mon/PROBE1
ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE2
ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE3
ad_connect axi_ad9250_core/adc_valid_b ila_jesd_rx_mon/PROBE4
ad_connect axi_ad9250_core/adc_enable_a ila_jesd_rx_mon/PROBE5
ad_connect axi_ad9250_core/adc_data_a ila_jesd_rx_mon/PROBE6

45
projects/daq1/common/daq1_spi.v
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@ -1,9 +1,9 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2016(c) Analog Devices, Inc.
// //
// All rights reserved. // All rights reserved.
// //
// Redistribution and use in source and binary forms, with or without modification, // Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met: // are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright // - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software. // patent holders to use this software.
// - Use of the software either in source or binary form, must be run // - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component. // on or directly connected to an Analog Devices Inc. component.
// //
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, // THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A // INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED. // PARTICULAR PURPOSE ARE DISCLAIMED.
// //
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, // IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY // EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR // RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, // BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF // STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. // THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
@ -48,7 +48,7 @@ module daq1_spi (
// 4 wire // 4 wire
input [ 2:0] spi_csn; input spi_csn;
input spi_clk; input spi_clk;
input spi_mosi; input spi_mosi;
output spi_miso; output spi_miso;
@ -57,11 +57,19 @@ module daq1_spi (
inout spi_sdio; inout spi_sdio;
// device address
localparam [ 7:0] SPI_SEL_AD9684 = 8'h80;
localparam [ 7:0] SPI_SEL_AD9122 = 8'h81;
localparam [ 7:0] SPI_SEL_AD9523 = 8'h82;
localparam [ 7:0] SPI_SEL_CPLD = 8'h83;
// internal registers // internal registers
reg [ 5:0] spi_count = 'd0; reg [ 5:0] spi_count = 6'b0;
reg spi_rd_wr_n = 'd0; reg spi_rd_wr_n = 1'b0;
reg spi_enable = 'd0; reg spi_enable = 1'b0;
reg [ 7:0] spi_device_addr = 8'b0;
// internal signals // internal signals
@ -75,11 +83,15 @@ module daq1_spi (
always @(posedge spi_clk or posedge spi_csn_s) begin always @(posedge spi_clk or posedge spi_csn_s) begin
if (spi_csn_s == 1'b1) begin if (spi_csn_s == 1'b1) begin
spi_count <= 6'd0; spi_count <= 6'b0000000;
spi_rd_wr_n <= 1'd0; spi_rd_wr_n <= 1'b0;
spi_device_addr <= 8'b00000000;
end else begin end else begin
spi_count <= spi_count + 1'b1; spi_count <= spi_count + 1'b1;
if (spi_count == 6'd0) begin if (spi_count <= 6'd7) begin
spi_device_addr <= {spi_device_addr[6:0], spi_mosi};
end
if (spi_count == 6'd8) begin
spi_rd_wr_n <= spi_mosi; spi_rd_wr_n <= spi_mosi;
end end
end end
@ -89,9 +101,10 @@ module daq1_spi (
if (spi_csn_s == 1'b1) begin if (spi_csn_s == 1'b1) begin
spi_enable <= 1'b0; spi_enable <= 1'b0;
end else begin end else begin
if (((spi_count == 6'd16) && (spi_csn[2] == 1'b0)) || if (((spi_device_addr == SPI_SEL_AD9684) && (spi_count == 6'd24)) ||
((spi_count == 6'd8) && (spi_csn[1] == 1'b0)) || ((spi_device_addr == SPI_SEL_AD9122) && (spi_count == 6'd16)) ||
((spi_count == 6'd16) && (spi_csn[0] == 1'b0))) begin ((spi_device_addr == SPI_SEL_AD9523) && (spi_count == 6'd24)) ||
((spi_device_addr == SPI_SEL_CPLD) && (spi_count == 6'd16))) begin
spi_enable <= spi_rd_wr_n; spi_enable <= spi_rd_wr_n;
end end
end end

15
projects/daq1/cpld/daq1_cpld.v
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@ -113,6 +113,7 @@ module daq1_cpld (
localparam [ 6:0] ADC_CONTROL_ADDR = 7'h00; localparam [ 6:0] ADC_CONTROL_ADDR = 7'h00;
localparam [ 6:0] DAC_CONTROL_ADDR = 7'h01; localparam [ 6:0] DAC_CONTROL_ADDR = 7'h01;
localparam [ 6:0] CLK_CONTROL_ADDR = 7'h02; localparam [ 6:0] CLK_CONTROL_ADDR = 7'h02;
localparam [ 6:0] IRQ_MASK_ADDR = 7'h03;
localparam [ 6:0] ADC_STATUS_ADDR = 7'h10; localparam [ 6:0] ADC_STATUS_ADDR = 7'h10;
localparam [ 6:0] DAC_STATUS_ADDR = 7'h11; localparam [ 6:0] DAC_STATUS_ADDR = 7'h11;
localparam [ 6:0] CLK_STATUS_ADDR = 7'h12; localparam [ 6:0] CLK_STATUS_ADDR = 7'h12;
@ -137,6 +138,8 @@ module daq1_cpld (
reg cpld_rdata_bit = 1'b0; reg cpld_rdata_bit = 1'b0;
reg [ 2:0] cpld_rdata_index = 3'h0; reg [ 2:0] cpld_rdata_index = 3'h0;
reg [ 7:0] cpld_wdata = 8'b0; reg [ 7:0] cpld_wdata = 8'b0;
reg [ 7:0] cpld_irq_mask = 8'b0;
reg [ 7:0] cpld_irq = 8'b0;
wire rdnwr; wire rdnwr;
wire cpld_rdata_s; wire cpld_rdata_s;
@ -199,6 +202,8 @@ module daq1_cpld (
cpld_rdata <= dac_resetn; cpld_rdata <= dac_resetn;
CLK_CONTROL_ADDR : CLK_CONTROL_ADDR :
cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn}; cpld_rdata <= {clk_syncn, clk_resetn, clk_pwdnn};
IRQ_MASK_ADDR:
cpld_rdata <= cpld_irq_mask;
ADC_STATUS_ADDR : ADC_STATUS_ADDR :
cpld_rdata <= {adc_status_p, adc_fdb, adc_fda}; cpld_rdata <= {adc_status_p, adc_fdb, adc_fda};
DAC_STATUS_ADDR : DAC_STATUS_ADDR :
@ -235,6 +240,8 @@ module daq1_cpld (
dac_control <= cpld_wdata; dac_control <= cpld_wdata;
CLK_CONTROL_ADDR : CLK_CONTROL_ADDR :
clk_control <= cpld_wdata; clk_control <= cpld_wdata;
IRQ_MASK_ADDR:
cpld_irq_mask <= cpld_wdata;
endcase endcase
end end
end end
@ -265,7 +272,13 @@ module daq1_cpld (
assign clk_resetn = clk_control[1]; assign clk_resetn = clk_control[1];
assign clk_syncn = clk_control[2]; assign clk_syncn = clk_control[2];
assign fmc_irq = dac_irqn; // interrupt logic
always @(*) begin
cpld_irq <= {2'b00, dac_irqn, clk_status2, clk_status1, adc_status_p, adc_fdb, adc_fda};
end
assign fmc_irq = |(~cpld_irq_mask & cpld_irq);
endmodule endmodule

139
projects/daq1/zc706/system_constr.xdc
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@ -1,77 +1,86 @@
# daq1 # daq1
set_property -dict {PACKAGE_PIN AF20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_ref_clk_p] ; ## G06 FMC_HPC_LA00_CC_P set_property -dict {PACKAGE_PIN AC28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_p] ; ## G02 FMC_LPC_CLK1_M2C_P
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports tx_ref_clk_n] ; ## G07 FMC_HPC_LA00_CC_N set_property -dict {PACKAGE_PIN AD28 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports dac_clk_in_n] ; ## G03 FMC_LPC_CLK1_M2C_N
set_property -dict {PACKAGE_PIN AG17 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_p] ; ## H4 FMC_LPC_CLK0_M2C_P
set_property -dict {PACKAGE_PIN AG16 IOSTANDARD LVDS_25 } [get_ports dac_clk_out_n] ; ## H5 FMC_LPC_CLK0_M2C_N
set_property -dict {PACKAGE_PIN V23 IOSTANDARD LVDS_25} [get_ports tx_clk_p] ; ## D20 FMC_HPC_LA17_CC_P set_property -dict {PACKAGE_PIN AB27 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_p] ; ## D20 FMC_LPC_LA17_CC_P
set_property -dict {PACKAGE_PIN W24 IOSTANDARD LVDS_25} [get_ports tx_clk_n] ; ## D21 FMC_HPC_LA17_CC_N set_property -dict {PACKAGE_PIN AC27 IOSTANDARD LVDS_25 } [get_ports dac_frame_out_n] ; ## D21 FMC_LPC_LA17_CC_N
set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVDS_25} [get_ports tx_frame_p] ; ## C22 FMC_HPC_LA18_CC_P
set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVDS_25} [get_ports tx_frame_n] ; ## C23 FMC_HPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS_25} [get_ports tx_data_p[0]] ; ## H10 FMC_HPC_LA04_P
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS_25} [get_ports tx_data_n[0]] ; ## H11 FMC_HPC_LA04_N
set_property -dict {PACKAGE_PIN AH23 IOSTANDARD LVDS_25} [get_ports tx_data_p[1]] ; ## D11 FMC_HPC_LA05_P
set_property -dict {PACKAGE_PIN AH24 IOSTANDARD LVDS_25} [get_ports tx_data_n[1]] ; ## D12 FMC_HPC_LA05_N
set_property -dict {PACKAGE_PIN AG22 IOSTANDARD LVDS_25} [get_ports tx_data_p[2]] ; ## C10 FMC_HPC_LA06_P
set_property -dict {PACKAGE_PIN AH22 IOSTANDARD LVDS_25} [get_ports tx_data_n[2]] ; ## C11 FMC_HPC_LA06_N
set_property -dict {PACKAGE_PIN AJ23 IOSTANDARD LVDS_25} [get_ports tx_data_p[3]] ; ## H13 FMC_HPC_LA07_P
set_property -dict {PACKAGE_PIN AJ24 IOSTANDARD LVDS_25} [get_ports tx_data_n[3]] ; ## H14 FMC_HPC_LA07_N
set_property -dict {PACKAGE_PIN AF19 IOSTANDARD LVDS_25} [get_ports tx_data_p[4]] ; ## G12 FMC_HPC_LA08_P
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS_25} [get_ports tx_data_n[4]] ; ## G13 FMC_HPC_LA08_N
set_property -dict {PACKAGE_PIN AD21 IOSTANDARD LVDS_25} [get_ports tx_data_p[5]] ; ## D14 FMC_HPC_LA09_P
set_property -dict {PACKAGE_PIN AE21 IOSTANDARD LVDS_25} [get_ports tx_data_n[5]] ; ## D15 FMC_HPC_LA09_N
set_property -dict {PACKAGE_PIN AG24 IOSTANDARD LVDS_25} [get_ports tx_data_p[6]] ; ## C14 FMC_HPC_LA10_P
set_property -dict {PACKAGE_PIN AG25 IOSTANDARD LVDS_25} [get_ports tx_data_n[6]] ; ## C15 FMC_HPC_LA10_N
set_property -dict {PACKAGE_PIN AD23 IOSTANDARD LVDS_25} [get_ports tx_data_p[7]] ; ## H16 FMC_HPC_LA11_P
set_property -dict {PACKAGE_PIN AE23 IOSTANDARD LVDS_25} [get_ports tx_data_n[7]] ; ## H17 FMC_HPC_LA11_N
set_property -dict {PACKAGE_PIN AF23 IOSTANDARD LVDS_25} [get_ports tx_data_p[8]] ; ## G15 FMC_HPC_LA12_P
set_property -dict {PACKAGE_PIN AF24 IOSTANDARD LVDS_25} [get_ports tx_data_n[8]] ; ## G16 FMC_HPC_LA12_N
set_property -dict {PACKAGE_PIN AA22 IOSTANDARD LVDS_25} [get_ports tx_data_p[9]] ; ## D17 FMC_HPC_LA13_P
set_property -dict {PACKAGE_PIN AA23 IOSTANDARD LVDS_25} [get_ports tx_data_n[9]] ; ## D18 FMC_HPC_LA13_N
set_property -dict {PACKAGE_PIN AC24 IOSTANDARD LVDS_25} [get_ports tx_data_p[10]] ; ## C18 FMC_HPC_LA14_P
set_property -dict {PACKAGE_PIN AD24 IOSTANDARD LVDS_25} [get_ports tx_data_n[10]] ; ## C19 FMC_HPC_LA14_N
set_property -dict {PACKAGE_PIN Y22 IOSTANDARD LVDS_25} [get_ports tx_data_p[11]] ; ## H19 FMC_HPC_LA15_P
set_property -dict {PACKAGE_PIN Y23 IOSTANDARD LVDS_25} [get_ports tx_data_n[11]] ; ## H20 FMC_HPC_LA15_N
set_property -dict {PACKAGE_PIN AA24 IOSTANDARD LVDS_25} [get_ports tx_data_p[12]] ; ## G18 FMC_HPC_LA16_P
set_property -dict {PACKAGE_PIN AB24 IOSTANDARD LVDS_25} [get_ports tx_data_n[12]] ; ## G19 FMC_HPC_LA16_N
set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVDS_25} [get_ports tx_data_p[13]] ; ## H07 FMC_HPC_LA02_P
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVDS_25} [get_ports tx_data_n[13]] ; ## H08 FMC_HPC_LA02_N
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVDS_25} [get_ports tx_data_p[14]] ; ## D08 FMC_HPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVDS_25} [get_ports tx_data_n[14]] ; ## D09 FMC_HPC_LA01_CC_N
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVDS_25} [get_ports tx_data_p[15]] ; ## G09 FMC_HPC_LA03_P
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVDS_25} [get_ports tx_data_n[15]] ; ## G10 FMC_HPC_LA03_N
set_property -dict {PACKAGE_PIN AD10 } [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P set_property -dict {PACKAGE_PIN AE27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[0]] ; ## C22 FMC_LPC_LA18_CC_P
set_property -dict {PACKAGE_PIN AD9 } [get_ports rx_ref_clk_n] ; ## D05 FMC_HPC_GBTCLK0_M2C_N set_property -dict {PACKAGE_PIN AF27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[0]] ; ## C23 FMC_LPC_LA18_CC_N
set_property -dict {PACKAGE_PIN AH10 } [get_ports rx_data_p[0]] ; ## C06 FMC_HPC_DP0_M2C_P set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[1]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AH9 } [get_ports rx_data_n[0]] ; ## C07 FMC_HPC_DP0_M2C_N set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[1]] ; ## G22 FMC_LPC_LA20_N
set_property -dict {PACKAGE_PIN AJ8 } [get_ports rx_data_p[1]] ; ## A02 FMC_HPC_DP1_M2C_P set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[2]] ; ## H22 FMC_LPC_LA19_P
set_property -dict {PACKAGE_PIN AJ7 } [get_ports rx_data_n[1]] ; ## A03 FMC_HPC_DP1_M2C_N set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[2]] ; ## H23 FMC_LPC_LA19_N
set_property -dict {PACKAGE_PIN T24 IOSTANDARD LVDS_25} [get_ports rx_sync_p] ; ## H22 FMC_HPC_LA19_P set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[3]] ; ## D23 FMC_LPC_LA23_P
set_property -dict {PACKAGE_PIN T25 IOSTANDARD LVDS_25} [get_ports rx_sync_n] ; ## H23 FMC_HPC_LA19_N set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[3]] ; ## D24 FMC_LPC_LA23_N
set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_p] ; ## H25 FMC_HPC_LA21_P set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[4]] ; ## G24 FMC_LPC_LA22_P
set_property -dict {PACKAGE_PIN W30 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_sysref_n] ; ## H26 FMC_HPC_LA21_N set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[4]] ; ## G25 FMC_LPC_LA22_N
set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[5]] ; ## H25 FMC_LPC_LA21_P
set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[5]] ; ## H26 FMC_LPC_LA21_N
set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[6]] ; ## D26 FMC_LPC_LA26_P
set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[6]] ; ## D27 FMC_LPC_LA26_N
set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[7]] ; ## G27 FMC_LPC_LA25_P
set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[7]] ; ## G28 FMC_LPC_LA25_N
set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[8]] ; ## H28 FMC_LPC_LA24_P
set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[8]] ; ## H29 FMC_LPC_LA24_N
set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[9]] ; ## C26 FMC_LPC_LA27_P
set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[9]] ; ## C27 FMC_LPC_LA27_N
set_property -dict {PACKAGE_PIN AE25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[10]] ; ## G30 FMC_LPC_LA29_P
set_property -dict {PACKAGE_PIN AF25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[10]] ; ## G31 FMC_LPC_LA29_N
set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[11]] ; ## H31 FMC_LPC_LA28_P
set_property -dict {PACKAGE_PIN AE26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[11]] ; ## H32 FMC_LPC_LA28_N
set_property -dict {PACKAGE_PIN AC29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[12]] ; ## G33 FMC_LPC_LA31_P
set_property -dict {PACKAGE_PIN AD29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[12]] ; ## G34 FMC_LPC_LA31_N
set_property -dict {PACKAGE_PIN AB29 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[13]] ; ## H34 FMC_LPC_LA30_P
set_property -dict {PACKAGE_PIN AB30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[13]] ; ## H35 FMC_LPC_LA30_N
set_property -dict {PACKAGE_PIN Y30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[14]] ; ## G09 FMC_LPC_LA33_P
set_property -dict {PACKAGE_PIN AA30 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[14]] ; ## G10 FMC_LPC_LA33_N
set_property -dict {PACKAGE_PIN Y26 IOSTANDARD LVDS_25 } [get_ports dac_data_out_p[15]] ; ## H37 FMC_LPC_LA32_P
set_property -dict {PACKAGE_PIN Y27 IOSTANDARD LVDS_25 } [get_ports dac_data_out_n[15]] ; ## H38 FMC_LPC_LA32_N
set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports spi_csn_clk] ; ## G28 FMC_HPC_LA25_N set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_p] ; ## G06 FMC_LPC_LA00_CC_P
set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports spi_csn_dac] ; ## G27 FMC_HPC_LA25_P set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_clk_in_n] ; ## G07 FMC_LPC_LA00_CC_N
set_property -dict {PACKAGE_PIN U30 IOSTANDARD LVCMOS25} [get_ports spi_csn_adc] ; ## H29 FMC_HPC_LA24_N
set_property -dict {PACKAGE_PIN P26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D24 FMC_HPC_LA23_N
set_property -dict {PACKAGE_PIN P25 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## D23 FMC_HPC_LA23_P
set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports gpio_resetn] ; ## G25 FMC_HPC_LA22_N set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[0]] ; ## G12 FMC_LPC_LA08_P
set_property -dict {PACKAGE_PIN R30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_syncn] ; ## H32 FMC_HPC_LA28_N set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[0]] ; ## G13 FMC_LPC_LA08_N
set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_pdn] ; ## H31 FMC_HPC_LA28_P set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[1]] ; ## C18 FMC_LPC_LA14_P
set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[1]] ; ## C19 FMC_LPC_LA14_N
set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[2]] ; ## D17 FMC_LPC_LA13_P
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[2]] ; ## D18 FMC_LPC_LA13_N
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[3]] ; ## H16 FMC_LPC_LA11_P
set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[3]] ; ## H17 FMC_LPC_LA11_N
set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[4]] ; ## G15 FMC_LPC_LA12_P
set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[4]] ; ## G16 FMC_LPC_LA12_N
set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[5]] ; ## D14 FMC_LPC_LA09_P
set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[5]] ; ## D15 FMC_LPC_LA09_N
set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[6]] ; ## H13 FMC_LPC_LA07_P
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[6]] ; ## H14 FMC_LPC_LA07_N
set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[7]] ; ## C14 FMC_LPC_LA10_P
set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[7]] ; ## C15 FMC_LPC_LA10_N
set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[8]] ; ## D11 FMC_LPC_LA05_P
set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[8]] ; ## D12 FMC_LPC_LA05_N
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[9]] ; ## H10 FMC_LPC_LA04_P
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[9]] ; ## H11 FMC_LPC_LA04_N
set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[10]] ; ## G09 FMC_LPC_LA03_P
set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[10]] ; ## G10 FMC_LPC_LA03_N
set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[11]] ; ## C10 FMC_LPC_LA06_P
set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[11]] ; ## C11 FMC_LPC_LA06_N
set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[12]] ; ## H07 FMC_LPC_LA02_P
set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[12]] ; ## H08 FMC_LPC_LA02_N
set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_p[13]] ; ## D08 FMC_LPC_LA01_CC_P
set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports adc_data_in_n[13]] ; ## D09 FMC_LPC_LA01_CC_N
set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[1]] ; ## D27 FMC_HPC_LA26_N set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVCMOS25} [get_ports cpld_sclk] ; ## H19 FMC_LPC_LA15_P
set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_clkd_status[0]] ; ## D26 FMC_HPC_LA26_P set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVCMOS25} [get_ports cpld_csn] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports gpio_dac_irqn] ; ## G24 FMC_HPC_LA22_P set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports cpld_sdio] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN V28 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fda] ; ## C26 FMC_HPC_LA27_P set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports daq1_irq] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN V29 IOSTANDARD LVCMOS25} [get_ports gpio_adc_fdb] ; ## C27 FMC_HPC_LA27_N
# clocks # clocks
create_clock -name tx_ref_clk -period 2.00 [get_ports tx_ref_clk_p] create_clock -name dac_clk_in -period 2.00 [get_ports dac_clk_in_p]
create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p] create_clock -name adc_clk_in -period 2.00 [get_ports adc_clk_in_p]
create_clock -name tx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_ad9122_dac_div_clk]
create_clock -name rx_div_clk -period 8.00 [get_nets i_system_wrapper/system_i/axi_daq1_gt_rx_clk]

291
projects/daq1/zc706/system_top.v
View File

@ -1,6 +1,6 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc. // Copyright 2016(c) Analog Devices, Inc.
// //
// All rights reserved. // All rights reserved.
// //
@ -77,38 +77,26 @@ module system_top (
iic_scl, iic_scl,
iic_sda, iic_sda,
rx_ref_clk_p, dac_clk_in_p,
rx_ref_clk_n, dac_clk_in_n,
rx_sysref_p, dac_clk_out_p,
rx_sysref_n, dac_clk_out_n,
rx_sync_p, dac_frame_out_p,
rx_sync_n, dac_frame_out_n,
rx_data_p, dac_data_out_p,
rx_data_n, dac_data_out_n,
tx_ref_clk_p, adc_clk_in_p,
tx_ref_clk_n, adc_clk_in_n,
tx_clk_p, adc_data_in_p,
tx_clk_n, adc_data_in_n,
tx_frame_p,
tx_frame_n,
tx_data_p,
tx_data_n,
gpio_adc_fdb, daq1_irq,
gpio_adc_fda,
gpio_dac_irqn,
gpio_clkd_status,
gpio_clkd_pdn, cpld_sclk,
gpio_clkd_syncn, cpld_csn,
gpio_resetn, cpld_sdio
);
spi_csn_clk,
spi_csn_dac,
spi_csn_adc,
spi_clk,
spi_sdio);
inout [14:0] ddr_addr; inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba; inout [ 2:0] ddr_ba;
@ -146,176 +134,49 @@ module system_top (
inout iic_scl; inout iic_scl;
inout iic_sda; inout iic_sda;
input rx_ref_clk_p; input dac_clk_in_p;
input rx_ref_clk_n; input dac_clk_in_n;
input rx_sysref_p; output dac_clk_out_p;
input rx_sysref_n; output dac_clk_out_n;
output rx_sync_p; output dac_frame_out_p;
output rx_sync_n; output dac_frame_out_n;
input [ 1:0] rx_data_p; output [15:0] dac_data_out_p;
input [ 1:0] rx_data_n; output [15:0] dac_data_out_n;
input tx_ref_clk_p; input adc_clk_in_p;
input tx_ref_clk_n; input adc_clk_in_n;
output tx_clk_p; input [13:0] adc_data_in_p;
output tx_clk_n; input [13:0] adc_data_in_n;
output tx_frame_p;
output tx_frame_n;
output [15:0] tx_data_p;
output [15:0] tx_data_n;
inout gpio_adc_fdb; input daq1_irq;
inout gpio_adc_fda;
inout gpio_dac_irqn;
inout [ 1:0] gpio_clkd_status;
inout gpio_clkd_pdn; output cpld_sclk;
inout gpio_clkd_syncn; output cpld_csn;
inout gpio_resetn; inout cpld_sdio;
output spi_csn_clk;
output spi_csn_dac;
output spi_csn_adc;
output spi_clk;
inout spi_sdio;
// internal registers
reg dac_drd = 'd0;
reg [63:0] dac_ddata_0 = 'd0;
reg [63:0] dac_ddata_1 = 'd0;
reg adc_dwr = 'd0;
reg [63:0] adc_ddata = 'd0;
// internal signals // internal signals
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
wire [63:0] gpio_t; wire [63:0] gpio_t;
wire rx_ref_clk;
wire rx_sysref;
wire rx_sync;
wire [ 2:0] spi_csn;
wire adc_clk;
wire [31:0] adc_data_a;
wire [31:0] adc_data_b;
wire adc_enable_a;
wire adc_enable_b;
wire dac_clk;
wire [127:0] dac_ddata;
wire dac_enable_0;
wire dac_enable_1;
// pack & unpack data
always @(posedge dac_clk) begin
case ({dac_enable_1, dac_enable_0})
2'b11: begin
dac_drd <= 1'b1;
dac_ddata_1[63:48] <= dac_ddata[127:112];
dac_ddata_1[47:32] <= dac_ddata[ 95: 80];
dac_ddata_1[31:16] <= dac_ddata[ 63: 48];
dac_ddata_1[15: 0] <= dac_ddata[ 31: 16];
dac_ddata_0[63:48] <= dac_ddata[111: 96];
dac_ddata_0[47:32] <= dac_ddata[ 79: 64];
dac_ddata_0[31:16] <= dac_ddata[ 47: 32];
dac_ddata_0[15: 0] <= dac_ddata[ 15: 0];
end
2'b01: begin
dac_drd <= ~dac_drd;
dac_ddata_1 <= 64'd0;
dac_ddata_0 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
end
2'b10: begin
dac_drd <= ~dac_drd;
dac_ddata_1 <= (dac_drd == 1'b1) ? dac_ddata[127:64] : dac_ddata[63:0];
dac_ddata_0 <= 64'd0;
end
default: begin
dac_drd <= 1'b0;
dac_ddata_1 <= 64'd0;
dac_ddata_0 <= 64'd0;
end
endcase
end
always @(posedge adc_clk) begin
case ({adc_enable_b, adc_enable_a})
2'b11: begin
adc_dwr <= 1'b1;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_a[31:16];
adc_ddata[31:16] <= adc_data_b[15: 0];
adc_ddata[15: 0] <= adc_data_a[15: 0];
end
2'b10: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_b[31:16];
adc_ddata[47:32] <= adc_data_b[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
2'b01: begin
adc_dwr <= ~adc_dwr;
adc_ddata[63:48] <= adc_data_a[31:16];
adc_ddata[47:32] <= adc_data_a[15: 0];
adc_ddata[31:16] <= adc_ddata[63:48];
adc_ddata[15: 0] <= adc_ddata[47:32];
end
default: begin
adc_dwr <= 1'b0;
adc_ddata[63:48] <= 16'd0;
adc_ddata[47:32] <= 16'd0;
adc_ddata[31:16] <= 16'd0;
adc_ddata[15: 0] <= 16'd0;
end
endcase
end
// instantiations // instantiations
assign spi_csn_adc = spi_csn[2]; ad_iobuf #(
assign spi_csn_dac = spi_csn[1]; .DATA_WIDTH(15)
assign spi_csn_clk = spi_csn[0]; ) i_gpio_bd (
.dio_t(gpio_t[14:0]),
// instantiations .dio_i(gpio_o[14:0]),
.dio_o(gpio_i[14:0]),
IBUFDS_GTE2 i_ibufds_rx_ref_clk ( .dio_p(gpio_bd));
.CEB (1'd0),
.I (rx_ref_clk_p),
.IB (rx_ref_clk_n),
.O (rx_ref_clk),
.ODIV2 ());
IBUFDS i_ibufds_rx_sysref (
.I (rx_sysref_p),
.IB (rx_sysref_n),
.O (rx_sysref));
OBUFDS i_obufds_rx_sync (
.I (rx_sync),
.O (rx_sync_p),
.OB (rx_sync_n));
daq1_spi i_spi ( daq1_spi i_spi (
.spi_csn (spi_csn), .spi_csn(cpld_csn),
.spi_clk (spi_clk), .spi_clk(cpld_sclk),
.spi_mosi (spi_mosi), .spi_mosi(cpld_mosi),
.spi_miso (spi_miso), .spi_miso(cpld_miso),
.spi_sdio (spi_sdio)); .spi_sdio(cpld_sdio)
);
ad_iobuf #(.DATA_WIDTH(23)) i_iobuf (
.dio_t({gpio_t[39:32], gpio_t[14:0]}),
.dio_i({gpio_o[39:32], gpio_o[14:0]}),
.dio_o({gpio_i[39:32], gpio_i[14:0]}),
.dio_p({gpio_adc_fdb, // 39
gpio_adc_fda, // 38
gpio_dac_irqn, // 37
gpio_clkd_status, // 36:35
gpio_clkd_pdn, // 34
gpio_clkd_syncn, // 33
gpio_resetn, // 32
gpio_bd})); // 14:0
system_wrapper i_system_wrapper ( system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr), .ddr_addr (ddr_addr),
@ -342,25 +203,6 @@ module system_top (
.gpio_i (gpio_i), .gpio_i (gpio_i),
.gpio_o (gpio_o), .gpio_o (gpio_o),
.gpio_t (gpio_t), .gpio_t (gpio_t),
.adc_clk (adc_clk),
.adc_data_a (adc_data_a),
.adc_data_b (adc_data_b),
.adc_ddata (adc_ddata),
.adc_dsync (1'b1),
.adc_dwr (adc_dwr),
.adc_enable_a (adc_enable_a),
.adc_enable_b (adc_enable_b),
.adc_valid_a (),
.adc_valid_b (),
.dac_clk (dac_clk),
.dac_ddata (dac_ddata),
.dac_ddata_0 (dac_ddata_0),
.dac_ddata_1 (dac_ddata_1),
.dac_drd (dac_drd),
.dac_enable_0 (dac_enable_0),
.dac_enable_1 (dac_enable_1),
.dac_valid_0 (),
.dac_valid_1 (),
.hdmi_data (hdmi_data), .hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e), .hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync), .hdmi_hsync (hdmi_hsync),
@ -370,8 +212,6 @@ module system_top (
.iic_main_sda_io (iic_sda), .iic_main_sda_io (iic_sda),
.ps_intr_00 (1'b0), .ps_intr_00 (1'b0),
.ps_intr_01 (1'b0), .ps_intr_01 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_11 (1'b0),
.ps_intr_02 (1'b0), .ps_intr_02 (1'b0),
.ps_intr_03 (1'b0), .ps_intr_03 (1'b0),
.ps_intr_04 (1'b0), .ps_intr_04 (1'b0),
@ -380,29 +220,28 @@ module system_top (
.ps_intr_07 (1'b0), .ps_intr_07 (1'b0),
.ps_intr_08 (1'b0), .ps_intr_08 (1'b0),
.ps_intr_09 (1'b0), .ps_intr_09 (1'b0),
.rx_data_n (rx_data_n), .ps_intr_10 (1'b0),
.rx_data_p (rx_data_p),
.rx_ref_clk (rx_ref_clk),
.rx_sync (rx_sync),
.rx_sysref (rx_sysref),
.spdif (spdif), .spdif (spdif),
.spi0_clk_i (1'b0), .spi0_clk_i (1'b0),
.spi0_clk_o (spi_clk), .spi0_clk_o (cpld_sclk),
.spi0_csn_0_o (spi_csn[0]), .spi0_csn_0_o (cpld_csn),
.spi0_csn_1_o (spi_csn[1]),
.spi0_csn_2_o (spi_csn[2]),
.spi0_csn_i (1'b1), .spi0_csn_i (1'b1),
.spi0_sdi_i (spi_miso), .spi0_sdi_i (cpld_miso),
.spi0_sdo_i (1'b0), .spi0_sdo_i (1'b0),
.spi0_sdo_o (spi_mosi), .spi0_sdo_o (cpld_mosi),
.tx_clk_n (tx_clk_n), .dac_clk_in_p (dac_clk_in_p),
.tx_clk_p (tx_clk_p), .dac_clk_in_n (dac_clk_in_n),
.tx_data_n (tx_data_n), .dac_clk_out_p (dac_clk_out_p),
.tx_data_p (tx_data_p), .dac_clk_out_n (dac_clk_out_n),
.tx_frame_n (tx_frame_n), .dac_frame_out_p (dac_frame_out_p),
.tx_frame_p (tx_frame_p), .dac_frame_out_n (dac_frame_out_n),
.tx_ref_clk_n (tx_ref_clk_n), .dac_data_out_p (dac_data_out_p),
.tx_ref_clk_p (tx_ref_clk_p)); .dac_data_out_n (dac_data_out_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_clk_in_n (adc_clk_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_in_n (adc_data_in_n),
.daq1_irq (daq1_irq));
endmodule endmodule