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ad9671: Fixed constraints. Modified system_timing.tcl so that it will fail if timing are not met

main
Adrian Costina 2014-10-29 18:25:56 +02:00
parent fbce64411e
commit 8c789104a6
2 changed files with 34 additions and 24 deletions
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41
projects/ad9671_fmc/a5gt/system_constr.sdc
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@ -1,32 +1,29 @@
create_clock -period "10.000 ns" -name n_clk_100m [get_ports {sys_clk}]
create_clock -period "4.000 ns" -name n_clk_250m [get_ports {ref_clk}]
create_clock -period "12.500 ns" -name n_clk_ref [get_ports {ref_clk}]
create_clock -period "8.000 ns" -name n_eth_rx_clk_125m [get_ports {eth_rx_clk}]
create_clock -period "8.000 ns" -name n_eth_tx_clk_125m [get_nets {eth_tx_clk}]
derive_pll_clocks
derive_clock_uncertainty
set clk_100m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_166m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_125m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_25m [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_2m5 [get_clocks {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_rxlink [get_clocks {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}]
set clk_100m {i_system_bd|sys_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_166m {i_system_bd|sys_pll|altera_pll_i|general[1].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_125m {i_system_bd|sys_pll|altera_pll_i|general[2].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_25m {i_system_bd|sys_pll|altera_pll_i|general[3].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_2m5 {i_system_bd|sys_pll|altera_pll_i|general[4].gpll~PLL_OUTPUT_COUNTER|divclk}
set clk_rxlink {i_system_bd|sys_jesd204b_s1_pll|altera_pll_i|general[0].gpll~PLL_OUTPUT_COUNTER|divclk}
set_clock_groups -asynchronous -group [get_clocks {n_clk_ref} ]
set_clock_groups -asynchronous -group [get_clocks {n_clk_100m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_rx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks {n_eth_tx_clk_125m} ]
set_clock_groups -asynchronous -group [get_clocks $clk_100m ]
set_clock_groups -asynchronous -group [get_clocks $clk_166m ]
set_clock_groups -asynchronous -group [get_clocks $clk_125m ]
set_clock_groups -asynchronous -group [get_clocks $clk_25m ]
set_clock_groups -asynchronous -group [get_clocks $clk_2m5 ]
set_clock_groups -asynchronous -group [get_clocks $clk_rxlink ]
set_false_path -from {sys_resetn} -to *
set_false_path -from $clk_100m -to $clk_166m
set_false_path -from $clk_100m -to $clk_rxlink
set_false_path -from $clk_166m -to $clk_100m
set_false_path -from $clk_166m -to $clk_rxlink
set_false_path -from $clk_rxlink -to $clk_100m
set_false_path -from $clk_rxlink -to $clk_166m
set_false_path -from $clk_125m -to $clk_25m
set_false_path -from $clk_125m -to $clk_2m5
set_false_path -from $clk_25m -to $clk_125m
set_false_path -from $clk_25m -to $clk_2m5
set_false_path -from $clk_2m5 -to $clk_125m
set_false_path -from $clk_2m5 -to $clk_25m
set_false_path -from * -to {sys_resetn}

17
projects/ad9671_fmc/a5gt/system_timing.tcl
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@ -1,3 +1,16 @@
report_timing -detail path_only -npaths 20 -file timing_impl.log
set worst_path [get_timing_paths -npaths 1 -setup]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
if {$slack > 0} {
set worst_path [get_timing_paths -npaths 1 -hold]
foreach_in_collection path $worst_path {
set slack [get_path_info $path -slack]
}
}
if {$slack < 0} {
use_this_invalid_command_to_crash
}