diff --git a/projects/ad9081_fmca_ebz/vck190/Makefile b/projects/ad9081_fmca_ebz/vck190/Makefile new file mode 100644 index 000000000..0caddb158 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vck190/Makefile @@ -0,0 +1,46 @@ +#################################################################################### +## Copyright (c) 2018 - 2021 Analog Devices, Inc. +### SPDX short identifier: BSD-1-Clause +## Auto-generated, do not modify! +#################################################################################### + +PROJECT_NAME := ad9081_fmca_ebz_vck190 + +M_DEPS += timing_constr.xdc +M_DEPS += ../../../library/common/ad_edge_detect.v +M_DEPS += ../../scripts/adi_pd.tcl +M_DEPS += ../../common/xilinx/data_offload_bd.tcl +M_DEPS += ../../common/xilinx/dacfifo_bd.tcl +M_DEPS += ../../common/xilinx/adcfifo_bd.tcl +M_DEPS += ../../common/vmk180/vmk180_system_bd.tcl +M_DEPS += ../../common/vck190/vck190_system_constr.xdc +M_DEPS += ../../common/vck190/vck190_system_bd.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/versal_transceiver.tcl +M_DEPS += ../../ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +M_DEPS += ../../../library/jesd204/scripts/jesd204.tcl +M_DEPS += ../../../library/common/ad_iobuf.v +M_DEPS += ../../../library/common/ad_3w_spi.v + +LIB_DEPS += axi_dmac +LIB_DEPS += axi_sysid +LIB_DEPS += axi_tdd +LIB_DEPS += data_offload +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc +LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac +LIB_DEPS += jesd204/axi_jesd204_rx +LIB_DEPS += jesd204/axi_jesd204_tx +LIB_DEPS += jesd204/jesd204_rx +LIB_DEPS += jesd204/jesd204_tx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_rx +LIB_DEPS += jesd204/jesd204_versal_gt_adapter_tx +LIB_DEPS += sysid_rom +LIB_DEPS += util_adcfifo +LIB_DEPS += util_dacfifo +LIB_DEPS += util_fifo2axi_bridge +LIB_DEPS += util_pack/util_cpack2 +LIB_DEPS += util_pack/util_upack2 +LIB_DEPS += util_tdd_sync +LIB_DEPS += xilinx/axi_adxcvr +LIB_DEPS += xilinx/util_adxcvr + +include ../../scripts/project-xilinx.mk diff --git a/projects/ad9081_fmca_ebz/vck190/system_bd.tcl b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl new file mode 100644 index 000000000..f219be240 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vck190/system_bd.tcl @@ -0,0 +1,23 @@ + +## ADC FIFO depth in samples per converter +set adc_fifo_samples_per_converter [expr $ad_project_params(RX_KS_PER_CHANNEL)*1024] +## DAC FIFO depth in samples per converter +set dac_fifo_samples_per_converter [expr $ad_project_params(TX_KS_PER_CHANNEL)*1024] + +source $ad_hdl_dir/projects/common/vck190/vck190_system_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/adcfifo_bd.tcl +source $ad_hdl_dir/projects/common/xilinx/dacfifo_bd.tcl + +# use versal transceiver wizard +set ADI_PHY_SEL 0 + +source $ad_hdl_dir/projects/ad9081_fmca_ebz/common/ad9081_fmca_ebz_bd.tcl +source $ad_hdl_dir/projects/scripts/adi_pd.tcl + +#system ID +ad_ip_parameter axi_sysid_0 CONFIG.ROM_ADDR_BITS 9 +ad_ip_parameter rom_sys_0 CONFIG.PATH_TO_FILE "[pwd]/mem_init_sys.txt" +ad_ip_parameter rom_sys_0 CONFIG.ROM_ADDR_BITS 9 + +sysid_gen_sys_init_file + diff --git a/projects/ad9081_fmca_ebz/vck190/system_constr.xdc b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc new file mode 100644 index 000000000..c57e84aed --- /dev/null +++ b/projects/ad9081_fmca_ebz/vck190/system_constr.xdc @@ -0,0 +1,88 @@ +# +## mxfe +# + +set_property -dict {PACKAGE_PIN BB16 IOSTANDARD LVCMOS15 } [get_ports agc0[0] ] ; ## FMC0_LA17_CC_P IO_L13P_T2L_N0_GC_QBC_67 +set_property -dict {PACKAGE_PIN BC16 IOSTANDARD LVCMOS15 } [get_ports agc0[1] ] ; ## FMC0_LA17_CC_N IO_L13N_T2L_N1_GC_QBC_67 +set_property -dict {PACKAGE_PIN BE17 IOSTANDARD LVCMOS15 } [get_ports agc1[0] ] ; ## FMC0_LA18_CC_P IO_L16P_T2U_N6_QBC_AD3P_67 +set_property -dict {PACKAGE_PIN BD17 IOSTANDARD LVCMOS15 } [get_ports agc1[1] ] ; ## FMC0_LA18_CC_N IO_L16N_T2U_N7_QBC_AD3N_67 +set_property -dict {PACKAGE_PIN BE16 IOSTANDARD LVCMOS15 } [get_ports agc2[0] ] ; ## FMC0_LA20_P IO_L22P_T3U_N6_DBC_AD0P_67 +set_property -dict {PACKAGE_PIN BF17 IOSTANDARD LVCMOS15 } [get_ports agc2[1] ] ; ## FMC0_LA20_N IO_L22N_T3U_N7_DBC_AD0N_67 +set_property -dict {PACKAGE_PIN BE19 IOSTANDARD LVCMOS15 } [get_ports agc3[0] ] ; ## FMC0_LA21_P IO_L21P_T3L_N4_AD8P_67 +set_property -dict {PACKAGE_PIN BD19 IOSTANDARD LVCMOS15 } [get_ports agc3[1] ] ; ## FMC0_LA21_N IO_L21N_T3L_N5_AD8N_67 +set_property -dict {PACKAGE_PIN BD24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_n ] ; ## FMC0_CLK2_IO_N IO_L13N_T2L_N1_GC_QBC_66 +set_property -dict {PACKAGE_PIN BD23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin10_p ] ; ## FMC0_CLK2_IO_P IO_L13P_T2L_N0_GC_QBC_66 +set_property -dict {PACKAGE_PIN AP18 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin6_n ] ; ## FMC0_CLK1_M2C_N IO_L12N_T1U_N11_GC_67 +set_property -dict {PACKAGE_PIN AP19 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports clkin6_p ] ; ## FMC0_CLK1_M2C_P IO_L12P_T1U_N10_GC_67 +set_property -dict {PACKAGE_PIN M14 } [get_ports fpga_refclk_in_n ] ; ## FMC0_GBTCLK0_M2C_N MGTREFCLK0N_229 +set_property -dict {PACKAGE_PIN M15 } [get_ports fpga_refclk_in_p ] ; ## FMC0_GBTCLK0_M2C_P MGTREFCLK0P_229 +set_property -quiet -dict {PACKAGE_PIN Y1 } [get_ports rx_data_n[2] ] ; ## FMC0_DP2_M2C_N MGTHRXN3_229 FPGA_SERDIN_0_N +set_property -quiet -dict {PACKAGE_PIN Y2 } [get_ports rx_data_p[2] ] ; ## FMC0_DP2_M2C_P MGTHRXP3_229 FPGA_SERDIN_0_P +set_property -quiet -dict {PACKAGE_PIN AB1 } [get_ports rx_data_n[0] ] ; ## FMC0_DP0_M2C_N MGTHRXN2_229 FPGA_SERDIN_1_N +set_property -quiet -dict {PACKAGE_PIN AB2 } [get_ports rx_data_p[0] ] ; ## FMC0_DP0_M2C_P MGTHRXP2_229 FPGA_SERDIN_1_P +set_property -quiet -dict {PACKAGE_PIN R3 } [get_ports rx_data_n[7] ] ; ## FMC0_DP7_M2C_N MGTHRXN2_228 FPGA_SERDIN_2_N +set_property -quiet -dict {PACKAGE_PIN R4 } [get_ports rx_data_p[7] ] ; ## FMC0_DP7_M2C_P MGTHRXP2_228 FPGA_SERDIN_2_P +set_property -quiet -dict {PACKAGE_PIN T1 } [get_ports rx_data_n[6] ] ; ## FMC0_DP6_M2C_N MGTHRXN0_228 FPGA_SERDIN_3_N +set_property -quiet -dict {PACKAGE_PIN T2 } [get_ports rx_data_p[6] ] ; ## FMC0_DP6_M2C_P MGTHRXP0_228 FPGA_SERDIN_3_P +set_property -quiet -dict {PACKAGE_PIN U3 } [get_ports rx_data_n[5] ] ; ## FMC0_DP5_M2C_N MGTHRXN1_228 FPGA_SERDIN_4_N +set_property -quiet -dict {PACKAGE_PIN U4 } [get_ports rx_data_p[5] ] ; ## FMC0_DP5_M2C_P MGTHRXP1_228 FPGA_SERDIN_4_P +set_property -quiet -dict {PACKAGE_PIN V1 } [get_ports rx_data_n[4] ] ; ## FMC0_DP4_M2C_N MGTHRXN3_228 FPGA_SERDIN_5_N +set_property -quiet -dict {PACKAGE_PIN V2 } [get_ports rx_data_p[4] ] ; ## FMC0_DP4_M2C_P MGTHRXP3_228 FPGA_SERDIN_5_P +set_property -quiet -dict {PACKAGE_PIN W3 } [get_ports rx_data_n[3] ] ; ## FMC0_DP3_M2C_N MGTHRXN0_229 FPGA_SERDIN_6_N +set_property -quiet -dict {PACKAGE_PIN W4 } [get_ports rx_data_p[3] ] ; ## FMC0_DP3_M2C_P MGTHRXP0_229 FPGA_SERDIN_6_P +set_property -quiet -dict {PACKAGE_PIN AA3 } [get_ports rx_data_n[1] ] ; ## FMC0_DP1_M2C_N MGTHRXN1_229 FPGA_SERDIN_7_N +set_property -quiet -dict {PACKAGE_PIN AA4 } [get_ports rx_data_p[1] ] ; ## FMC0_DP1_M2C_P MGTHRXP1_229 FPGA_SERDIN_7_P +set_property -quiet -dict {PACKAGE_PIN AB6 } [get_ports tx_data_n[0] ] ; ## FMC0_DP0_C2M_N MGTHTXN2_229 FPGA_SERDOUT_0_N +set_property -quiet -dict {PACKAGE_PIN AB7 } [get_ports tx_data_p[0] ] ; ## FMC0_DP0_C2M_P MGTHTXP2_229 FPGA_SERDOUT_0_P +set_property -quiet -dict {PACKAGE_PIN Y6 } [get_ports tx_data_n[2] ] ; ## FMC0_DP2_C2M_N MGTHTXN3_229 FPGA_SERDOUT_1_N +set_property -quiet -dict {PACKAGE_PIN Y7 } [get_ports tx_data_p[2] ] ; ## FMC0_DP2_C2M_P MGTHTXP3_229 FPGA_SERDOUT_1_P +set_property -quiet -dict {PACKAGE_PIN R8 } [get_ports tx_data_n[7] ] ; ## FMC0_DP7_C2M_N MGTHTXN2_228 FPGA_SERDOUT_2_N +set_property -quiet -dict {PACKAGE_PIN R9 } [get_ports tx_data_p[7] ] ; ## FMC0_DP7_C2M_P MGTHTXP2_228 FPGA_SERDOUT_2_P +set_property -quiet -dict {PACKAGE_PIN T6 } [get_ports tx_data_n[6] ] ; ## FMC0_DP6_C2M_N MGTHTXN0_228 FPGA_SERDOUT_3_N +set_property -quiet -dict {PACKAGE_PIN T7 } [get_ports tx_data_p[6] ] ; ## FMC0_DP6_C2M_P MGTHTXP0_228 FPGA_SERDOUT_3_P +set_property -quiet -dict {PACKAGE_PIN AA8 } [get_ports tx_data_n[1] ] ; ## FMC0_DP1_C2M_N MGTHTXN1_229 FPGA_SERDOUT_4_N +set_property -quiet -dict {PACKAGE_PIN AA9 } [get_ports tx_data_p[1] ] ; ## FMC0_DP1_C2M_P MGTHTXP1_229 FPGA_SERDOUT_4_P +set_property -quiet -dict {PACKAGE_PIN U8 } [get_ports tx_data_n[5] ] ; ## FMC0_DP5_C2M_N MGTHTXN1_228 FPGA_SERDOUT_5_N +set_property -quiet -dict {PACKAGE_PIN U9 } [get_ports tx_data_p[5] ] ; ## FMC0_DP5_C2M_P MGTHTXP1_228 FPGA_SERDOUT_5_P +set_property -quiet -dict {PACKAGE_PIN V6 } [get_ports tx_data_n[4] ] ; ## FMC0_DP4_C2M_N MGTHTXN3_228 FPGA_SERDOUT_6_N +set_property -quiet -dict {PACKAGE_PIN V7 } [get_ports tx_data_p[4] ] ; ## FMC0_DP4_C2M_P MGTHTXP3_228 FPGA_SERDOUT_6_P +set_property -quiet -dict {PACKAGE_PIN W8 } [get_ports tx_data_n[3] ] ; ## FMC0_DP3_C2M_N MGTHTXN0_229 FPGA_SERDOUT_7_N +set_property -quiet -dict {PACKAGE_PIN W9 } [get_ports tx_data_p[3] ] ; ## FMC0_DP3_C2M_P MGTHTXP0_229 FPGA_SERDOUT_7_P +set_property -quiet -dict {PACKAGE_PIN AY25 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[0] ] ; ## FMC0_LA02_N IO_L23N_T3U_N9_66 +set_property -quiet -dict {PACKAGE_PIN AW24 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[0] ] ; ## FMC0_LA02_P IO_L23P_T3U_N8_66 +set_property -quiet -dict {PACKAGE_PIN AW21 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_n[1] ] ; ## FMC0_LA03_N IO_L22N_T3U_N7_DBC_AD0N_66 +set_property -quiet -dict {PACKAGE_PIN AV22 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports fpga_syncin_p[1] ] ; ## FMC0_LA03_P IO_L22P_T3U_N6_DBC_AD0P_66 +set_property -quiet -dict {PACKAGE_PIN BD22 IOSTANDARD LVDS15 } [get_ports fpga_syncout_n[0]] ; ## FMC0_LA01_CC_N IO_L16N_T2U_N7_QBC_AD3N_66 +set_property -quiet -dict {PACKAGE_PIN BC23 IOSTANDARD LVDS15 } [get_ports fpga_syncout_p[0]] ; ## FMC0_LA01_CC_P IO_L16P_T2U_N6_QBC_AD3P_66 +set_property -quiet -dict {PACKAGE_PIN BD20 IOSTANDARD LVDS15 } [get_ports fpga_syncout_n[1]] ; ## FMC0_LA06_N IO_L19N_T3L_N1_DBC_AD9N_66 +set_property -quiet -dict {PACKAGE_PIN BC20 IOSTANDARD LVDS15 } [get_ports fpga_syncout_p[1]] ; ## FMC0_LA06_P IO_L19P_T3L_N0_DBC_AD9P_66 +set_property -dict {PACKAGE_PIN AY22 IOSTANDARD LVCMOS15 } [get_ports gpio[0] ] ; ## FMC0_LA15_P IO_L6P_T0U_N10_AD6P_66 +set_property -dict {PACKAGE_PIN AY23 IOSTANDARD LVCMOS15 } [get_ports gpio[1] ] ; ## FMC0_LA15_N IO_L6N_T0U_N11_AD6N_66 +set_property -dict {PACKAGE_PIN BA17 IOSTANDARD LVCMOS15 } [get_ports gpio[2] ] ; ## FMC0_LA19_P IO_L23P_T3U_N8_67 +set_property -dict {PACKAGE_PIN BA16 IOSTANDARD LVCMOS15 } [get_ports gpio[3] ] ; ## FMC0_LA19_N IO_L23N_T3U_N9_67 +set_property -dict {PACKAGE_PIN BE21 IOSTANDARD LVCMOS15 } [get_ports gpio[4] ] ; ## FMC0_LA13_P IO_L8P_T1L_N2_AD5P_66 +set_property -dict {PACKAGE_PIN BE20 IOSTANDARD LVCMOS15 } [get_ports gpio[5] ] ; ## FMC0_LA13_N IO_L8N_T1L_N3_AD5N_66 +set_property -dict {PACKAGE_PIN AU24 IOSTANDARD LVCMOS15 } [get_ports gpio[6] ] ; ## FMC0_LA14_P IO_L7P_T1L_N0_QBC_AD13P_66 +set_property -dict {PACKAGE_PIN AU23 IOSTANDARD LVCMOS15 } [get_ports gpio[7] ] ; ## FMC0_LA14_N IO_L7N_T1L_N1_QBC_AD13N_66 +set_property -dict {PACKAGE_PIN BF21 IOSTANDARD LVCMOS15 } [get_ports gpio[8] ] ; ## FMC0_LA16_P IO_L5P_T0U_N8_AD14P_66 +set_property -dict {PACKAGE_PIN BG20 IOSTANDARD LVCMOS15 } [get_ports gpio[9] ] ; ## FMC0_LA16_N IO_L5N_T0U_N9_AD14N_66 +set_property -dict {PACKAGE_PIN BG18 IOSTANDARD LVCMOS15 } [get_ports gpio[10] ] ; ## FMC0_LA22_N IO_L20N_T3L_N3_AD1N_67 +set_property -dict {PACKAGE_PIN BE22 IOSTANDARD LVCMOS15 } [get_ports hmc_gpio1 ] ; ## FMC0_LA11_N IO_L10N_T1U_N7_QBC_AD4N_66 +set_property -dict {PACKAGE_PIN BD25 IOSTANDARD LVCMOS15 } [get_ports hmc_sync ] ; ## FMC0_LA07_N IO_L18N_T2U_N11_AD2N_66 +set_property -dict {PACKAGE_PIN BC22 IOSTANDARD LVCMOS15 } [get_ports irqb[0] ] ; ## FMC0_LA08_P IO_L17P_T2U_N8_AD10P_66 +set_property -dict {PACKAGE_PIN BC21 IOSTANDARD LVCMOS15 } [get_ports irqb[1] ] ; ## FMC0_LA08_N IO_L17N_T2U_N9_AD10N_66 +set_property -dict {PACKAGE_PIN BC25 IOSTANDARD LVCMOS15 } [get_ports rstb ] ; ## FMC0_LA07_P IO_L18P_T2U_N10_AD2P_66 +set_property -dict {PACKAGE_PIN BG25 IOSTANDARD LVCMOS15 } [get_ports rxen[0] ] ; ## FMC0_LA10_P IO_L15P_T2L_N4_AD11P_66 +set_property -dict {PACKAGE_PIN BG24 IOSTANDARD LVCMOS15 } [get_ports rxen[1] ] ; ## FMC0_LA10_N IO_L15N_T2L_N5_AD11N_66 +set_property -dict {PACKAGE_PIN BF24 IOSTANDARD LVCMOS15 } [get_ports spi0_csb ] ; ## FMC0_LA05_P IO_L20P_T3L_N2_AD1P_66 +set_property -dict {PACKAGE_PIN BG23 IOSTANDARD LVCMOS15 } [get_ports spi0_miso ] ; ## FMC0_LA05_N IO_L20N_T3L_N3_AD1N_66 +set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS15 } [get_ports spi0_mosi ] ; ## FMC0_LA04_P IO_L21P_T3L_N4_AD8P_66 +set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS15 } [get_ports spi0_sclk ] ; ## FMC0_LA04_N IO_L21N_T3L_N5_AD8N_66 +set_property -dict {PACKAGE_PIN BG21 IOSTANDARD LVCMOS15 } [get_ports spi1_csb ] ; ## FMC0_LA12_P IO_L9P_T1L_N4_AD12P_66 +set_property -dict {PACKAGE_PIN BF23 IOSTANDARD LVCMOS15 } [get_ports spi1_sclk ] ; ## FMC0_LA11_P IO_L10P_T1U_N6_QBC_AD4P_66 +set_property -dict {PACKAGE_PIN BF22 IOSTANDARD LVCMOS15 } [get_ports spi1_sdio ] ; ## FMC0_LA12_N IO_L9N_T1L_N5_AD12N_66 +set_property -dict {PACKAGE_PIN AW23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref2_n ] ; ## FMC0_CLK0_M2C_N IO_L12N_T1U_N11_GC_66 +set_property -dict {PACKAGE_PIN AV23 IOSTANDARD LVDS15 DIFF_TERM_ADV TERM_100 } [get_ports sysref2_p ] ; ## FMC0_CLK0_M2C_P IO_L12P_T1U_N10_GC_66 +set_property -dict {PACKAGE_PIN BE25 IOSTANDARD LVCMOS15 } [get_ports txen[0] ] ; ## FMC0_LA09_P IO_L24P_T3U_N10_66 +set_property -dict {PACKAGE_PIN BE24 IOSTANDARD LVCMOS15 } [get_ports txen[1] ] ; ## FMC0_LA09_N IO_L24N_T3U_N11_66 + diff --git a/projects/ad9081_fmca_ebz/vck190/system_project.tcl b/projects/ad9081_fmca_ebz/vck190/system_project.tcl new file mode 100644 index 000000000..103ab8c78 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vck190/system_project.tcl @@ -0,0 +1,61 @@ + +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl +source $ad_hdl_dir/projects/scripts/adi_board.tcl + +# get_env_param retrieves parameter value from the environment if exists, +# other case use the default value +# +# Use over-writable parameters from the environment. +# +# e.g. +# make RX_JESD_L=4 RX_JESD_M=8 RX_JESD_S=1 TX_JESD_L=4 TX_JESD_M=8 TX_JESD_S=1 +# make RX_JESD_L=8 RX_JESD_M=4 RX_JESD_S=1 TX_JESD_L=8 TX_JESD_M=4 TX_JESD_S=1 + +# +# Parameter description: +# JESD_MODE : Used link layer encoder mode +# 64B66B - 64b66b link layer defined in JESD 204C, uses Xilinx IP as Physical layer +# 8B10B - 8b10b link layer defined in JESD 204B, uses ADI IP as Physical layer +# +# RX_RATE : Line rate of the Rx link ( MxFE to FPGA ) +# TX_RATE : Line rate of the Tx link ( FPGA to MxFE ) +# [RX/TX]_JESD_M : Number of converters per link +# [RX/TX]_JESD_L : Number of lanes per link +# [RX/TX]_JESD_NP : Number of bits per sample, only 16 is supported +# [RX/TX]_NUM_LINKS : Number of links, matches numer of MxFE devices +# +# + +# make JESD_MODE=64B66B RX_RATE=24.75 TX_RATE=24.75 RX_JESD_M=4 RX_JESD_L=4 RX_JESD_S=2 RX_JESD_NP=12 TX_JESD_M=4 TX_JESD_L=4 TX_JESD_S=2 TX_JESD_NP=12 + +adi_project ad9081_fmca_ebz_vck190 0 [list \ + JESD_MODE [get_env_param JESD_MODE 64B66B ]\ + RX_LANE_RATE [get_env_param RX_RATE 24.75 ] \ + TX_LANE_RATE [get_env_param TX_RATE 24.75 ] \ + RX_JESD_M [get_env_param RX_JESD_M 4 ] \ + RX_JESD_L [get_env_param RX_JESD_L 4 ] \ + RX_JESD_S [get_env_param RX_JESD_S 2 ] \ + RX_JESD_NP [get_env_param RX_JESD_NP 12] \ + RX_NUM_LINKS [get_env_param RX_NUM_LINKS 1 ] \ + TX_JESD_M [get_env_param TX_JESD_M 4 ] \ + TX_JESD_L [get_env_param TX_JESD_L 4 ] \ + TX_JESD_S [get_env_param TX_JESD_S 2 ] \ + TX_JESD_NP [get_env_param TX_JESD_NP 12] \ + TX_NUM_LINKS [get_env_param TX_NUM_LINKS 1 ] \ + RX_KS_PER_CHANNEL [get_env_param RX_KS_PER_CHANNEL 64 ] \ + TX_KS_PER_CHANNEL [get_env_param TX_KS_PER_CHANNEL 64 ] \ +] + +adi_project_files ad9081_fmca_ebz_vck190 [list \ + "system_top.v" \ + "system_constr.xdc"\ + "timing_constr.xdc"\ + "../../../library/common/ad_3w_spi.v"\ + "$ad_hdl_dir/library/common/ad_iobuf.v" \ + "$ad_hdl_dir/projects/common/vck190/vck190_system_constr.xdc" ] + +set_property strategy Performance_Explore [get_runs impl_1] + +adi_project_run ad9081_fmca_ebz_vck190 + diff --git a/projects/ad9081_fmca_ebz/vck190/system_top.v b/projects/ad9081_fmca_ebz/vck190/system_top.v new file mode 100644 index 000000000..d98d23ad9 --- /dev/null +++ b/projects/ad9081_fmca_ebz/vck190/system_top.v @@ -0,0 +1,283 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved. +// +// In this HDL repository, there are many different and unique modules, consisting +// of various HDL (Verilog or VHDL) components. The individual modules are +// developed independently, and may be accompanied by separate and unique license +// terms. +// +// The user should read each of these license terms, and understand the +// freedoms and responsibilities that he or she has by using this source/core. +// +// This core is distributed in the hope that it will be useful, but WITHOUT ANY +// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR +// A PARTICULAR PURPOSE. +// +// Redistribution and use of source or resulting binaries, with or without modification +// of this file, are permitted under one of the following two license terms: +// +// 1. The GNU General Public License version 2 as published by the +// Free Software Foundation, which can be found in the top level directory +// of this repository (LICENSE_GPL2), and also online at: +// +// +// OR +// +// 2. An ADI specific BSD license, which can be found in the top level directory +// of this repository (LICENSE_ADIBSD), and also on-line at: +// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD +// This will allow to generate bit files and not release the source code, +// as long as it attaches to an ADI device. +// +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top #( + parameter TX_JESD_L = 4, + parameter TX_NUM_LINKS = 1, + parameter RX_JESD_L = 4, + parameter RX_NUM_LINKS = 1 + ) ( + input sys_clk_n, + input sys_clk_p, + output ddr4_act_n, + output [16:0] ddr4_adr, + output [1:0] ddr4_ba, + output [1:0] ddr4_bg, + output ddr4_ck_c, + output ddr4_ck_t, + output ddr4_cke, + output ddr4_cs_n, + inout [7:0] ddr4_dm_n, + inout [63:0] ddr4_dq, + inout [7:0] ddr4_dqs_c, + inout [7:0] ddr4_dqs_t, + output ddr4_odt, + output ddr4_reset_n, + // GPIOs + output [3:0] gpio_led, + input [3:0] gpio_dip_sw, + input [1:0] gpio_pb, + + // FMC HPC IOs + input [1:0] agc0, + input [1:0] agc1, + input [1:0] agc2, + input [1:0] agc3, + input clkin6_n, + input clkin6_p, + input clkin10_n, + input clkin10_p, + input fpga_refclk_in_n, + input fpga_refclk_in_p, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_n, + input [RX_JESD_L*RX_NUM_LINKS-1:0] rx_data_p, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_n, + output [TX_JESD_L*TX_NUM_LINKS-1:0] tx_data_p, + input [TX_NUM_LINKS-1:0] fpga_syncin_n, + input [TX_NUM_LINKS-1:0] fpga_syncin_p, + output [RX_NUM_LINKS-1:0] fpga_syncout_n, + output [RX_NUM_LINKS-1:0] fpga_syncout_p, + inout [10:0] gpio, + inout hmc_gpio1, + output hmc_sync, + input [1:0] irqb, + output rstb, + output [1:0] rxen, + output spi0_csb, + input spi0_miso, + output spi0_mosi, + output spi0_sclk, + output spi1_csb, + output spi1_sclk, + inout spi1_sdio, + input sysref2_n, + input sysref2_p, + output [1:0] txen + +); + + // internal signals + + wire [95:0] gpio_i; + wire [95:0] gpio_o; + wire [95:0] gpio_t; + + wire [ 2:0] spi0_csn; + + wire [ 2:0] spi1_csn; + wire spi1_mosi; + wire spi1_miso; + + wire sysref; + wire [TX_NUM_LINKS-1:0] tx_syncin; + wire [RX_NUM_LINKS-1:0] rx_syncout; + + wire [7:0] rx_data_p_loc; + wire [7:0] rx_data_n_loc; + wire [7:0] tx_data_p_loc; + wire [7:0] tx_data_n_loc; + + wire clkin6; + wire clkin10; + wire tx_device_clk; + wire rx_device_clk; + + // instantiations + + IBUFDS i_ibufds_sysref ( + .I (sysref2_p), + .IB (sysref2_n), + .O (sysref)); + + IBUFDS i_ibufds_tx_device_clk ( + .I (clkin6_p), + .IB (clkin6_n), + .O (clkin6)); + + IBUFDS i_ibufds_rx_device_clk ( + .I (clkin10_p), + .IB (clkin10_n), + .O (clkin10)); + + genvar i; + generate + for(i=0;i