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fmcjesdadc1: Intergrate ad_sysref_gen into project

main
Istvan Csomortani 2016-12-19 13:37:29 +00:00
parent 0c42e04bc3
commit 8d799d0316
27 changed files with 4135 additions and 41 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
projects/fmcjesdadc1/a5gt/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/altera/sys_gen.tcl
M_DEPS += ../../common/a5gt/a5gt_system_qsys.tcl
M_DEPS += ../../common/a5gt/a5gt_system_assign.tcl
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl

14
projects/fmcjesdadc1/a5gt/fmcjesdadc1_a5gt.sld Normal file
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@ -0,0 +1,14 @@
<sld_project_info>
<sld_infos>
<sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
<assignment_values>
<assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482148783"/>
</assignment_values>
</sld_info>
<sld_info hpath="sld_hub:auto_hub|alt_sld_fab:\instrumentation_fabric_with_node_gen:instrumentation_fabric" library="alt_sld_fab" name="instrumentation_fabric">
<assignment_values>
<assignment_value text="QSYS_NAME alt_sld_fab HAS_SOPCINFO 1"/>
</assignment_values>
</sld_info>
</sld_infos>
</sld_project_info>

8
projects/fmcjesdadc1/a5gt/serv_req_info.txt Normal file
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@ -0,0 +1,8 @@
<internal_error>
<executable>quartus_sta</executable>
<sub_system>MEM</sub_system>
<error>*** Fatal Error: Out of memory in module quartus_sta (4171 megabytes used)</error>
<date>Mon Dec 19 12:41:45 2016</date>
<version>Version 16.0.2 Build 222 07/20/2016 SJ Standard Edition</version>
</internal_error>

2404
projects/fmcjesdadc1/a5gt/system_bd.qsys Normal file
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File diff suppressed because one or more lines are too long

34
projects/fmcjesdadc1/a5gt/system_bd_sys_ddr3_cntrl_p0_summary.csv Normal file
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@ -0,0 +1,34 @@
Core: system_bd_sys_ddr3_cntrl_p0 - Instance: i_system_bd|sys_ddr3_cntrl
Path, Setup Margin, Hold Margin
"Address Command (Slow 1150mV 100C Model)",0.436,0.635
"Bus Turnaround Time (Slow 1150mV 100C Model)",5.495,--
"Core (Slow 1150mV 100C Model)",0.379,0.223
"Core Recovery/Removal (Slow 1150mV 100C Model)",2.083,0.531
"DQS vs CK (Slow 1150mV 100C Model)",0.571,0.601
"Postamble (Slow 1150mV 100C Model)",0.52,0.52
"Read Capture (Slow 1150mV 100C Model)",0.256,0.245
"Write (Slow 1150mV 100C Model)",0.358,0.358
"Address Command (Slow 1150mV -40C Model)",0.522,0.579
"Bus Turnaround Time (Slow 1150mV -40C Model)",5.599,--
"Core (Slow 1150mV -40C Model)",0.713,0.163
"Core Recovery/Removal (Slow 1150mV -40C Model)",2.462,0.454
"DQS vs CK (Slow 1150mV -40C Model)",0.594,0.645
"Postamble (Slow 1150mV -40C Model)",0.506,0.506
"Read Capture (Slow 1150mV -40C Model)",0.29,0.279
"Write (Slow 1150mV -40C Model)",0.382,0.382
"Address Command (Fast 1150mV 100C Model)",0.807,0.54
"Bus Turnaround Time (Fast 1150mV 100C Model)",5.73,--
"Core (Fast 1150mV 100C Model)",1.331,0.154
"Core Recovery/Removal (Fast 1150mV 100C Model)",2.959,0.328
"DQS vs CK (Fast 1150mV 100C Model)",0.641,0.71
"Postamble (Fast 1150mV 100C Model)",0.685,0.685
"Read Capture (Fast 1150mV 100C Model)",0.339,0.331
"Write (Fast 1150mV 100C Model)",0.388,0.388
"Address Command (Fast 1150mV -40C Model)",0.874,0.483
"Bus Turnaround Time (Fast 1150mV -40C Model)",5.742,--
"Core (Fast 1150mV -40C Model)",1.374,0.112
"Core Recovery/Removal (Fast 1150mV -40C Model)",3.313,0.275
"DQS vs CK (Fast 1150mV -40C Model)",0.643,0.723
"Postamble (Fast 1150mV -40C Model)",0.67,0.67
"Read Capture (Fast 1150mV -40C Model)",0.339,0.331
"Write (Fast 1150mV -40C Model)",0.385,0.385
Can't render this file because it has a wrong number of fields in line 2.

1
projects/fmcjesdadc1/a5gt/system_project.tcl
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@ -7,6 +7,7 @@ project_new fmcjesdadc1_a5gt -overwrite
source "../../common/a5gt/a5gt_system_assign.tcl"
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys

4
projects/fmcjesdadc1/a5gt/system_qsys_script.tcl Normal file
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@ -0,0 +1,4 @@
set mmu_enabled 1
set ad_hdl_dir /home/icsomort/Git/hdl
set ad_phdl_dir /home/icsomort/Git/hdl
source system_qsys.tcl

28
projects/fmcjesdadc1/a5gt/system_top.v
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@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -99,9 +99,6 @@ module system_top (
reg [ 3:0] phy_rst_cnt = 0;
reg phy_rst_reg = 0;
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_int = 'd0;
// internal signals
@ -144,15 +141,12 @@ module system_top (
// sysref
assign rx_sysref = rx_sysref_int;
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref));
always @(posedge rx_clk) begin
rx_sysref_m1 <= gpio_o[32];
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
end
// instantiations
// instantiations
assign spi_csn = spi_csn_s[0];
@ -196,7 +190,7 @@ module system_top (
.rx_ip_sof_1_export (rx_ip_sof),
.rx_ref_clk_clk (ref_clk),
.rx_sync_export (rx_sync),
.rx_sysref_export (rx_sysref_int),
.rx_sysref_export (rx_sysref),
.sys_125m_clk_clk (sys_125m_clk),
.sys_25m_clk_clk (sys_25m_clk),
.sys_2m5_clk_clk (sys_2m5_clk),

1
projects/fmcjesdadc1/a5soc/Makefile
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@ -22,6 +22,7 @@ M_DEPS += ../../scripts/adi_env.tcl
M_DEPS += ../../common/altera/sys_gen.tcl
M_DEPS += ../../common/a5soc/a5soc_system_qsys.tcl
M_DEPS += ../../common/a5soc/a5soc_system_assign.tcl
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/altera/avl_adxcvr/avl_adxcvr_hw.tcl
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr.v
M_DEPS += ../../../library/altera/axi_adxcvr/axi_adxcvr_hw.tcl

9
projects/fmcjesdadc1/a5soc/fmcjesdadc1_a5soc.sld Normal file
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@ -0,0 +1,9 @@
<sld_project_info>
<sld_infos>
<sld_info hpath="system_bd:i_system_bd" name="i_system_bd">
<assignment_values>
<assignment_value text="QSYS_NAME system_bd HAS_SOPCINFO 1 GENERATION_ID 1482152395"/>
</assignment_values>
</sld_info>
</sld_infos>
</sld_project_info>

1585
projects/fmcjesdadc1/a5soc/system_bd.qsys Normal file
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File diff suppressed because one or more lines are too long

1
projects/fmcjesdadc1/a5soc/system_project.tcl
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@ -7,6 +7,7 @@ project_new fmcjesdadc1_a5soc -overwrite
source "../../common/a5soc/a5soc_system_assign.tcl"
set_global_assignment -name VERILOG_FILE ../common/fmcjesdadc1_spi.v
set_global_assignment -name VERILOG_FILE ../../../library/common/ad_sysref_gen.v
set_global_assignment -name VERILOG_FILE system_top.v
set_global_assignment -name QSYS_FILE system_bd.qsys

4
projects/fmcjesdadc1/a5soc/system_qsys_script.tcl Normal file
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@ -0,0 +1,4 @@
set mmu_enabled 1
set ad_hdl_dir /home/icsomort/Git/hdl
set ad_phdl_dir /home/icsomort/Git/hdl
source system_qsys.tcl

29
projects/fmcjesdadc1/a5soc/system_top.v
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@ -1,9 +1,9 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
//
// All rights reserved.
//
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
@ -21,16 +21,16 @@
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
@ -121,12 +121,6 @@ module system_top (
output spi_clk,
inout spi_sdio);
// internal registers
reg rx_sysref_m1 = 'd0;
reg rx_sysref_m2 = 'd0;
reg rx_sysref_int = 'd0;
// internal signals
wire sys_cpu_clk;
@ -156,13 +150,10 @@ module system_top (
// sysref
assign rx_sysref = rx_sysref_int;
always @(posedge rx_clk) begin
rx_sysref_m1 <= gpio_o[32];
rx_sysref_m2 <= rx_sysref_m1;
rx_sysref_int <= rx_sysref_m1 & ~rx_sysref_m2;
end
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref));
// instantiations
@ -193,7 +184,7 @@ module system_top (
.rx_ip_sof_1_export (rx_ip_sof),
.rx_ref_clk_clk (ref_clk),
.rx_sync_export (rx_sync),
.rx_sysref_export (rx_sysref_int),
.rx_sysref_export (rx_sysref),
.sys_clk_clk (sys_cpu_clk),
.sys_dma_clk_clk (sys_dma_clk),
.sys_dma_rst_reset_n (sys_rstn),

3
projects/fmcjesdadc1/common/fmcjesdadc1_bd.tcl
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@ -74,10 +74,13 @@ ad_xcvrpll axi_ad9250_xcvr/up_pll_rst util_fmcjesdadc1_xcvr/up_cpll_rst_*
ad_connect sys_cpu_resetn util_fmcjesdadc1_xcvr/up_rstn
ad_connect sys_cpu_clk util_fmcjesdadc1_xcvr/up_clk
create_bd_port -dir O rx_core_clk
# connections (adc)
ad_xcvrcon util_fmcjesdadc1_xcvr axi_ad9250_xcvr axi_ad9250_jesd
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_0_core/rx_clk
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 rx_core_clk
ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_0_core/rx_sof
ad_connect util_fmcjesdadc1_xcvr/rx_out_clk_0 axi_ad9250_1_core/rx_clk
ad_connect axi_ad9250_jesd/rx_start_of_frame axi_ad9250_1_core/rx_sof

1
projects/fmcjesdadc1/kc705/Makefile
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@ -18,6 +18,7 @@ M_DEPS += ../../common/kc705/kc705_system_mig.prj
M_DEPS += ../../common/kc705/kc705_system_constr.xdc
M_DEPS += ../../common/kc705/kc705_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr

3
projects/fmcjesdadc1/kc705/system_constr.xdc
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@ -25,3 +25,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]

1
projects/fmcjesdadc1/kc705/system_project.tcl
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@ -9,6 +9,7 @@ adi_project_files fmcjesdadc1_kc705 [list \
"system_top.v" \
"system_constr.xdc" \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"$ad_hdl_dir/projects/common/kc705/kc705_system_constr.xdc" ]
adi_project_run fmcjesdadc1_kc705

8
projects/fmcjesdadc1/kc705/system_top.v
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@ -180,6 +180,8 @@ module system_top (
wire spi_mosi;
wire spi_miso;
wire rx_ref_clk;
wire rx_clk;
wire rx_sysref;
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
@ -209,6 +211,11 @@ module system_top (
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref));
// instantiations
system_wrapper i_system_wrapper (
@ -277,6 +284,7 @@ module system_top (
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.rx_core_clk (rx_clk),
.spi_clk_i (spi_clk),
.spi_clk_o (spi_clk),
.spi_csn_i (spi_csn),

1
projects/fmcjesdadc1/vc707/Makefile
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@ -18,6 +18,7 @@ M_DEPS += ../../common/vc707/vc707_system_mig.prj
M_DEPS += ../../common/vc707/vc707_system_constr.xdc
M_DEPS += ../../common/vc707/vc707_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library/common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_dmac/axi_dmac.xpr

4
projects/fmcjesdadc1/vc707/system_constr.xdc
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@ -24,4 +24,8 @@ create_clock -name rx_ref_clk -period 4.00 [get_ports rx_ref_clk_p]
create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_i/util_fmcjesdadc1_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_false_path -to [get_cells i_system_wrapper/system_i/axi_ad9250_jesd/inst/rx_sysref_r_reg/D]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]

1
projects/fmcjesdadc1/vc707/system_project.tcl
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@ -6,6 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcjesdadc1_vc707
adi_project_files fmcjesdadc1_vc707 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"../common/fmcjesdadc1_spi.v" \
"system_top.v" \
"system_constr.xdc" \

8
projects/fmcjesdadc1/vc707/system_top.v
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@ -174,6 +174,8 @@ module system_top (
wire spi_miso;
wire rx_ref_clk;
wire [31:0] mb_intrs;
wire rx_clk;
wire rx_sysref;
assign ddr3_1_p = 2'b11;
assign ddr3_1_n = 3'b000;
@ -203,6 +205,11 @@ module system_top (
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref));
// instantiations
system_wrapper i_system_wrapper (
@ -267,6 +274,7 @@ module system_top (
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.rx_core_clk (rx_clk),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (8'hff),

1
projects/fmcjesdadc1/zc706/Makefile
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@ -17,6 +17,7 @@ M_DEPS += ../../scripts/adi_board.tcl
M_DEPS += ../../common/zc706/zc706_system_constr.xdc
M_DEPS += ../../common/zc706/zc706_system_bd.tcl
M_DEPS += ../../../library/xilinx/common/ad_iobuf.v
M_DEPS += ../../../library//common/ad_sysref_gen.v
M_DEPS += ../../../library/axi_ad9250/axi_ad9250.xpr
M_DEPS += ../../../library/xilinx/axi_adxcvr/axi_adxcvr.xpr
M_DEPS += ../../../library/axi_clkgen/axi_clkgen.xpr

13
projects/fmcjesdadc1/zc706/system_constr.xdc
View File

@ -11,12 +11,12 @@ set_property -dict {PACKAGE_PIN AG8 } [get_ports rx_data_p[2]]
set_property -dict {PACKAGE_PIN AG7 } [get_ports rx_data_n[2]] ; ## A07 FMC_HPC_DP2_M2C_N
set_property -dict {PACKAGE_PIN AE8 } [get_ports rx_data_p[3]] ; ## A10 FMC_HPC_DP3_M2C_P
set_property -dict {PACKAGE_PIN AE7 } [get_ports rx_data_n[3]] ; ## A11 FMC_HPC_DP3_M2C_N
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N
set_property -dict {PACKAGE_PIN N26 IOSTANDARD LVCMOS25} [get_ports rx_sync] ; ## G36 FMC_HPC_LA33_P
set_property -dict {PACKAGE_PIN N27 IOSTANDARD LVCMOS25} [get_ports rx_sysref] ; ## G37 FMC_HPC_LA33_N
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P
set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS25} [get_ports spi_csn] ; ## G34 FMC_HPC_LA31_N
set_property -dict {PACKAGE_PIN N29 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## G33 FMC_HPC_LA31_P
set_property -dict {PACKAGE_PIN P21 IOSTANDARD LVCMOS25} [get_ports spi_sdio] ; ## H37 FMC_HPC_LA32_P
# clocks
@ -25,3 +25,6 @@ create_clock -name rx_div_clk -period 6.40 [get_pins i_system_wrapper/system_
set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9250_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
set_property shreg_extract no [get_cells -hier -filter {name =~ *sysref_en_m*}]
set_false_path -to [get_cells -hier -filter {name =~ *sysref_en_m* && IS_SEQUENTIAL}]

1
projects/fmcjesdadc1/zc706/system_project.tcl
View File

@ -6,6 +6,7 @@ source $ad_hdl_dir/projects/scripts/adi_board.tcl
adi_project_create fmcjesdadc1_zc706
adi_project_files fmcjesdadc1_zc706 [list \
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
"$ad_hdl_dir/library/common/ad_sysref_gen.v" \
"../common/fmcjesdadc1_spi.v" \
"system_top.v" \
"system_constr.xdc" \

8
projects/fmcjesdadc1/zc706/system_top.v
View File

@ -149,6 +149,8 @@ module system_top (
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire rx_clk;
wire rx_sysref;
assign spi_csn = spi0_csn[0];
assign spi_clk = spi0_clk;
@ -180,6 +182,11 @@ module system_top (
.spi_miso (spi_miso),
.spi_sdio (spi_sdio));
ad_sysref_gen i_sysref (
.core_clk (rx_clk),
.sysref_en (gpio_o[32]),
.sysref_out (rx_sysref));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -235,6 +242,7 @@ module system_top (
.rx_ref_clk_0 (rx_ref_clk),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (rx_sysref),
.rx_core_clk (rx_clk),
.spdif (spdif),
.spi0_clk_i (spi0_clk),
.spi0_clk_o (spi0_clk),