From 8dc2161870dd9f8657ea94a24cb825bf624a3e84 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Sun, 13 Aug 2017 10:12:12 +0200 Subject: [PATCH] alt_mem_asym: Set read latency to 1 clock cycle In its default configuration the ram_2port module as a read latency of 2 clock cycles. Both the read address as well as the output data are registered. This is not the behavior that is expected from the alt_mem_asym module and causes incorrect behavior and data corruption in the util_adc_fifo. Disable the data output register to get a read latency of 1 clock cycle. Signed-off-by: Lars-Peter Clausen --- library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl | 1 + 1 file changed, 1 insertion(+) diff --git a/library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl b/library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl index 22baf3153..77fe3cb70 100644 --- a/library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl +++ b/library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl @@ -37,6 +37,7 @@ proc p_alt_mem_asym {} { set_instance_parameter_value alt_mem {GUI_QA_WIDTH} $m_data_width_a set_instance_parameter_value alt_mem {GUI_DATAA_WIDTH} $m_data_width_a set_instance_parameter_value alt_mem {GUI_QB_WIDTH} $m_data_width_b + set_instance_parameter_value alt_mem {GUI_READ_OUTPUT_QB} {false} set_instance_parameter_value alt_mem {GUI_RAM_BLOCK_TYPE} {M20K} set_instance_parameter_value alt_mem {GUI_CLOCK_TYPE} 1