zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

alt_mem_asym: Set read latency to 1 clock cycle 

In its default configuration the ram_2port module as a read latency of 2
clock cycles. Both the read address as well as the output data are
registered.

This is not the behavior that is expected from the alt_mem_asym module and
causes incorrect behavior and data corruption in the util_adc_fifo.

Disable the data output register to get a read latency of 1 clock cycle.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2017-08-13 10:12:12 +02:00
parent bb660d8cf8
commit 8dc2161870
1 changed files with 1 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
library/altera/common/alt_mem_asym/alt_mem_asym_hw.tcl
View File

@ -37,6 +37,7 @@ proc p_alt_mem_asym {} {
set_instance_parameter_value alt_mem {GUI_QA_WIDTH} $m_data_width_a
set_instance_parameter_value alt_mem {GUI_DATAA_WIDTH} $m_data_width_a
set_instance_parameter_value alt_mem {GUI_QB_WIDTH} $m_data_width_b
set_instance_parameter_value alt_mem {GUI_READ_OUTPUT_QB} {false}
set_instance_parameter_value alt_mem {GUI_RAM_BLOCK_TYPE} {M20K}
set_instance_parameter_value alt_mem {GUI_CLOCK_TYPE} 1