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adi_board.tcl: All procedures works on Zynq/Microblaze 

General patch for the integration procedures. Tested on kc705 and
	zed.
main
Istvan Csomortani 2014-04-01 16:19:24 +03:00
parent 9676146725
commit 8deb36ce08
1 changed files with 95 additions and 70 deletions
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163
projects/scripts/adi_board.tcl
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@ -11,14 +11,14 @@ proc set_num {number} {
} }
} }
# search the first free HP port in case of a Zynq device # search the first free HP port in case of a Zynq device
proc free_hp_port {} { proc free_hp_port { sys_ps7 } {
set hp_port_num 0 set hp_port_num 0
set hp_port 1 set hp_port 1
while(hp_port) { while { $hp_port == 1 } {
set hp_port_num [expr hp_port_num + 1] set hp_port_num [expr $hp_port_num + 1]
set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" [get_bd_cells sys_ps7]] set hp_port [get_property "CONFIG.PCW_USE_S_AXI_HP${hp_port_num}" $sys_ps7]
} }
return $hp_port_num return $hp_port_num
@ -42,9 +42,6 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
# check processor type, connect system clock and reset to the peripheral # check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } { if { $::sys_zynq == 1 } {
# sys_proc is a zynq
set sys_proc [get_bd_cells sys_ps7]
# connect clk and reset for the interconnect # connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
@ -57,13 +54,10 @@ proc adi_interconnect_lite { peripheral_name peripheral_address } {
connect_bd_net -net sys_100m_resetn \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${peripheral_name}/s_axi_aresetn"] [get_bd_pins "${peripheral_name}/s_axi_aresetn"]
} else { } else {
# sys_proc is a micorblaze
set sys_proc [get_bd_cells sys_mb]
# connect clk and reset for the interconnect # connect clk and reset for the interconnect
connect_bd_net -net sys_100m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn_intc \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source [get_bd_pins "$interconnect_bd/M[set_num [expr $number_of_master -1]]_ARESETN"] $::sys_100m_resetn_source
# connect clk and reset for the peripheral port # connect clk and reset for the peripheral port
@ -109,12 +103,10 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
# check processor type, connect system clock and reset to the peripheral # check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } { if { $::sys_zynq == 1 } {
# sys_proc is a zynq
set sys_proc [get_bd_cells sys_ps7]
# add SPI interface to ps7 # add SPI interface to ps7
set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] $sys_proc set_property -dict [list CONFIG.PCW_SPI0_PERIPHERAL_ENABLE {1}] [get_bd_cells sys_ps7]
set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] $sys_proc set_property -dict [list CONFIG.PCW_SPI0_SPI0_IO {EMIO}] [get_bd_cells sys_ps7]
set i 0 set i 0
while { $i < $spi_ss_width } { while { $i < $spi_ss_width } {
@ -155,58 +147,76 @@ proc adi_spi_core { spi_name spi_ss_width spi_base_addr } {
[get_bd_ports spi_csn_i] \ [get_bd_ports spi_csn_i] \
[get_bd_pins sys_ps7/SPI0_SS_I] [get_bd_pins sys_ps7/SPI0_SS_I]
connect_bd_net -net spi_sclk_i \ connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_clk_i] \ [get_bd_ports spi_sclk_i] \
[get_bd_pins sys_ps7/SPI0_SCLK_I] [get_bd_pins sys_ps7/SPI0_SCLK_I]
connect_bd_net -net spi_sclk_o \ connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_clk_o] \ [get_bd_ports spi_sclk_o] \
[get_bd_pins sys_ps7/SPI0_SCLK_O] [get_bd_pins sys_ps7/SPI0_SCLK_O]
connect_bd_net -net spi_mosi_i \ connect_bd_net -net spi_mosi_i \
[get_bd_ports spi_sdo_i] \ [get_bd_ports spi_mosi_i] \
[get_bd_pins sys_ps7/SPI0_MOSI_I] [get_bd_pins sys_ps7/SPI0_MOSI_I]
connect_bd_net -net spi_mosi_o \ connect_bd_net -net spi_mosi_o \
[get_bd_ports spi_sdo_o] \ [get_bd_ports spi_mosi_o] \
[get_bd_pins sys_ps7/SPI0_MOSI_O] [get_bd_pins sys_ps7/SPI0_MOSI_O]
connect_bd_net -net spi_miso_i \ connect_bd_net -net spi_miso_i \
[get_bd_ports spi_sdi_i] \ [get_bd_ports spi_miso_i] \
[get_bd_pins sys_ps7/SPI0_MISO_I] [get_bd_pins sys_ps7/SPI0_MISO_I]
} else { } else {
# SPI SS lines # SPI SS lines
set spi_csn_i [create_bd_port -dir I -from [expr $spi_ss_width - 1] -to 0 spi_csn_i]
set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o] set spi_csn_o [create_bd_port -dir O -from [expr $spi_ss_width - 1] -to 0 spi_csn_o]
# instanciate AXI_SPI core # instanciate AXI_SPI core
set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name] set spi_name [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 $spi_name]
set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name set_property -dict [list CONFIG.C_USE_STARTUP {0}] $spi_name
set_property -dict [list CONFIG.C_NUM_SS_BITS {$spi_ss_width}] $spi_name
set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name set_property -dict [list CONFIG.C_SCK_RATIO {16}] $spi_name
set_property -dict [list CONFIG.Multiples16 {2}] $spi_name set_property -dict [list CONFIG.Multiples16 {2}] $spi_name
switch $spi_ss_width {
1
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {1}] $spi_name
}
2
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {2}] $spi_name
}
3
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {3}] $spi_name
}
4
{
set_property -dict [list CONFIG.C_NUM_SS_BITS {4}] $spi_name
}
}
adi_interconnect_lite $spi_name $spi_base_addr
connect_bd_net -net sys_100m_clk \
[get_bd_pins "${spi_name}/ext_spi_clk"] \
$::sys_100m_clk_source
# spi external ports # spi external ports
connect_bd_net -net spi_csn_o \ connect_bd_net -net spi_csn_o \
[get_bd_ports spi_csn_o] \ [get_bd_ports spi_csn_o] \
[get_bd_pins "${spi_name}/ss_i"] [get_bd_pins "${spi_name}/ss_o"]
connect_bd_net -net spi_csn_i \ connect_bd_net -net spi_csn_i \
[get_bd_ports spi_csn_i] \ [get_bd_ports spi_csn_i] \
[get_bd_pins "${spi_name}/ss_o"] [get_bd_pins "${spi_name}/ss_i"]
connect_bd_net -net spi_sclk_o \ connect_bd_net -net spi_sclk_o \
[get_bd_ports spi_clk_o] \ [get_bd_ports spi_sclk_o] \
[get_bd_pins "${spi_name}/sck_o"] [get_bd_pins "${spi_name}/sck_o"]
connect_bd_net -net spi_sclk_i \ connect_bd_net -net spi_sclk_i \
[get_bd_ports spi_clk_i] \ [get_bd_ports spi_sclk_i] \
[get_bd_pins "${spi_name}/sck_i"] [get_bd_pins "${spi_name}/sck_i"]
connect_bd_net -net spi_mosi_o \ connect_bd_net -net spi_mosi_o \
[get_bd_pins spi_sdo_o] \ [get_bd_ports spi_mosi_o] \
[get_bd_pins "${spi_name}/io0_o"] [get_bd_pins "${spi_name}/io0_o"]
connect_bd_net -net spi_mosi_i \ connect_bd_net -net spi_mosi_i \
[get_bd_pins spi_sdo_i] \ [get_bd_ports spi_mosi_i] \
[get_bd_pins "${spi_name}/io0_i"] [get_bd_pins "${spi_name}/io0_i"]
connect_bd_net -net spi_miso_i \ connect_bd_net -net spi_miso_i \
[get_bd_ports spi_sdi_i] \ [get_bd_ports spi_miso_i] \
[get_bd_pins "${spi_name}/io1_i"] [get_bd_pins "${spi_name}/io1_i"]
create_bd_addr_seg -range 0x00010000 -offset $spi_base_addr
$::sys_addr_cntrl_space \
[get_bd_addr_segs "${spi_name}/axi_lite/Reg"] \
"SEG_data_${spi_name}"
} }
} }
@ -215,43 +225,59 @@ proc adi_dma_interconnect { dma_name port_name} {
# check processor type, connect system clock and reset to the peripheral # check processor type, connect system clock and reset to the peripheral
if { $::sys_zynq == 1 } { if { $::sys_zynq == 1 } {
set hp_port [free_hp_port]
set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] $sys_ps7 set hp_port [free_hp_port [get_bd_cells sys_ps7]]
set axi_dma_interconnect_($hp_port) [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_($hp_port)] set_property -dict [list "CONFIG.PCW_USE_S_AXI_HP${hp_port}" {1}] [get_bd_cells sys_ps7]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_($hp_port) switch $hp_port {
1
{
set axi_dma_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_1]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_1
}
2
{
set axi_dma_interconnect_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_2]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_2
}
3
{
set axi_dma_interconnect_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_dma_interconnect_3]
set_property -dict [list CONFIG.NUM_MI {1}] $axi_dma_interconnect_3
}
}
# connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals # connect the master port of the interconnect to the HP1, and connect aditional clock/reset signals
connect_bd_net -net sys_100m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins sys_ps7/S_AXI_HP1_ACLK] [get_bd_pins sys_ps7/S_AXI_HP1_ACLK]
connect_bd_net -net sys_100m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins axi_ddr_interconnect/M00_ACLK] $::sys_100m_clk_source [get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source [get_bd_pins "axi_dma_interconnect_${hp_port}/M00_ARESETN"] $::sys_100m_resetn_source
connect_bd_net -net sys_100m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source [get_bd_pins "axi_dma_interconnect_${hp_port}/ACLK"] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source [get_bd_pins "axi_dma_interconnect_${hp_port}/ARESETN"] $::sys_100m_resetn_source
connect_bd_intf_net -intf_net axi_ddr_interconnect_m00_axi \ connect_bd_intf_net -intf_net axi_dma_interconnect_m00_axi \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \ [get_bd_intf_pins "axi_dma_interconnect_${hp_port}/M00_AXI"] \
[get_bd_intf_pins sys_ps7/S_AXI_HP1] [get_bd_intf_pins sys_ps7/S_AXI_HP1]
# connect clk and reset for the interconnect # connect clk and reset for the interconnect
connect_bd_net -net sys_200m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "${axi_dma_interconnect_($hp_port)}/S00_ACLK"] \ [get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ACLK"] \
[get_bd_pins $clk] $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn_intc \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$axi_dma_interconnect_($hp_port)/S00_ARESETN"] \ [get_bd_pins "axi_dma_interconnect_${hp_port}/S00_ARESETN"] \
[get_bd_pins $reset_i] $::sys_100m_resetn_source
# connect clk and reset for the peripheral port # connect clk and reset for the peripheral port
puts "${dma_name}/${peripheral_port}_aclk" puts "${dma_name}/${port_name}_aclk"
connect_bd_net -net sys_200m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "${dma_name}/${peripheral_port}_aclk"] [get_bd_pins "${dma_name}/${port_name}_aclk"]
connect_bd_net -net sys_200m_resetn \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"] [get_bd_pins "${dma_name}/${port_name}_aresetn"]
# Connect the interconnect to the dma # Connect the interconnect to the dma
connect_bd_intf_net -intf_net ${dma_name}_interconnect_s00_axi \ connect_bd_intf_net -intf_net "axi_dma_interconnect_${hp_port}_s00_axi" \
[get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \ [get_bd_intf_pins "axi_dma_interconnect_${hp_port}/S00_AXI"] \
[get_bd_intf_pins "${dma_name}/${port_name}"] [get_bd_intf_pins "${dma_name}/${port_name}"]
@ -262,35 +288,34 @@ proc adi_dma_interconnect { dma_name port_name} {
"SEG_sys_ps7_hp${hp_port}_ddr_lowocm" "SEG_sys_ps7_hp${hp_port}_ddr_lowocm"
} else { } else {
set axi_ddr_interconnect [get_bd_cells axi_ddr_interconnect] set axi_mem_interconnect [get_bd_cells axi_mem_interconnect]
# increment the number of the master ports of the interconnect # increment the number of the master ports of the interconnect
set number_of_slave [get_property CONFIG.NUM_SI $axi_ddr_interconnect] set number_of_slave [get_property CONFIG.NUM_SI $axi_mem_interconnect]
set number_of_slave [expr $number_of_slave + 1] set number_of_slave [expr $number_of_slave + 1]
set_property CONFIG.NUM_SI $number_of_slave $axi_ddr_interconnect set_property CONFIG.NUM_SI $number_of_slave $axi_mem_interconnect
# connect clk and reset for the interconnect # connect clk and reset for the interconnect
connect_bd_net -net sys_200m_clk \ connect_bd_net -net sys_100m_clk \
[get_bd_pins "${axi_ddr_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \ [get_bd_pins "${axi_mem_interconnect}/S0[expr $number_of_slave-1]_ACLK"] \
$::sys_200m_clk_source $::sys_100m_clk_source
connect_bd_net -net sys_100m_resetn_intc \ connect_bd_net -net sys_100m_resetn \
[get_bd_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \ [get_bd_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_ARESETN"] \
$::sys_100m_resetn_source $::sys_100m_resetn_source
# connect clk and reset for the peripheral port # connect clk and reset for the peripheral port
puts "${dma_name}/${peripheral_port}_aclk" connect_bd_net -net sys_100m_clk \
connect_bd_net -net sys_200m_clk \ [get_bd_pins "${dma_name}/${port_name}_aclk"]
[get_bd_pins "${dma_name}/${peripheral_port}_aclk"] connect_bd_net -net sys_100m_resetn \
connect_bd_net -net sys_200m_resetn \ [get_bd_pins "${dma_name}/${port_name}_aresetn"]
[get_bd_pins "${dma_name}/${peripheral_port}_aresetn"]
# make the port connection # make the port connection
connect_bd_intf_net -intf_net "axi_ddr_interconnect_s${number_of_slave}" \ connect_bd_intf_net -intf_net "axi_mem_interconnect_s${number_of_slave}" \
[get_bd_intf_pins "$axi_ddr_interconnect/S0[expr $number_of_slave -1]_AXI"] \ [get_bd_intf_pins "$axi_mem_interconnect/S0[expr $number_of_slave -1]_AXI"] \
[get_bd_intf_pins "${dma_name}/${peripheral_port}"] [get_bd_intf_pins "${dma_name}/${port_name}"]
# define address space for the peripheral # define address space for the peripheral
create_bd_addr_seg -range $peripheral_address_range -offset $peripheral_address \ create_bd_addr_seg -range $::sys_mem_size -offset 0x00000000 \
[get_bd_addr_spaces "${dma_name}/${peripheral_port}"] \ [get_bd_addr_spaces "${dma_name}/${port_name}"] \
[get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \ [get_bd_addr_segs "axi_ddr_cntrl/memmap/memaddr"] \
"SEG_data_${dma_name}_2_ddr" "SEG_data_${dma_name}_2_ddr"
} }