From 8e0a45dea963b75caf9c18195ee7076b1191a8db Mon Sep 17 00:00:00 2001 From: Laszlo Nagy Date: Thu, 11 Nov 2021 17:52:50 +0200 Subject: [PATCH] jesd204_rx/jesd204_lane_latency_monitor.v: Fix for datapath width of 4 Current implementation is correct only for datapath width of 8. The buswidth of latency measurement inside a beat has a fixed width (3 bits) for each lane that must be taken in account when computing the total latency. Signed-off-by: Laszlo Nagy --- library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v index f27e3483e..d533db84e 100755 --- a/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v +++ b/library/jesd204/jesd204_rx/jesd204_lane_latency_monitor.v @@ -88,7 +88,7 @@ for (i = 0; i < NUM_LANES; i = i + 1) begin: gen_lane end end - assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[(i*DPW_LOG2)+DPW_LOG2-1:i*DPW_LOG2]}; + assign lane_latency[i*14+13:i*14] = {lane_latency_mem[i],lane_frame_align[(i*3)+DPW_LOG2-1:i*3]}; assign lane_latency_ready[i] = lane_captured[i]; end endgenerate