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all: Change tab to double space 

Occasional file parsing and restructuring become a pain, if tabs exists
in code. General rule of the repos is tab always a double space.
main
Istvan Csomortani 2016-10-01 18:13:42 +03:00
parent 0208335ef3
commit 8e25bc01b3
32 changed files with 2638 additions and 2638 deletions
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140
library/axi_dmac/2d_transfer.v
View File

@ -37,28 +37,28 @@
// ***************************************************************************
module dmac_2d_transfer (
input req_aclk,
input req_aresetn,
input req_aclk,
input req_aresetn,
input req_valid,
output reg req_ready,
input req_valid,
output reg req_ready,
input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [DMA_LENGTH_WIDTH-1:0] req_x_length,
input [DMA_LENGTH_WIDTH-1:0] req_y_length,
input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
input req_sync_transfer_start,
output reg req_eot,
input [31:BYTES_PER_BEAT_WIDTH_DEST] req_dest_address,
input [31:BYTES_PER_BEAT_WIDTH_SRC] req_src_address,
input [DMA_LENGTH_WIDTH-1:0] req_x_length,
input [DMA_LENGTH_WIDTH-1:0] req_y_length,
input [DMA_LENGTH_WIDTH-1:0] req_dest_stride,
input [DMA_LENGTH_WIDTH-1:0] req_src_stride,
input req_sync_transfer_start,
output reg req_eot,
output reg out_req_valid,
input out_req_ready,
output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
output reg out_req_valid,
input out_req_ready,
output [31:BYTES_PER_BEAT_WIDTH_DEST] out_req_dest_address,
output [31:BYTES_PER_BEAT_WIDTH_SRC] out_req_src_address,
output [DMA_LENGTH_WIDTH-1:0] out_req_length,
output reg out_req_sync_transfer_start,
input out_eot
);
parameter DMA_LENGTH_WIDTH = 24;
@ -82,61 +82,61 @@ assign out_req_length = x_length;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
req_id <= 2'b0;
eot_id <= 2'b0;
req_eot <= 1'b0;
end else begin
if (out_req_valid && out_req_ready) begin
req_id <= req_id + 1'b1;
last_req[req_id] <= y_length == 0;
end
req_eot <= 1'b0;
if (out_eot) begin
eot_id <= eot_id + 1'b1;
req_eot <= last_req[eot_id];
end
end
if (req_aresetn == 1'b0) begin
req_id <= 2'b0;
eot_id <= 2'b0;
req_eot <= 1'b0;
end else begin
if (out_req_valid && out_req_ready) begin
req_id <= req_id + 1'b1;
last_req[req_id] <= y_length == 0;
end
req_eot <= 1'b0;
if (out_eot) begin
eot_id <= eot_id + 1'b1;
req_eot <= last_req[eot_id];
end
end
end
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
dest_address <= 'h00;
src_address <= 'h00;
x_length <= 'h00;
y_length <= 'h00;
dest_stride <= 'h00;
src_stride <= 'h00;
req_ready <= 1'b1;
out_req_valid <= 1'b0;
out_req_sync_transfer_start <= 1'b0;
end else begin
if (req_ready) begin
if (req_valid) begin
dest_address <= req_dest_address;
src_address <= req_src_address;
x_length <= req_x_length;
y_length <= req_y_length;
dest_stride <= req_dest_stride;
src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start;
req_ready <= 1'b0;
out_req_valid <= 1'b1;
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin
out_req_valid <= 1'b0;
req_ready <= 1'b1;
end
end
end
end
if (req_aresetn == 1'b0) begin
dest_address <= 'h00;
src_address <= 'h00;
x_length <= 'h00;
y_length <= 'h00;
dest_stride <= 'h00;
src_stride <= 'h00;
req_ready <= 1'b1;
out_req_valid <= 1'b0;
out_req_sync_transfer_start <= 1'b0;
end else begin
if (req_ready) begin
if (req_valid) begin
dest_address <= req_dest_address;
src_address <= req_src_address;
x_length <= req_x_length;
y_length <= req_y_length;
dest_stride <= req_dest_stride;
src_stride <= req_src_stride;
out_req_sync_transfer_start <= req_sync_transfer_start;
req_ready <= 1'b0;
out_req_valid <= 1'b1;
end
end else begin
if (out_req_valid && out_req_ready) begin
dest_address <= dest_address + dest_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_DEST];
src_address <= src_address + src_stride[DMA_LENGTH_WIDTH-1:BYTES_PER_BEAT_WIDTH_SRC];
y_length <= y_length - 1'b1;
out_req_sync_transfer_start <= 1'b0;
if (y_length == 0) begin
out_req_valid <= 1'b0;
req_ready <= 1'b1;
end
end
end
end
end
endmodule

114
library/axi_dmac/address_generator.v
View File

@ -36,32 +36,32 @@
// ***************************************************************************
module dmac_address_generator (
input clk,
input resetn,
input clk,
input resetn,
input req_valid,
output reg req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_valid,
output reg req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
input eot,
input eot,
input enable,
input pause,
output reg enabled,
input enable,
input pause,
output reg enabled,
input addr_ready,
output reg addr_valid,
output [31:0] addr,
output [ 7:0] len,
output [ 2:0] size,
output [ 1:0] burst,
output [ 2:0] prot,
output [ 3:0] cache
input addr_ready,
output reg addr_valid,
output [31:0] addr,
output [ 7:0] len,
output [ 2:0] size,
output [ 1:0] burst,
output [ 2:0] prot,
output [ 3:0] cache
);
@ -110,52 +110,52 @@ always @(posedge clk) begin
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
last <= 1'b0;
end else if (addr_valid == 1'b0) begin
last <= eot;
end
if (resetn == 1'b0) begin
last <= 1'b0;
end else if (addr_valid == 1'b0) begin
last <= eot;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
address <= 'h00;
last_burst_len <= 'h00;
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (~enabled) begin
req_ready <= 1'b1;
end else if (req_ready) begin
if (req_valid && enable) begin
address <= req_address;
req_ready <= 1'b0;
last_burst_len <= req_last_burst_length;
end
end else begin
if (addr_valid && addr_ready) begin
address <= address + MAX_BEATS_PER_BURST;
addr_valid <= 1'b0;
if (last)
req_ready <= 1'b1;
end else if (id != request_id && enable) begin
addr_valid <= 1'b1;
end
end
end
if (resetn == 1'b0) begin
address <= 'h00;
last_burst_len <= 'h00;
req_ready <= 1'b1;
addr_valid <= 1'b0;
end else begin
if (~enabled) begin
req_ready <= 1'b1;
end else if (req_ready) begin
if (req_valid && enable) begin
address <= req_address;
req_ready <= 1'b0;
last_burst_len <= req_last_burst_length;
end
end else begin
if (addr_valid && addr_ready) begin
address <= address + MAX_BEATS_PER_BURST;
addr_valid <= 1'b0;
if (last)
req_ready <= 1'b1;
end else if (id != request_id && enable) begin
addr_valid <= 1'b1;
end
end
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <='h0;
if (resetn == 1'b0) begin
id <='h0;
addr_valid_d1 <= 1'b0;
end else begin
end else begin
addr_valid_d1 <= addr_valid;
if ((addr_valid && ~addr_valid_d1) ||
(sync_id && id != request_id))
id <= inc_id(id);
(sync_id && id != request_id))
id <= inc_id(id);
end
end
end
endmodule

724
library/axi_dmac/axi_dmac.v
View File

@ -37,141 +37,141 @@
// ***************************************************************************
module axi_dmac (
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
// Slave AXI interface
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [13:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [13:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_awvalid,
input [13:0] s_axi_awaddr,
output s_axi_awready,
input [2:0] s_axi_awprot,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [13:0] s_axi_araddr,
output s_axi_arready,
input [2:0] s_axi_arprot,
output s_axi_rvalid,
input s_axi_rready,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
// Interrupt
output reg irq,
// Interrupt
output reg irq,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
// Master AXI interface
input m_dest_axi_aclk,
input m_dest_axi_aresetn,
// Write address
output [31:0] m_dest_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [ 2:0] m_dest_axi_awsize,
output [ 1:0] m_dest_axi_awburst,
output [ 2:0] m_dest_axi_awprot,
output [ 3:0] m_dest_axi_awcache,
output m_dest_axi_awvalid,
input m_dest_axi_awready,
// Write address
output [31:0] m_dest_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_awlen,
output [ 2:0] m_dest_axi_awsize,
output [ 1:0] m_dest_axi_awburst,
output [ 2:0] m_dest_axi_awprot,
output [ 3:0] m_dest_axi_awcache,
output m_dest_axi_awvalid,
input m_dest_axi_awready,
// Write data
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
input m_dest_axi_wready,
output m_dest_axi_wvalid,
output m_dest_axi_wlast,
// Write data
output [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_wdata,
output [(DMA_DATA_WIDTH_DEST/8)-1:0] m_dest_axi_wstrb,
input m_dest_axi_wready,
output m_dest_axi_wvalid,
output m_dest_axi_wlast,
// Write response
input m_dest_axi_bvalid,
input [ 1:0] m_dest_axi_bresp,
output m_dest_axi_bready,
// Write response
input m_dest_axi_bvalid,
input [ 1:0] m_dest_axi_bresp,
output m_dest_axi_bready,
// Unused read interface
output m_dest_axi_arvalid,
output [31:0] m_dest_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [ 2:0] m_dest_axi_arsize,
output [ 1:0] m_dest_axi_arburst,
output [ 3:0] m_dest_axi_arcache,
output [ 2:0] m_dest_axi_arprot,
input m_dest_axi_arready,
input m_dest_axi_rvalid,
input [ 1:0] m_dest_axi_rresp,
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
// Unused read interface
output m_dest_axi_arvalid,
output [31:0] m_dest_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_DEST):0] m_dest_axi_arlen,
output [ 2:0] m_dest_axi_arsize,
output [ 1:0] m_dest_axi_arburst,
output [ 3:0] m_dest_axi_arcache,
output [ 2:0] m_dest_axi_arprot,
input m_dest_axi_arready,
input m_dest_axi_rvalid,
input [ 1:0] m_dest_axi_rresp,
input [DMA_DATA_WIDTH_DEST-1:0] m_dest_axi_rdata,
output m_dest_axi_rready,
// Master AXI interface
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Master AXI interface
input m_src_axi_aclk,
input m_src_axi_aresetn,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,
output [31:0] m_src_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [ 2:0] m_src_axi_arsize,
output [ 1:0] m_src_axi_arburst,
output [ 2:0] m_src_axi_arprot,
output [ 3:0] m_src_axi_arcache,
// Read address
input m_src_axi_arready,
output m_src_axi_arvalid,
output [31:0] m_src_axi_araddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_arlen,
output [ 2:0] m_src_axi_arsize,
output [ 1:0] m_src_axi_arburst,
output [ 2:0] m_src_axi_arprot,
output [ 3:0] m_src_axi_arcache,
// Read data and response
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
output m_src_axi_rready,
input m_src_axi_rvalid,
input [ 1:0] m_src_axi_rresp,
// Read data and response
input [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_rdata,
output m_src_axi_rready,
input m_src_axi_rvalid,
input [ 1:0] m_src_axi_rresp,
// Unused write interface
output m_src_axi_awvalid,
output [31:0] m_src_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [ 2:0] m_src_axi_awsize,
output [ 1:0] m_src_axi_awburst,
output [ 3:0] m_src_axi_awcache,
output [ 2:0] m_src_axi_awprot,
input m_src_axi_awready,
output m_src_axi_wvalid,
output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output m_src_axi_wlast,
input m_src_axi_wready,
input m_src_axi_bvalid,
input [ 1:0] m_src_axi_bresp,
output m_src_axi_bready,
// Unused write interface
output m_src_axi_awvalid,
output [31:0] m_src_axi_awaddr,
output [7-(4*DMA_AXI_PROTOCOL_SRC):0] m_src_axi_awlen,
output [ 2:0] m_src_axi_awsize,
output [ 1:0] m_src_axi_awburst,
output [ 3:0] m_src_axi_awcache,
output [ 2:0] m_src_axi_awprot,
input m_src_axi_awready,
output m_src_axi_wvalid,
output [DMA_DATA_WIDTH_SRC-1:0] m_src_axi_wdata,
output [(DMA_DATA_WIDTH_SRC/8)-1:0] m_src_axi_wstrb,
output m_src_axi_wlast,
input m_src_axi_wready,
input m_src_axi_bvalid,
input [ 1:0] m_src_axi_bresp,
output m_src_axi_bready,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Slave streaming AXI interface
input s_axis_aclk,
output s_axis_ready,
input s_axis_valid,
input [DMA_DATA_WIDTH_SRC-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
// Master streaming AXI interface
input m_axis_aclk,
input m_axis_ready,
output m_axis_valid,
output [DMA_DATA_WIDTH_DEST-1:0] m_axis_data,
output m_axis_last,
output m_axis_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_wr_clk,
input fifo_wr_en,
input [DMA_DATA_WIDTH_SRC-1:0] fifo_wr_din,
output fifo_wr_overflow,
input fifo_wr_sync,
output fifo_wr_xfer_req,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
// Input FIFO interface
input fifo_rd_clk,
input fifo_rd_en,
output fifo_rd_valid,
output [DMA_DATA_WIDTH_DEST-1:0] fifo_rd_dout,
output fifo_rd_underflow,
output fifo_rd_xfer_req
);
@ -210,21 +210,21 @@ localparam HAS_SRC_ADDR = DMA_TYPE_SRC == DMA_TYPE_AXI_MM;
// Argh... "[Synth 8-2722] system function call clog2 is not allowed here"
localparam BYTES_PER_BEAT_WIDTH_DEST = DMA_DATA_WIDTH_DEST > 1024 ? 8 :
DMA_DATA_WIDTH_DEST > 512 ? 7 :
DMA_DATA_WIDTH_DEST > 256 ? 6 :
DMA_DATA_WIDTH_DEST > 128 ? 5 :
DMA_DATA_WIDTH_DEST > 64 ? 4 :
DMA_DATA_WIDTH_DEST > 32 ? 3 :
DMA_DATA_WIDTH_DEST > 16 ? 2 :
DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
DMA_DATA_WIDTH_DEST > 512 ? 7 :
DMA_DATA_WIDTH_DEST > 256 ? 6 :
DMA_DATA_WIDTH_DEST > 128 ? 5 :
DMA_DATA_WIDTH_DEST > 64 ? 4 :
DMA_DATA_WIDTH_DEST > 32 ? 3 :
DMA_DATA_WIDTH_DEST > 16 ? 2 :
DMA_DATA_WIDTH_DEST > 8 ? 1 : 0;
localparam BYTES_PER_BEAT_WIDTH_SRC = DMA_DATA_WIDTH_SRC > 1024 ? 8 :
DMA_DATA_WIDTH_SRC > 512 ? 7 :
DMA_DATA_WIDTH_SRC > 256 ? 6 :
DMA_DATA_WIDTH_SRC > 128 ? 5 :
DMA_DATA_WIDTH_SRC > 64 ? 4 :
DMA_DATA_WIDTH_SRC > 32 ? 3 :
DMA_DATA_WIDTH_SRC > 16 ? 2 :
DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
DMA_DATA_WIDTH_SRC > 512 ? 7 :
DMA_DATA_WIDTH_SRC > 256 ? 6 :
DMA_DATA_WIDTH_SRC > 128 ? 5 :
DMA_DATA_WIDTH_SRC > 64 ? 4 :
DMA_DATA_WIDTH_SRC > 32 ? 3 :
DMA_DATA_WIDTH_SRC > 16 ? 2 :
DMA_DATA_WIDTH_SRC > 8 ? 1 : 0;
// Register interface signals
reg [31:0] up_rdata = 'd0;
@ -300,35 +300,35 @@ assign m_src_axi_wstrb = 'd0;
assign m_src_axi_wlast = 'd0;
up_axi #(
.ADDRESS_WIDTH (12)
.ADDRESS_WIDTH (12)
) i_up_axi (
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack)
.up_rstn(s_axi_aresetn),
.up_clk(s_axi_aclk),
.up_axi_awvalid(s_axi_awvalid),
.up_axi_awaddr(s_axi_awaddr),
.up_axi_awready(s_axi_awready),
.up_axi_wvalid(s_axi_wvalid),
.up_axi_wdata(s_axi_wdata),
.up_axi_wstrb(s_axi_wstrb),
.up_axi_wready(s_axi_wready),
.up_axi_bvalid(s_axi_bvalid),
.up_axi_bresp(s_axi_bresp),
.up_axi_bready(s_axi_bready),
.up_axi_arvalid(s_axi_arvalid),
.up_axi_araddr(s_axi_araddr),
.up_axi_arready(s_axi_arready),
.up_axi_rvalid(s_axi_rvalid),
.up_axi_rresp(s_axi_rresp),
.up_axi_rdata(s_axi_rdata),
.up_axi_rready(s_axi_rready),
.up_wreq(up_wreq),
.up_waddr(up_waddr),
.up_wdata(up_wdata),
.up_wack(up_wack),
.up_rreq(up_rreq),
.up_raddr(up_raddr),
.up_rdata(up_rdata),
.up_rack(up_rack)
);
// IRQ handling
@ -338,124 +338,124 @@ assign up_irq_source_clear = (up_wreq == 1'b1 && up_waddr == 12'h021) ? up_wdata
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
if (s_axi_aresetn == 1'b0)
irq <= 1'b0;
else
irq <= |up_irq_pending;
end
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_irq_source <= 2'b00;
end else begin
up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
end
if (s_axi_aresetn == 1'b0) begin
up_irq_source <= 2'b00;
end else begin
up_irq_source <= up_irq_trigger | (up_irq_source & ~up_irq_source_clear);
end
end
// Register Interface
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
up_enable <= 'h00;
up_pause <= 'h00;
up_dma_src_address <= 'h00;
up_dma_dest_address <= 'h00;
up_dma_y_length <= 'h00;
up_dma_x_length <= 'h00;
up_dma_dest_stride <= 'h00;
up_dma_src_stride <= 'h00;
up_irq_mask <= 3'b11;
up_dma_req_valid <= 1'b0;
up_scratch <= 'h00;
up_wack <= 1'b0;
end else begin
up_wack <= up_wreq;
if (up_enable == 1'b1) begin
if (up_wreq && up_waddr == 12'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot) begin
up_dma_req_valid <= 1'b0;
end
end else begin
up_dma_req_valid <= 1'b0;
end
if (s_axi_aresetn == 1'b0) begin
up_enable <= 'h00;
up_pause <= 'h00;
up_dma_src_address <= 'h00;
up_dma_dest_address <= 'h00;
up_dma_y_length <= 'h00;
up_dma_x_length <= 'h00;
up_dma_dest_stride <= 'h00;
up_dma_src_stride <= 'h00;
up_irq_mask <= 3'b11;
up_dma_req_valid <= 1'b0;
up_scratch <= 'h00;
up_wack <= 1'b0;
end else begin
up_wack <= up_wreq;
if (up_enable == 1'b1) begin
if (up_wreq && up_waddr == 12'h102) begin
up_dma_req_valid <= up_dma_req_valid | up_wdata[0];
end else if (up_sot) begin
up_dma_req_valid <= 1'b0;
end
end else begin
up_dma_req_valid <= 1'b0;
end
if (up_wreq) begin
case (up_waddr)
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
if (up_wreq) begin
case (up_waddr)
12'h002: up_scratch <= up_wdata;
12'h020: up_irq_mask <= up_wdata;
12'h100: {up_pause, up_enable} <= up_wdata[1:0];
12'h103: begin
if (CYCLIC) up_dma_cyclic <= up_wdata[0];
up_axis_xlast <= up_wdata[1];
end
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
endcase
end
end
12'h104: up_dma_dest_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_DEST];
12'h105: up_dma_src_address <= up_wdata[31:BYTES_PER_BEAT_WIDTH_SRC];
12'h106: up_dma_x_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h107: up_dma_y_length <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h108: up_dma_dest_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
12'h109: up_dma_src_stride <= up_wdata[DMA_LENGTH_WIDTH-1:0];
endcase
end
end
end
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0) begin
if (s_axi_aresetn == 1'b0) begin
up_rack <= 'd0;
up_rdata <= 'h00;
end else begin
up_rdata <= 'h00;
end else begin
up_rack <= up_rreq;
case (up_raddr)
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h020: up_rdata <= up_irq_mask;
12'h021: up_rdata <= up_irq_pending;
12'h022: up_rdata <= up_irq_source;
12'h100: up_rdata <= {up_pause, up_enable};
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h10a: up_rdata <= up_transfer_done_bitmap;
12'h10b: up_rdata <= up_transfer_id_eot;
12'h10c: up_rdata <= 'h00; // Status
12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
12'h110: up_rdata <= dbg_status;
default: up_rdata <= 'h00;
endcase
end
case (up_raddr)
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h020: up_rdata <= up_irq_mask;
12'h021: up_rdata <= up_irq_pending;
12'h022: up_rdata <= up_irq_source;
12'h100: up_rdata <= {up_pause, up_enable};
12'h101: up_rdata <= up_transfer_id;
12'h102: up_rdata <= up_dma_req_valid;
12'h103: up_rdata <= {30'h00, up_axis_xlast, up_dma_cyclic}; // Flags
12'h104: up_rdata <= HAS_DEST_ADDR ? {up_dma_dest_address,{BYTES_PER_BEAT_WIDTH_DEST{1'b0}}} : 'h00;
12'h105: up_rdata <= HAS_SRC_ADDR ? {up_dma_src_address,{BYTES_PER_BEAT_WIDTH_SRC{1'b0}}} : 'h00;
12'h106: up_rdata <= up_dma_x_length;
12'h107: up_rdata <= DMA_2D_TRANSFER ? up_dma_y_length : 'h00;
12'h108: up_rdata <= DMA_2D_TRANSFER ? up_dma_dest_stride : 'h00;
12'h109: up_rdata <= DMA_2D_TRANSFER ? up_dma_src_stride : 'h00;
12'h10a: up_rdata <= up_transfer_done_bitmap;
12'h10b: up_rdata <= up_transfer_id_eot;
12'h10c: up_rdata <= 'h00; // Status
12'h10d: up_rdata <= m_dest_axi_awaddr; //HAS_DEST_ADDR ? 'h00 : 'h00; // Current dest address
12'h10e: up_rdata <= m_src_axi_araddr; //HAS_SRC_ADDR ? 'h00 : 'h00; // Current src address
12'h10f: up_rdata <= {src_response_id, 1'b0, src_data_id, 1'b0, src_address_id, 1'b0, src_request_id,
1'b0, dest_response_id, 1'b0, dest_data_id, 1'b0, dest_address_id, 1'b0, dest_request_id};
12'h110: up_rdata <= dbg_status;
default: up_rdata <= 'h00;
endcase
end
end
// Request ID and Request done bitmap handling
always @(posedge s_axi_aclk)
begin
if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
up_transfer_id <= 'h0;
up_transfer_id_eot <= 'h0;
up_transfer_done_bitmap <= 'h0;
end begin
if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
up_transfer_id <= up_transfer_id + 1'b1;
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
end
if (up_eot == 1'b1) begin
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
end
end
if (s_axi_aresetn == 1'b0 || up_enable == 1'b0) begin
up_transfer_id <= 'h0;
up_transfer_id_eot <= 'h0;
up_transfer_done_bitmap <= 'h0;
end begin
if (up_dma_req_valid == 1'b1 && up_dma_req_ready == 1'b1) begin
up_transfer_id <= up_transfer_id + 1'b1;
up_transfer_done_bitmap[up_transfer_id] <= 1'b0;
end
if (up_eot == 1'b1) begin
up_transfer_done_bitmap[up_transfer_id_eot] <= 1'b1;
up_transfer_id_eot <= up_transfer_id_eot + 1'b1;
end
end
end
wire dma_req_valid;
@ -474,32 +474,32 @@ assign up_eot = up_dma_cyclic ? 1'b0 : up_req_eot;
generate if (DMA_2D_TRANSFER == 1) begin
dmac_2d_transfer #(
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC)
) i_2d_transfer (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.req_eot(up_req_eot),
.req_eot(up_req_eot),
.req_valid(up_dma_req_valid),
.req_ready(up_dma_req_ready),
.req_dest_address(up_dma_dest_address),
.req_src_address(up_dma_src_address),
.req_x_length(up_dma_x_length),
.req_y_length(up_dma_y_length),
.req_dest_stride(up_dma_dest_stride),
.req_src_stride(up_dma_src_stride),
.req_sync_transfer_start(up_dma_sync_transfer_start),
.req_valid(up_dma_req_valid),
.req_ready(up_dma_req_ready),
.req_dest_address(up_dma_dest_address),
.req_src_address(up_dma_src_address),
.req_x_length(up_dma_x_length),
.req_y_length(up_dma_y_length),
.req_dest_stride(up_dma_dest_stride),
.req_src_stride(up_dma_src_stride),
.req_sync_transfer_start(up_dma_sync_transfer_start),
.out_req_valid(dma_req_valid),
.out_req_ready(dma_req_ready),
.out_req_dest_address(dma_req_dest_address),
.out_req_src_address(dma_req_src_address),
.out_req_length(dma_req_length),
.out_req_sync_transfer_start(dma_req_sync_transfer_start),
.out_eot(dma_req_eot)
.out_req_valid(dma_req_valid),
.out_req_ready(dma_req_ready),
.out_req_dest_address(dma_req_dest_address),
.out_req_src_address(dma_req_src_address),
.out_req_length(dma_req_length),
.out_req_sync_transfer_start(dma_req_sync_transfer_start),
.out_eot(dma_req_eot)
);
end else begin
@ -515,123 +515,123 @@ assign up_req_eot = dma_req_eot;
end endgenerate
dmac_request_arb #(
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.DMA_TYPE_DEST(DMA_TYPE_DEST),
.DMA_TYPE_SRC(DMA_TYPE_SRC),
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
.AXI_SLICE_DEST(AXI_SLICE_DEST),
.AXI_SLICE_SRC(AXI_SLICE_SRC),
.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
.FIFO_SIZE(FIFO_SIZE)
.DMA_DATA_WIDTH_SRC(DMA_DATA_WIDTH_SRC),
.DMA_DATA_WIDTH_DEST(DMA_DATA_WIDTH_DEST),
.DMA_LENGTH_WIDTH(DMA_LENGTH_WIDTH),
.BYTES_PER_BEAT_WIDTH_DEST(BYTES_PER_BEAT_WIDTH_DEST),
.BYTES_PER_BEAT_WIDTH_SRC(BYTES_PER_BEAT_WIDTH_SRC),
.DMA_TYPE_DEST(DMA_TYPE_DEST),
.DMA_TYPE_SRC(DMA_TYPE_SRC),
.ASYNC_CLK_REQ_SRC(ASYNC_CLK_REQ_SRC),
.ASYNC_CLK_SRC_DEST(ASYNC_CLK_SRC_DEST),
.ASYNC_CLK_DEST_REQ(ASYNC_CLK_DEST_REQ),
.AXI_SLICE_DEST(AXI_SLICE_DEST),
.AXI_SLICE_SRC(AXI_SLICE_SRC),
.MAX_BYTES_PER_BURST(MAX_BYTES_PER_BURST),
.FIFO_SIZE(FIFO_SIZE)
) i_request_arb (
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.req_aclk(s_axi_aclk),
.req_aresetn(s_axi_aresetn),
.enable(up_enable),
.pause(up_pause),
.enable(up_enable),
.pause(up_pause),
.req_valid(dma_req_valid),
.req_ready(dma_req_ready),
.req_dest_address(dma_req_dest_address),
.req_src_address(dma_req_src_address),
.req_length(dma_req_length),
.req_valid(dma_req_valid),
.req_ready(dma_req_ready),
.req_dest_address(dma_req_dest_address),
.req_src_address(dma_req_src_address),
.req_length(dma_req_length),
.req_xlast(up_axis_xlast),
.req_sync_transfer_start(dma_req_sync_transfer_start),
.req_sync_transfer_start(dma_req_sync_transfer_start),
.eot(dma_req_eot),
.eot(dma_req_eot),
.m_dest_axi_aclk(m_dest_axi_aclk),
.m_dest_axi_aresetn(m_dest_axi_aresetn),
.m_src_axi_aclk(m_src_axi_aclk),
.m_src_axi_aresetn(m_src_axi_aresetn),
.m_dest_axi_aclk(m_dest_axi_aclk),
.m_dest_axi_aresetn(m_dest_axi_aresetn),
.m_src_axi_aclk(m_src_axi_aclk),
.m_src_axi_aresetn(m_src_axi_aresetn),
.m_axi_awaddr(m_dest_axi_awaddr),
.m_axi_awlen(m_dest_axi_awlen),
.m_axi_awsize(m_dest_axi_awsize),
.m_axi_awburst(m_dest_axi_awburst),
.m_axi_awprot(m_dest_axi_awprot),
.m_axi_awcache(m_dest_axi_awcache),
.m_axi_awvalid(m_dest_axi_awvalid),
.m_axi_awready(m_dest_axi_awready),
.m_axi_awaddr(m_dest_axi_awaddr),
.m_axi_awlen(m_dest_axi_awlen),
.m_axi_awsize(m_dest_axi_awsize),
.m_axi_awburst(m_dest_axi_awburst),
.m_axi_awprot(m_dest_axi_awprot),
.m_axi_awcache(m_dest_axi_awcache),
.m_axi_awvalid(m_dest_axi_awvalid),
.m_axi_awready(m_dest_axi_awready),
.m_axi_wdata(m_dest_axi_wdata),
.m_axi_wstrb(m_dest_axi_wstrb),
.m_axi_wready(m_dest_axi_wready),
.m_axi_wvalid(m_dest_axi_wvalid),
.m_axi_wlast(m_dest_axi_wlast),
.m_axi_wdata(m_dest_axi_wdata),
.m_axi_wstrb(m_dest_axi_wstrb),
.m_axi_wready(m_dest_axi_wready),
.m_axi_wvalid(m_dest_axi_wvalid),
.m_axi_wlast(m_dest_axi_wlast),
.m_axi_bvalid(m_dest_axi_bvalid),
.m_axi_bresp(m_dest_axi_bresp),
.m_axi_bready(m_dest_axi_bready),
.m_axi_bvalid(m_dest_axi_bvalid),
.m_axi_bresp(m_dest_axi_bresp),
.m_axi_bready(m_dest_axi_bready),
.m_axi_arready(m_src_axi_arready),
.m_axi_arvalid(m_src_axi_arvalid),
.m_axi_araddr(m_src_axi_araddr),
.m_axi_arlen(m_src_axi_arlen),
.m_axi_arsize(m_src_axi_arsize),
.m_axi_arburst(m_src_axi_arburst),
.m_axi_arprot(m_src_axi_arprot),
.m_axi_arcache(m_src_axi_arcache),
.m_axi_arready(m_src_axi_arready),
.m_axi_arvalid(m_src_axi_arvalid),
.m_axi_araddr(m_src_axi_araddr),
.m_axi_arlen(m_src_axi_arlen),
.m_axi_arsize(m_src_axi_arsize),
.m_axi_arburst(m_src_axi_arburst),
.m_axi_arprot(m_src_axi_arprot),
.m_axi_arcache(m_src_axi_arcache),
.m_axi_rdata(m_src_axi_rdata),
.m_axi_rready(m_src_axi_rready),
.m_axi_rvalid(m_src_axi_rvalid),
.m_axi_rresp(m_src_axi_rresp),
.m_axi_rdata(m_src_axi_rdata),
.m_axi_rready(m_src_axi_rready),
.m_axi_rvalid(m_src_axi_rvalid),
.m_axi_rresp(m_src_axi_rresp),
.s_axis_aclk(s_axis_aclk),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req),
.s_axis_aclk(s_axis_aclk),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_data(s_axis_data),
.s_axis_user(s_axis_user),
.s_axis_xfer_req(s_axis_xfer_req),
.m_axis_aclk(m_axis_aclk),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_aclk(m_axis_aclk),
.m_axis_ready(m_axis_ready),
.m_axis_valid(m_axis_valid),
.m_axis_data(m_axis_data),
.m_axis_last(m_axis_last),
.m_axis_xfer_req(m_axis_xfer_req),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_wr_xfer_req(fifo_wr_xfer_req),
.fifo_wr_clk(fifo_wr_clk),
.fifo_wr_en(fifo_wr_en),
.fifo_wr_din(fifo_wr_din),
.fifo_wr_overflow(fifo_wr_overflow),
.fifo_wr_sync(fifo_wr_sync),
.fifo_wr_xfer_req(fifo_wr_xfer_req),
.fifo_rd_clk(fifo_rd_clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_clk(fifo_rd_clk),
.fifo_rd_en(fifo_rd_en),
.fifo_rd_valid(fifo_rd_valid),
.fifo_rd_dout(fifo_rd_dout),
.fifo_rd_underflow(fifo_rd_underflow),
.fifo_rd_xfer_req(fifo_rd_xfer_req),
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status)
// DBG
.dbg_dest_request_id(dest_request_id),
.dbg_dest_address_id(dest_address_id),
.dbg_dest_data_id(dest_data_id),
.dbg_dest_response_id(dest_response_id),
.dbg_src_request_id(src_request_id),
.dbg_src_address_id(src_address_id),
.dbg_src_data_id(src_data_id),
.dbg_src_response_id(src_response_id),
.dbg_status(dbg_status)
);
assign m_dest_axi_arvalid = 1'b0;

56
library/axi_dmac/axi_register_slice.v
View File

@ -36,16 +36,16 @@
// ***************************************************************************
module axi_register_slice (
input clk,
input resetn,
input clk,
input resetn,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
input s_axi_valid,
output s_axi_ready,
input [DATA_WIDTH-1:0] s_axi_data,
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
output m_axi_valid,
input m_axi_ready,
output [DATA_WIDTH-1:0] m_axi_data
);
parameter DATA_WIDTH = 32;
@ -79,19 +79,19 @@ assign fwd_valid_s = fwd_valid;
assign fwd_data_s = fwd_data;
always @(posedge clk) begin
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
if (~fwd_valid | m_axi_ready)
fwd_data <= bwd_data_s;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
if (resetn == 1'b0) begin
fwd_valid <= 1'b0;
end else begin
if (bwd_valid_s)
fwd_valid <= 1'b1;
else if (m_axi_ready)
fwd_valid <= 1'b0;
end
end
end else begin
@ -111,19 +111,19 @@ assign bwd_data_s = bwd_ready ? s_axi_data : bwd_data;
assign bwd_ready_s = bwd_ready;
always @(posedge clk) begin
if (bwd_ready)
bwd_data <= s_axi_data;
if (bwd_ready)
bwd_data <= s_axi_data;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
if (resetn == 1'b0) begin
bwd_ready <= 1'b1;
end else begin
if (fwd_ready_s)
bwd_ready <= 1'b1;
else if (s_axi_valid)
bwd_ready <= 1'b0;
end
end
end else begin

134
library/axi_dmac/data_mover.v
View File

@ -37,31 +37,31 @@
// ***************************************************************************
module dmac_data_mover (
input clk,
input resetn,
input clk,
input resetn,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
input enable,
output reg enabled,
input enable,
output reg enabled,
output xfer_req,
output xfer_req,
output s_axi_ready,
input s_axi_valid,
input [DATA_WIDTH-1:0] s_axi_data,
output s_axi_ready,
input s_axi_valid,
input [DATA_WIDTH-1:0] s_axi_data,
input m_axi_ready,
output m_axi_valid,
output [DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
input m_axi_ready,
output m_axi_valid,
output [DATA_WIDTH-1:0] m_axi_data,
output m_axi_last,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length
);
parameter ID_WIDTH = 3;
@ -104,73 +104,73 @@ assign last_load = s_axi_ready && s_axi_valid && last_eot && eot;
assign req_ready = last_load || ~active;
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)
enabled <= 1'b0;
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id)
enabled <= 1'b0;
end
end
end
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable) begin
enabled <= 1'b1;
end else begin
if (DISABLE_WAIT_FOR_ID == 0) begin
// We are not allowed to just deassert valid, so wait until the
// current beat has been accepted
if (~s_axi_valid || m_axi_ready)
enabled <= 1'b0;
end else begin
// For memory mapped AXI busses we have to complete all pending
// burst requests before we can disable the data mover.
if (response_id == request_id)
enabled <= 1'b0;
end
end
end
end
always @(posedge clk) begin
if (req_ready) begin
last_eot <= req_last_burst_length == 'h0;
last_non_eot <= 1'b0;
beat_counter <= 'h1;
end else if (s_axi_ready && s_axi_valid) begin
last_eot <= beat_counter == last_burst_length;
last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
beat_counter <= beat_counter + 1;
end
if (req_ready) begin
last_eot <= req_last_burst_length == 'h0;
last_non_eot <= 1'b0;
beat_counter <= 'h1;
end else if (s_axi_ready && s_axi_valid) begin
last_eot <= beat_counter == last_burst_length;
last_non_eot <= beat_counter == MAX_BEATS_PER_BURST - 1;
beat_counter <= beat_counter + 1;
end
end
always @(posedge clk) begin
if (req_ready)
last_burst_length <= req_last_burst_length;
if (req_ready)
last_burst_length <= req_last_burst_length;
end
always @(posedge clk) begin
if (enabled == 1'b0 || resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid) begin
active <= 1'b1;
end else if (last_load) begin
active <= 1'b0;
end
if (enabled == 1'b0 || resetn == 1'b0) begin
active <= 1'b0;
end else if (req_valid) begin
active <= 1'b1;
end else if (last_load) begin
active <= 1'b0;
end
end
always @(*)
begin
if ((s_axi_ready && s_axi_valid && last) ||
(sync_id && pending_burst))
id_next <= inc_id(id);
else
id_next <= id;
if ((s_axi_ready && s_axi_valid && last) ||
(sync_id && pending_burst))
id_next <= inc_id(id);
else
id_next <= id;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
id <= id_next;
end
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
id <= id_next;
end
end
always @(posedge clk) begin
pending_burst <= id_next != request_id;
pending_burst <= id_next != request_id;
end
endmodule

252
library/axi_dmac/dest_axi_mm.v
View File

@ -37,60 +37,60 @@
// ***************************************************************************
module dmac_dest_mm_axi (
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
input req_valid,
output req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input [BYTES_PER_BEAT_WIDTH-1:0] req_last_beat_bytes,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
output response_valid,
input response_ready,
output [1:0] response_resp,
output response_resp_eot,
output response_valid,
input response_ready,
output [1:0] response_resp,
output response_resp_eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
input response_eot,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
input response_eot,
input fifo_valid,
output fifo_ready,
input [DMA_DATA_WIDTH-1:0] fifo_data,
input fifo_valid,
output fifo_ready,
input [DMA_DATA_WIDTH-1:0] fifo_data,
// Write address
input m_axi_awready,
output m_axi_awvalid,
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
// Write address
input m_axi_awready,
output m_axi_awvalid,
output [31:0] m_axi_awaddr,
output [ 7:0] m_axi_awlen,
output [ 2:0] m_axi_awsize,
output [ 1:0] m_axi_awburst,
output [ 2:0] m_axi_awprot,
output [ 3:0] m_axi_awcache,
// Write data
output [DMA_DATA_WIDTH-1:0] m_axi_wdata,
output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write data
output [DMA_DATA_WIDTH-1:0] m_axi_wdata,
output [(DMA_DATA_WIDTH/8)-1:0] m_axi_wstrb,
input m_axi_wready,
output m_axi_wvalid,
output m_axi_wlast,
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready
// Write response
input m_axi_bvalid,
input [ 1:0] m_axi_bresp,
output m_axi_bready
);
parameter ID_WIDTH = 3;
@ -113,120 +113,120 @@ wire _fifo_ready;
assign fifo_ready = _fifo_ready | ~enabled;
splitter #(
.NUM_M(2)
.NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
);
dmac_address_generator #(
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.id(address_id),
.request_id(request_id),
.sync_id(sync_id),
.id(address_id),
.request_id(request_id),
.sync_id(sync_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.eot(address_eot),
.eot(address_eot),
.addr_ready(m_axi_awready),
.addr_valid(m_axi_awvalid),
.addr(m_axi_awaddr),
.len(m_axi_awlen),
.size(m_axi_awsize),
.burst(m_axi_awburst),
.prot(m_axi_awprot),
.cache(m_axi_awcache)
.addr_ready(m_axi_awready),
.addr_valid(m_axi_awvalid),
.addr(m_axi_awaddr),
.len(m_axi_awlen),
.size(m_axi_awsize),
.burst(m_axi_awburst),
.prot(m_axi_awprot),
.cache(m_axi_awcache)
);
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(address_enabled),
.enabled(data_enabled),
.enable(address_enabled),
.enabled(data_enabled),
.xfer_req(),
.xfer_req(),
.request_id(address_id),
.response_id(data_id),
.sync_id(sync_id),
.eot(data_eot),
.request_id(address_id),
.response_id(data_id),
.sync_id(sync_id),
.eot(data_eot),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_valid(fifo_valid),
.s_axi_ready(_fifo_ready),
.s_axi_data(fifo_data),
.m_axi_valid(m_axi_wvalid),
.m_axi_ready(m_axi_wready),
.m_axi_data(m_axi_wdata),
.m_axi_last(m_axi_wlast)
.s_axi_valid(fifo_valid),
.s_axi_ready(_fifo_ready),
.s_axi_data(fifo_data),
.m_axi_valid(m_axi_wvalid),
.m_axi_ready(m_axi_wready),
.m_axi_data(m_axi_wdata),
.m_axi_last(m_axi_wlast)
);
always @(*)
begin
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
end
if (data_eot & m_axi_wlast) begin
wstrb <= (1 << (req_last_beat_bytes + 1)) - 1;
end else begin
wstrb <= {(DMA_DATA_WIDTH/8){1'b1}};
end
end
assign m_axi_wstrb = wstrb;
dmac_response_handler #(
.ID_WIDTH(ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_handler (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.bvalid(m_axi_bvalid),
.bready(m_axi_bready),
.bresp(m_axi_bresp),
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.bvalid(m_axi_bvalid),
.bready(m_axi_bready),
.bresp(m_axi_bresp),
.enable(data_enabled),
.enabled(enabled),
.enable(data_enabled),
.enabled(enabled),
.id(response_id),
.request_id(data_id),
.sync_id(sync_id),
.id(response_id),
.request_id(data_id),
.sync_id(sync_id),
.eot(response_eot),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_resp(response_resp),
.resp_eot(response_resp_eot)
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_resp(response_resp),
.resp_eot(response_resp_eot)
);
endmodule

118
library/axi_dmac/dest_axi_stream.v
View File

@ -37,39 +37,39 @@
// ***************************************************************************
module dmac_dest_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
output xfer_req,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input m_axis_ready,
output m_axis_valid,
output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
input m_axis_ready,
output m_axis_valid,
output [S_AXIS_DATA_WIDTH-1:0] m_axis_data,
output m_axis_last,
output fifo_ready,
input fifo_valid,
input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
output fifo_ready,
input fifo_valid,
input [S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_xlast,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter ID_WIDTH = 3;
@ -97,56 +97,56 @@ end
assign m_axis_last = (req_xlast_d == 1'b1) ? m_axis_last_s : 1'b0;
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.LAST(1)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.LAST(1)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.m_axi_ready(m_axis_ready),
.m_axi_valid(m_axis_valid),
.m_axi_data(m_axis_data),
.m_axi_last(m_axis_last_s),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data)
);
dmac_response_generator # (
.ID_WIDTH(ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
assign fifo_ready = _fifo_ready | ~enabled;

130
library/axi_dmac/dest_fifo_inf.v
View File

@ -37,39 +37,39 @@
// ***************************************************************************
module dmac_dest_fifo_inf (
input clk,
input resetn,
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
input data_eot,
input response_eot,
input en,
output [DATA_WIDTH-1:0] dout,
output valid,
output underflow,
input en,
output [DATA_WIDTH-1:0] dout,
output valid,
output underflow,
output xfer_req,
output fifo_ready,
input fifo_valid,
input [DATA_WIDTH-1:0] fifo_data,
output fifo_ready,
input fifo_valid,
input [DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
output response_valid,
input response_ready,
output response_resp_eot,
output [1:0] response_resp
);
parameter ID_WIDTH = 3;
@ -88,11 +88,11 @@ wire data_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
if (resetn == 1'b0) begin
en_d1 <= 1'b0;
end else begin
en_d1 <= en;
end
end
assign underflow = en_d1 & (~data_valid | ~enable);
@ -100,55 +100,55 @@ assign data_ready = en_d1 & (data_valid | ~enable);
assign valid = en_d1 & data_valid & enable;
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.DISABLE_WAIT_FOR_ID(0)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.enable(enable),
.enabled(data_enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.request_id(request_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout),
.m_axi_last()
.s_axi_ready(_fifo_ready),
.s_axi_valid(fifo_valid),
.s_axi_data(fifo_data),
.m_axi_ready(data_ready),
.m_axi_valid(data_valid),
.m_axi_data(dout),
.m_axi_last()
);
dmac_response_generator # (
.ID_WIDTH(ID_WIDTH)
.ID_WIDTH(ID_WIDTH)
) i_response_generator (
.clk(clk),
.resetn(resetn),
.clk(clk),
.resetn(resetn),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.enable(data_enabled),
.enabled(enabled),
.sync_id(sync_id),
.request_id(data_id),
.response_id(response_id),
.request_id(data_id),
.response_id(response_id),
.eot(response_eot),
.eot(response_eot),
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
.resp_valid(response_valid),
.resp_ready(response_ready),
.resp_eot(response_resp_eot),
.resp_resp(response_resp)
);
endmodule

1064
library/axi_dmac/request_arb.v
View File

File diff suppressed because it is too large Load Diff

58
library/axi_dmac/request_generator.v
View File

@ -37,20 +37,20 @@
// ***************************************************************************
module dmac_request_generator (
input req_aclk,
input req_aresetn,
input req_aclk,
input req_aresetn,
output [ID_WIDTH-1:0] request_id,
input [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] request_id,
input [ID_WIDTH-1:0] response_id,
input req_valid,
output reg req_ready,
input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input req_valid,
output reg req_ready,
input [BURSTS_PER_TRANSFER_WIDTH-1:0] req_burst_count,
input enable,
input pause,
input enable,
input pause,
output eot
output eot
);
parameter ID_WIDTH = 3;
@ -74,25 +74,25 @@ assign request_id = id;
always @(posedge req_aclk)
begin
if (req_aresetn == 1'b0) begin
burst_count <= 'h00;
id <= 'h0;
req_ready <= 1'b1;
end else if (enable == 1'b0) begin
req_ready <= 1'b1;
end else begin
if (req_ready) begin
if (req_valid && enable) begin
burst_count <= req_burst_count;
req_ready <= 1'b0;
end
end else if (response_id != id_next && ~pause) begin
if (eot)
req_ready <= 1'b1;
burst_count <= burst_count - 1'b1;
id <= id_next;
end
end
if (req_aresetn == 1'b0) begin
burst_count <= 'h00;
id <= 'h0;
req_ready <= 1'b1;
end else if (enable == 1'b0) begin
req_ready <= 1'b1;
end else begin
if (req_ready) begin
if (req_valid && enable) begin
burst_count <= req_burst_count;
req_ready <= 1'b0;
end
end else if (response_id != id_next && ~pause) begin
if (eot)
req_ready <= 1'b1;
burst_count <= burst_count - 1'b1;
id <= id_next;
end
end
end
endmodule

54
library/axi_dmac/response_generator.v
View File

@ -37,22 +37,22 @@
// ***************************************************************************
module dmac_response_generator (
input clk,
input resetn,
input clk,
input resetn,
input enable,
output reg enabled,
input enable,
output reg enabled,
input [ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] response_id,
input sync_id,
input [ID_WIDTH-1:0] request_id,
output reg [ID_WIDTH-1:0] response_id,
input sync_id,
input eot,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
parameter ID_WIDTH = 3;
@ -67,24 +67,24 @@ assign resp_valid = request_id != response_id && enabled;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (request_id == response_id)
enabled <= 1'b0;
end
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (request_id == response_id)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
response_id <= 'h0;
end else begin
if ((resp_valid && resp_ready) ||
(sync_id && response_id != request_id))
response_id <= inc_id(response_id);
end
if (resetn == 1'b0) begin
response_id <= 'h0;
end else begin
if ((resp_valid && resp_ready) ||
(sync_id && response_id != request_id))
response_id <= inc_id(response_id);
end
end
endmodule

60
library/axi_dmac/response_handler.v
View File

@ -37,26 +37,26 @@
// ***************************************************************************
module dmac_response_handler (
input clk,
input resetn,
input clk,
input resetn,
input bvalid,
output bready,
input [1:0] bresp,
input bvalid,
output bready,
input [1:0] bresp,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
output reg [ID_WIDTH-1:0] id,
input [ID_WIDTH-1:0] request_id,
input sync_id,
input enable,
output reg enabled,
input enable,
output reg enabled,
input eot,
input eot,
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
output resp_valid,
input resp_ready,
output resp_eot,
output [1:0] resp_resp
);
parameter ID_WIDTH = 3;
@ -74,24 +74,24 @@ assign resp_valid = active && bvalid;
// We have to wait for all responses before we can disable the response handler
always @(posedge clk) begin
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (request_id == id)
enabled <= 1'b0;
end
if (resetn == 1'b0) begin
enabled <= 1'b0;
end else begin
if (enable)
enabled <= 1'b1;
else if (request_id == id)
enabled <= 1'b0;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
if ((bready && bvalid) ||
(sync_id && id != request_id))
id <= inc_id(id);
end
if (resetn == 1'b0) begin
id <= 'h0;
end else begin
if ((bready && bvalid) ||
(sync_id && id != request_id))
id <= inc_id(id);
end
end
endmodule

28
library/axi_dmac/splitter.v
View File

@ -37,14 +37,14 @@
module splitter (
input clk,
input resetn,
input clk,
input resetn,
input s_valid,
output s_ready,
input s_valid,
output s_ready,
output [NUM_M-1:0] m_valid,
input [NUM_M-1:0] m_ready
output [NUM_M-1:0] m_valid,
input [NUM_M-1:0] m_ready
);
parameter NUM_M = 2;
@ -56,14 +56,14 @@ assign m_valid = s_valid ? ~acked : {NUM_M{1'b0}};
always @(posedge clk)
begin
if (resetn == 1'b0) begin
acked <= {NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end
if (resetn == 1'b0) begin
acked <= {NUM_M{1'b0}};
end else begin
if (s_valid & s_ready)
acked <= {NUM_M{1'b0}};
else
acked <= acked | (m_ready & m_valid);
end
end
endmodule

202
library/axi_dmac/src_axi_mm.v
View File

@ -37,51 +37,51 @@
// ***************************************************************************
module dmac_src_mm_axi (
input m_axi_aclk,
input m_axi_aresetn,
input m_axi_aclk,
input m_axi_aresetn,
input req_valid,
output req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_valid,
output req_ready,
input [31:BYTES_PER_BEAT_WIDTH] req_address,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input pause,
input sync_id,
output sync_id_ret,
output response_valid,
input response_ready,
output [1:0] response_resp,
output response_valid,
input response_ready,
output [1:0] response_resp,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
output [ID_WIDTH-1:0] data_id,
output [ID_WIDTH-1:0] address_id,
input data_eot,
input address_eot,
output fifo_valid,
input fifo_ready,
output [DMA_DATA_WIDTH-1:0] fifo_data,
output fifo_valid,
input fifo_ready,
output [DMA_DATA_WIDTH-1:0] fifo_data,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
output [ 7:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read address
input m_axi_arready,
output m_axi_arvalid,
output [31:0] m_axi_araddr,
output [ 7:0] m_axi_arlen,
output [ 2:0] m_axi_arsize,
output [ 1:0] m_axi_arburst,
output [ 2:0] m_axi_arprot,
output [ 3:0] m_axi_arcache,
// Read data and response
input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp
// Read data and response
input [DMA_DATA_WIDTH-1:0] m_axi_rdata,
output m_axi_rready,
input m_axi_rvalid,
input [ 1:0] m_axi_rresp
);
parameter ID_WIDTH = 3;
@ -105,95 +105,95 @@ assign response_valid = 1'b0;
assign response_resp = RESP_OKAY;
splitter #(
.NUM_M(2)
.NUM_M(2)
) i_req_splitter (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.s_valid(req_valid),
.s_ready(req_ready),
.m_valid({
address_req_valid,
data_req_valid
}),
.m_ready({
address_req_ready,
data_req_ready
})
);
dmac_address_generator #(
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
.ID_WIDTH(ID_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH),
.BYTES_PER_BEAT_WIDTH(BYTES_PER_BEAT_WIDTH),
.DMA_DATA_WIDTH(DMA_DATA_WIDTH)
) i_addr_gen (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.sync_id(sync_id),
.enable(enable),
.enabled(address_enabled),
.pause(pause),
.sync_id(sync_id),
.request_id(request_id),
.id(address_id),
.request_id(request_id),
.id(address_id),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.req_valid(address_req_valid),
.req_ready(address_req_ready),
.req_address(req_address),
.req_last_burst_length(req_last_burst_length),
.eot(address_eot),
.eot(address_eot),
.addr_ready(m_axi_arready),
.addr_valid(m_axi_arvalid),
.addr(m_axi_araddr),
.len(m_axi_arlen),
.size(m_axi_arsize),
.burst(m_axi_arburst),
.prot(m_axi_arprot),
.cache(m_axi_arcache)
.addr_ready(m_axi_arready),
.addr_valid(m_axi_arvalid),
.addr(m_axi_araddr),
.len(m_axi_arlen),
.size(m_axi_arsize),
.burst(m_axi_arburst),
.prot(m_axi_arprot),
.cache(m_axi_arcache)
);
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DMA_DATA_WIDTH),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.clk(m_axi_aclk),
.resetn(m_axi_aresetn),
.enable(address_enabled),
.enabled(enabled),
.sync_id(sync_id),
.enable(address_enabled),
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(),
.xfer_req(),
.request_id(address_id),
.response_id(data_id),
.eot(data_eot),
.request_id(address_id),
.response_id(data_id),
.eot(data_eot),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(data_req_valid),
.req_ready(data_req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_valid(m_axi_rvalid),
.s_axi_ready(m_axi_rready),
.s_axi_data(m_axi_rdata),
.m_axi_valid(fifo_valid),
.m_axi_ready(fifo_ready),
.m_axi_data(fifo_data),
.m_axi_last()
.s_axi_valid(m_axi_rvalid),
.s_axi_ready(m_axi_rready),
.s_axi_data(m_axi_rdata),
.m_axi_valid(fifo_valid),
.m_axi_ready(fifo_ready),
.m_axi_data(fifo_data),
.m_axi_last()
);
reg [1:0] rresp;
always @(posedge m_axi_aclk)
begin
if (m_axi_rvalid && m_axi_rready) begin
if (m_axi_rresp != 2'b0)
rresp <= m_axi_rresp;
end
if (m_axi_rvalid && m_axi_rready) begin
if (m_axi_rresp != 2'b0)
rresp <= m_axi_rresp;
end
end
endmodule

104
library/axi_dmac/src_axi_stream.v
View File

@ -37,32 +37,32 @@
// ***************************************************************************
module dmac_src_axi_stream (
input s_axis_aclk,
input s_axis_aresetn,
input s_axis_aclk,
input s_axis_aresetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
output s_axis_ready,
input s_axis_valid,
input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
output s_axis_ready,
input s_axis_valid,
input [S_AXIS_DATA_WIDTH-1:0] s_axis_data,
input [0:0] s_axis_user,
output s_axis_xfer_req,
input fifo_ready,
output fifo_valid,
output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
input fifo_ready,
output fifo_valid,
output [S_AXIS_DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter ID_WIDTH = 3;
@ -78,46 +78,46 @@ assign sync_id_ret = sync_id;
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (s_axis_valid && s_axis_ready && sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
if (s_axis_aresetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (s_axis_valid && s_axis_ready && sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(S_AXIS_DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.clk(s_axis_aclk),
.resetn(s_axis_aresetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(s_axis_xfer_req),
.xfer_req(s_axis_xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(s_axis_ready),
.s_axi_valid(sync_valid),
.s_axi_data(s_axis_data),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
.s_axi_ready(s_axis_ready),
.s_axi_valid(sync_valid),
.s_axi_data(s_axis_data),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data)
);
endmodule

124
library/axi_dmac/src_fifo_inf.v
View File

@ -37,32 +37,32 @@
// ***************************************************************************
module dmac_src_fifo_inf (
input clk,
input resetn,
input clk,
input resetn,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input enable,
output enabled,
input sync_id,
output sync_id_ret,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
input [ID_WIDTH-1:0] request_id,
output [ID_WIDTH-1:0] response_id,
input eot,
input en,
input [DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
input en,
input [DATA_WIDTH-1:0] din,
output reg overflow,
input sync,
output xfer_req,
input fifo_ready,
output fifo_valid,
output [DATA_WIDTH-1:0] fifo_data,
input fifo_ready,
output fifo_valid,
output [DATA_WIDTH-1:0] fifo_data,
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
input req_valid,
output req_ready,
input [BEATS_PER_BURST_WIDTH-1:0] req_last_burst_length,
input req_sync_transfer_start
);
parameter ID_WIDTH = 3;
@ -77,62 +77,62 @@ wire sync_valid = en & ready & has_sync;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (ready && en && sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
if (resetn == 1'b0) begin
needs_sync <= 1'b0;
end else begin
if (ready && en && sync) begin
needs_sync <= 1'b0;
end else if (req_valid && req_ready) begin
needs_sync <= req_sync_transfer_start;
end
end
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
overflow <= 1'b0;
end else begin
if (enable) begin
overflow <= en & ~ready;
end else begin
overflow <= en;
end
end
if (resetn == 1'b0) begin
overflow <= 1'b0;
end else begin
if (enable) begin
overflow <= en & ~ready;
end else begin
overflow <= en;
end
end
end
assign sync_id_ret = sync_id;
dmac_data_mover # (
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
.ID_WIDTH(ID_WIDTH),
.DATA_WIDTH(DATA_WIDTH),
.DISABLE_WAIT_FOR_ID(0),
.BEATS_PER_BURST_WIDTH(BEATS_PER_BURST_WIDTH)
) i_data_mover (
.clk(clk),
.resetn(resetn),
.clk(clk),
.resetn(resetn),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.enable(enable),
.enabled(enabled),
.sync_id(sync_id),
.xfer_req(xfer_req),
.xfer_req(xfer_req),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.request_id(request_id),
.response_id(response_id),
.eot(eot),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.req_valid(req_valid),
.req_ready(req_ready),
.req_last_burst_length(req_last_burst_length),
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(din),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last()
.s_axi_ready(ready),
.s_axi_valid(sync_valid),
.s_axi_data(din),
.m_axi_ready(fifo_ready),
.m_axi_valid(fifo_valid),
.m_axi_data(fifo_data),
.m_axi_last()
);
endmodule

292
library/axi_generic_adc/axi_generic_adc.v
View File

@ -1,27 +1,27 @@
module axi_generic_adc (
input adc_clk,
output [NUM_OF_CHANNELS-1:0] adc_enable,
input adc_dovf,
input adc_clk,
output [NUM_OF_CHANNELS-1:0] adc_enable,
input adc_dovf,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input s_axi_aclk,
input s_axi_aresetn,
input s_axi_awvalid,
input [31:0] s_axi_awaddr,
output s_axi_awready,
input s_axi_wvalid,
input [31:0] s_axi_wdata,
input [ 3:0] s_axi_wstrb,
output s_axi_wready,
output s_axi_bvalid,
output [ 1:0] s_axi_bresp,
input s_axi_bready,
input s_axi_arvalid,
input [31:0] s_axi_araddr,
output s_axi_arready,
output s_axi_rvalid,
output [ 1:0] s_axi_rresp,
output [31:0] s_axi_rdata,
input s_axi_rready,
input [ 2:0] s_axi_awprot,
input [ 2:0] s_axi_arprot
@ -30,7 +30,7 @@ module axi_generic_adc (
parameter NUM_OF_CHANNELS = 2;
parameter ID = 0;
reg [31:0] up_rdata = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_rack = 'd0;
reg up_wack = 'd0;
@ -60,145 +60,145 @@ assign up_rstn = s_axi_aresetn;
integer j;
always @(*)
begin
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
up_rdata_r = 'h00;
up_rack_r = 'h00;
up_wack_r = 'h00;
for (j = 0; j <= NUM_OF_CHANNELS; j=j+1) begin
up_rack_r = up_rack_r | up_rack_s[j];
up_wack_r = up_wack_r | up_wack_s[j];
up_rdata_r = up_rdata_r | up_rdata_s[j];
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
if (up_rstn == 0) begin
up_rdata <= 'd0;
up_rack <= 'd0;
up_wack <= 'd0;
end else begin
up_rdata <= up_rdata_r;
up_rack <= up_rack_r;
up_wack <= up_wack_r;
end
end
up_adc_common #(.ID(ID)) i_up_adc_common (
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_status_ovf (adc_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd1),
.mmcm_rst (),
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_r1_mode (),
.adc_ddr_edgesel (),
.adc_pin_mode (),
.adc_status ('h00),
.adc_status_ovf (adc_dovf),
.adc_status_unf (1'b0),
.adc_clk_ratio (32'd1),
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_OF_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
.up_rack (up_rack_s[NUM_OF_CHANNELS]));
.up_status_pn_err (1'b0),
.up_status_pn_oos (1'b0),
.up_status_or (1'b0),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),
.up_drp_wdata (),
.up_drp_rdata (32'd0),
.up_drp_ready (1'd0),
.up_drp_locked (1'd1),
.up_usr_chanmax (),
.adc_usr_chanmax (8'd0),
.up_adc_gpio_in (),
.up_adc_gpio_out (),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[NUM_OF_CHANNELS]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[NUM_OF_CHANNELS]),
.up_rack (up_rack_s[NUM_OF_CHANNELS]));
// up bus interface
up_axi i_up_axi (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_axi_awvalid (s_axi_awvalid),
.up_axi_awaddr (s_axi_awaddr),
.up_axi_awready (s_axi_awready),
.up_axi_wvalid (s_axi_wvalid),
.up_axi_wdata (s_axi_wdata),
.up_axi_wstrb (s_axi_wstrb),
.up_axi_wready (s_axi_wready),
.up_axi_bvalid (s_axi_bvalid),
.up_axi_bresp (s_axi_bresp),
.up_axi_bready (s_axi_bready),
.up_axi_arvalid (s_axi_arvalid),
.up_axi_araddr (s_axi_araddr),
.up_axi_arready (s_axi_arready),
.up_axi_rvalid (s_axi_rvalid),
.up_axi_rresp (s_axi_rresp),
.up_axi_rdata (s_axi_rdata),
.up_axi_rready (s_axi_rready),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata),
.up_rack (up_rack));
generate
genvar i;
for (i = 0; i < NUM_OF_CHANNELS; i=i+1) begin
up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
up_adc_channel #(.CHANNEL_ID(i)) i_up_adc_channel (
.adc_clk (adc_clk),
.adc_rst (adc_rst),
.adc_enable (adc_enable[i]),
.adc_iqcor_enb (),
.adc_dcfilt_enb (),
.adc_dfmt_se (),
.adc_dfmt_type (),
.adc_dfmt_enable (),
.adc_dcfilt_offset (),
.adc_dcfilt_coeff (),
.adc_iqcor_coeff_1 (),
.adc_iqcor_coeff_2 (),
.adc_pnseq_sel (),
.adc_data_sel (),
.adc_pn_err (),
.adc_pn_oos (),
.adc_or (),
.up_adc_pn_err (),
.up_adc_pn_oos (),
.up_adc_or (),
.up_usr_datatype_be (),
.up_usr_datatype_signed (),
.up_usr_datatype_shift (),
.up_usr_datatype_total_bits (),
.up_usr_datatype_bits (),
.up_usr_decimation_m (),
.up_usr_decimation_n (),
.adc_usr_datatype_be (1'b0),
.adc_usr_datatype_signed (1'b1),
.adc_usr_datatype_shift (8'd0),
.adc_usr_datatype_total_bits (8'd32),
.adc_usr_datatype_bits (8'd32),
.adc_usr_decimation_m (16'd1),
.adc_usr_decimation_n (16'd1),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
.up_waddr (up_waddr_s),
.up_wdata (up_wdata_s),
.up_wack (up_wack_s[i]),
.up_rreq (up_rreq_s),
.up_raddr (up_raddr_s),
.up_rdata (up_rdata_s[i]),
.up_rack (up_rack_s[i]));
end
endgenerate

230
library/cn0363/cn0363_dma_sequencer/cn0363_dma_sequencer.v
View File

@ -1,38 +1,38 @@
module cn0363_dma_sequencer (
input clk,
input resetn,
input clk,
input resetn,
input [31:0] phase,
input phase_valid,
output reg phase_ready,
input [31:0] phase,
input phase_valid,
output reg phase_ready,
input [23:0] data,
input data_valid,
output reg data_ready,
input [23:0] data,
input data_valid,
output reg data_ready,
input [31:0] data_filtered,
input data_filtered_valid,
output reg data_filtered_ready,
input [31:0] data_filtered,
input data_filtered_valid,
output reg data_filtered_ready,
input [31:0] i_q,
input i_q_valid,
output reg i_q_ready,
input [31:0] i_q,
input i_q_valid,
output reg i_q_ready,
input [31:0] i_q_filtered,
input i_q_filtered_valid,
output reg i_q_filtered_ready,
input [31:0] i_q_filtered,
input i_q_filtered_valid,
output reg i_q_filtered_ready,
output overflow,
output overflow,
output reg [31:0] dma_wr_data,
output reg dma_wr_en,
output reg dma_wr_sync,
input dma_wr_overflow,
input dma_wr_xfer_req,
output reg [31:0] dma_wr_data,
output reg dma_wr_en,
output reg dma_wr_sync,
input dma_wr_overflow,
input dma_wr_xfer_req,
input [13:0] channel_enable,
input [13:0] channel_enable,
output processing_resetn
output processing_resetn
);
reg [3:0] count = 'h00;
@ -41,120 +41,120 @@ assign overflow = dma_wr_overflow;
assign processing_resetn = dma_wr_xfer_req;
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
count <= 'h0;
end else begin
case (count)
'h0: if (phase_valid) count <= count + 1;
'h1: if (data_valid) count <= count + 1;
'h2: if (data_filtered_valid) count <= count + 1;
'h3: if (i_q_valid) count <= count + 1;
'h4: if (i_q_valid) count <= count + 1;
'h5: if (i_q_filtered_valid) count <= count + 1;
'h6: if (i_q_filtered_valid) count <= count + 1;
'h7: if (phase_valid) count <= count + 1;
'h8: if (data_valid) count <= count + 1;
'h9: if (data_filtered_valid) count <= count + 1;
'ha: if (i_q_valid) count <= count + 1;
'hb: if (i_q_valid) count <= count + 1;
'hc: if (i_q_filtered_valid) count <= count + 1;
'hd: if (i_q_filtered_valid) count <= 'h00;
endcase
end
if (processing_resetn == 1'b0) begin
count <= 'h0;
end else begin
case (count)
'h0: if (phase_valid) count <= count + 1;
'h1: if (data_valid) count <= count + 1;
'h2: if (data_filtered_valid) count <= count + 1;
'h3: if (i_q_valid) count <= count + 1;
'h4: if (i_q_valid) count <= count + 1;
'h5: if (i_q_filtered_valid) count <= count + 1;
'h6: if (i_q_filtered_valid) count <= count + 1;
'h7: if (phase_valid) count <= count + 1;
'h8: if (data_valid) count <= count + 1;
'h9: if (data_filtered_valid) count <= count + 1;
'ha: if (i_q_valid) count <= count + 1;
'hb: if (i_q_valid) count <= count + 1;
'hc: if (i_q_filtered_valid) count <= count + 1;
'hd: if (i_q_filtered_valid) count <= 'h00;
endcase
end
end
always @(posedge clk) begin
case (count)
'h0: dma_wr_data <= phase;
'h1: dma_wr_data <= {8'h00,data[23:0]};
'h2: dma_wr_data <= data_filtered;
'h3: dma_wr_data <= i_q;
'h4: dma_wr_data <= i_q;
'h5: dma_wr_data <= i_q_filtered;
'h6: dma_wr_data <= i_q_filtered;
'h7: dma_wr_data <= phase;
'h8: dma_wr_data <= {8'h00,data[23:0]};
'h9: dma_wr_data <= data_filtered;
'ha: dma_wr_data <= i_q;
'hb: dma_wr_data <= i_q;
'hc: dma_wr_data <= i_q_filtered;
'hd: dma_wr_data <= i_q_filtered;
endcase
case (count)
'h0: dma_wr_data <= phase;
'h1: dma_wr_data <= {8'h00,data[23:0]};
'h2: dma_wr_data <= data_filtered;
'h3: dma_wr_data <= i_q;
'h4: dma_wr_data <= i_q;
'h5: dma_wr_data <= i_q_filtered;
'h6: dma_wr_data <= i_q_filtered;
'h7: dma_wr_data <= phase;
'h8: dma_wr_data <= {8'h00,data[23:0]};
'h9: dma_wr_data <= data_filtered;
'ha: dma_wr_data <= i_q;
'hb: dma_wr_data <= i_q;
'hc: dma_wr_data <= i_q_filtered;
'hd: dma_wr_data <= i_q_filtered;
endcase
end
always @(posedge clk) begin
if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
dma_wr_en <= 1'b0;
end else begin
case (count)
'h0: dma_wr_en <= phase_valid;
'h1: dma_wr_en <= data_valid;
'h2: dma_wr_en <= data_filtered_valid;
'h3: dma_wr_en <= i_q_valid;
'h4: dma_wr_en <= i_q_valid;
'h5: dma_wr_en <= i_q_filtered_valid;
'h6: dma_wr_en <= i_q_filtered_valid;
'h7: dma_wr_en <= phase_valid;
'h8: dma_wr_en <= data_valid;
'h9: dma_wr_en <= data_filtered_valid;
'ha: dma_wr_en <= i_q_valid;
'hb: dma_wr_en <= i_q_valid;
'hc: dma_wr_en <= i_q_filtered_valid;
'hd: dma_wr_en <= i_q_filtered_valid;
endcase
end
if (processing_resetn == 1'b0 || channel_enable[count] == 1'b0) begin
dma_wr_en <= 1'b0;
end else begin
case (count)
'h0: dma_wr_en <= phase_valid;
'h1: dma_wr_en <= data_valid;
'h2: dma_wr_en <= data_filtered_valid;
'h3: dma_wr_en <= i_q_valid;
'h4: dma_wr_en <= i_q_valid;
'h5: dma_wr_en <= i_q_filtered_valid;
'h6: dma_wr_en <= i_q_filtered_valid;
'h7: dma_wr_en <= phase_valid;
'h8: dma_wr_en <= data_valid;
'h9: dma_wr_en <= data_filtered_valid;
'ha: dma_wr_en <= i_q_valid;
'hb: dma_wr_en <= i_q_valid;
'hc: dma_wr_en <= i_q_filtered_valid;
'hd: dma_wr_en <= i_q_filtered_valid;
endcase
end
end
always @(posedge clk) begin
if (count == 'h00) begin
dma_wr_sync <= 1'b1;
end else if (dma_wr_en == 1'b1) begin
dma_wr_sync = 1'b0;
end
if (count == 'h00) begin
dma_wr_sync <= 1'b1;
end else if (dma_wr_en == 1'b1) begin
dma_wr_sync = 1'b0;
end
end
always @(*) begin
case (count)
'h0: phase_ready <= 1'b1;
'h7: phase_ready <= 1'b1;
default: phase_ready <= 1'b0;
endcase
case (count)
'h0: phase_ready <= 1'b1;
'h7: phase_ready <= 1'b1;
default: phase_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h1: data_ready <= 1'b1;
'h8: data_ready <= 1'b1;
default: data_ready <= 1'b0;
endcase
case (count)
'h1: data_ready <= 1'b1;
'h8: data_ready <= 1'b1;
default: data_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h2: data_filtered_ready <= 1'b1;
'h9: data_filtered_ready <= 1'b1;
default: data_filtered_ready <= 1'b0;
endcase
case (count)
'h2: data_filtered_ready <= 1'b1;
'h9: data_filtered_ready <= 1'b1;
default: data_filtered_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h3: i_q_ready <= 1'b1;
'h4: i_q_ready <= 1'b1;
'ha: i_q_ready <= 1'b1;
'hb: i_q_ready <= 1'b1;
default: i_q_ready <= 1'b0;
endcase
case (count)
'h3: i_q_ready <= 1'b1;
'h4: i_q_ready <= 1'b1;
'ha: i_q_ready <= 1'b1;
'hb: i_q_ready <= 1'b1;
default: i_q_ready <= 1'b0;
endcase
end
always @(*) begin
case (count)
'h5: i_q_filtered_ready <= 1'b1;
'h6: i_q_filtered_ready <= 1'b1;
'hc: i_q_filtered_ready <= 1'b1;
'hd: i_q_filtered_ready <= 1'b1;
default: i_q_filtered_ready <= 1'b0;
endcase
case (count)
'h5: i_q_filtered_ready <= 1'b1;
'h6: i_q_filtered_ready <= 1'b1;
'hc: i_q_filtered_ready <= 1'b1;
'hd: i_q_filtered_ready <= 1'b1;
default: i_q_filtered_ready <= 1'b0;
endcase
end
endmodule

146
library/cn0363/cn0363_phase_data_sync/cn0363_phase_data_sync.v
View File

@ -1,29 +1,29 @@
module cn0363_phase_data_sync (
input clk,
input resetn,
input clk,
input resetn,
input processing_resetn,
input processing_resetn,
output s_axis_sample_ready,
input s_axis_sample_valid,
input [7:0] s_axis_sample_data,
output s_axis_sample_ready,
input s_axis_sample_valid,
input [7:0] s_axis_sample_data,
input sample_has_stat,
input sample_has_stat,
input conv_done,
input [31:0] phase,
input conv_done,
input [31:0] phase,
output reg m_axis_sample_valid,
input m_axis_sample_ready,
output [23:0] m_axis_sample_data,
output reg m_axis_sample_valid,
input m_axis_sample_ready,
output [23:0] m_axis_sample_data,
output reg m_axis_phase_valid,
input m_axis_phase_ready,
output [31:0] m_axis_phase_data,
output reg m_axis_phase_valid,
input m_axis_phase_ready,
output [31:0] m_axis_phase_data,
output reg overflow
output reg overflow
);
reg [1:0] data_counter = 'h00;
@ -46,38 +46,38 @@ assign m_axis_sample_data = {~sample_hold[23],sample_hold[22:0]};
assign m_axis_phase_data = phase_hold;
always @(posedge clk) begin
if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
// Is the processing pipeline ready to accept data?
if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
overflow <= 1'b1;
end else begin
phase_hold <= phase;
overflow <= 1'b0;
end
end else begin
overflow <= 1'b0;
end
conv_done_d1 <= conv_done;
if (conv_done_d1 == 1'b0 && conv_done == 1'b1) begin
// Is the processing pipeline ready to accept data?
if (m_axis_sample_valid | m_axis_phase_valid | ~processing_resetn) begin
overflow <= 1'b1;
end else begin
phase_hold <= phase;
overflow <= 1'b0;
end
end else begin
overflow <= 1'b0;
end
conv_done_d1 <= conv_done;
end
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
m_axis_phase_valid <= 1'b0;
m_axis_sample_valid <= 1'b0;
end else begin
/* Data and phase become valid once we have both */
if (sample_hold_valid == 1'b1) begin
m_axis_phase_valid <= 1'b1;
m_axis_sample_valid <= 1'b1;
end else begin
if (m_axis_phase_ready == 1'b1) begin
m_axis_phase_valid <= 1'b0;
end
if (m_axis_sample_ready == 1'b1) begin
m_axis_sample_valid <= 1'b0;
end
end
end
if (processing_resetn == 1'b0) begin
m_axis_phase_valid <= 1'b0;
m_axis_sample_valid <= 1'b0;
end else begin
/* Data and phase become valid once we have both */
if (sample_hold_valid == 1'b1) begin
m_axis_phase_valid <= 1'b1;
m_axis_sample_valid <= 1'b1;
end else begin
if (m_axis_phase_ready == 1'b1) begin
m_axis_phase_valid <= 1'b0;
end
if (m_axis_sample_ready == 1'b1) begin
m_axis_sample_valid <= 1'b0;
end
end
end
end
/* If the STAT register is included in the sample we get 4 bytes per sample and
@ -87,45 +87,45 @@ end
* channel */
always @(posedge clk) begin
sample_hold_valid <= 1'b0;
if (sample_has_stat == 1'b0) begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
sample_hold_valid <= 1'b1;
end
end else begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
(sync == 1'b1 || synced == 1'b1)) begin
sample_hold_valid <= 1'b1;
end
end
sample_hold_valid <= 1'b0;
if (sample_has_stat == 1'b0) begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h2) begin
sample_hold_valid <= 1'b1;
end
end else begin
if (s_axis_sample_valid == 1'b1 && data_counter == 2'h3 &&
(sync == 1'b1 || synced == 1'b1)) begin
sample_hold_valid <= 1'b1;
end
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
sample_hold <= {sample_hold[15:0],s_axis_sample_data};
end
if (s_axis_sample_valid == 1'b1 && data_counter != 2'h3) begin
sample_hold <= {sample_hold[15:0],s_axis_sample_data};
end
end
always @(posedge clk) begin
if (s_axis_sample_valid == 1'b1) begin
if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
data_counter <= 2'h0;
end else begin
data_counter <= data_counter + 1'b1;
end
end
if (s_axis_sample_valid == 1'b1) begin
if (data_counter == 2'h2 && sample_has_stat == 1'b0) begin
data_counter <= 2'h0;
end else begin
data_counter <= data_counter + 1'b1;
end
end
end
assign sync = s_axis_sample_data[3:0] == 'h00 && data_counter == 'h3;
always @(posedge clk) begin
if (processing_resetn == 1'b0) begin
synced <= ~sample_has_stat;
end else begin
if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
synced <= 1'b1;
end
end
if (processing_resetn == 1'b0) begin
synced <= ~sample_has_stat;
end else begin
if (s_axis_sample_valid == 1'b1 && sync == 1'b1) begin
synced <= 1'b1;
end
end
end
endmodule

22
library/common/sync_bits.v
View File

@ -45,10 +45,10 @@
*/
module sync_bits
(
input [NUM_OF_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out
input [NUM_OF_BITS-1:0] in,
input out_resetn,
input out_clk,
output [NUM_OF_BITS-1:0] out
);
// Number of bits to synchronize
@ -62,13 +62,13 @@ reg [NUM_OF_BITS-1:0] cdc_sync_stage2 = 'h0;
always @(posedge out_clk)
begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in;
cdc_sync_stage2 <= cdc_sync_stage1;
end
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'b0;
cdc_sync_stage2 <= 'b0;
end else begin
cdc_sync_stage1 <= in;
cdc_sync_stage2 <= cdc_sync_stage1;
end
end
assign out = ASYNC_CLK ? cdc_sync_stage2 : in;

76
library/common/sync_gray.v
View File

@ -43,12 +43,12 @@
* change by either -1, 0 or +1.
*/
module sync_gray (
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count
input in_clk,
input in_resetn,
input [DATA_WIDTH-1:0] in_count,
input out_resetn,
input out_clk,
output [DATA_WIDTH-1:0] out_count
);
// Bit-width of the counter
@ -63,47 +63,47 @@ reg [DATA_WIDTH-1:0] cdc_sync_stage2 = 'h0;
reg [DATA_WIDTH-1:0] out_count_m = 'h0;
function [DATA_WIDTH-1:0] g2b;
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
input [DATA_WIDTH-1:0] g;
reg [DATA_WIDTH-1:0] b;
integer i;
begin
b[DATA_WIDTH-1] = g[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i - 1)
b[i] = b[i + 1] ^ g[i];
g2b = b;
end
endfunction
function [DATA_WIDTH-1:0] b2g;
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
input [DATA_WIDTH-1:0] b;
reg [DATA_WIDTH-1:0] g;
integer i;
begin
g[DATA_WIDTH-1] = b[DATA_WIDTH-1];
for (i = DATA_WIDTH - 2; i >= 0; i = i -1)
g[i] = b[i + 1] ^ b[i];
b2g = g;
end
endfunction
always @(posedge in_clk) begin
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
if (in_resetn == 1'b0) begin
cdc_sync_stage0 <= 'h00;
end else begin
cdc_sync_stage0 <= b2g(in_count);
end
end
always @(posedge out_clk) begin
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
if (out_resetn == 1'b0) begin
cdc_sync_stage1 <= 'h00;
cdc_sync_stage2 <= 'h00;
out_count_m <= 'h00;
end else begin
cdc_sync_stage1 <= cdc_sync_stage0;
cdc_sync_stage2 <= cdc_sync_stage1;
out_count_m <= g2b(cdc_sync_stage2);
end
end
assign out_count = ASYNC_CLK ? out_count_m : in_count;

2
library/common/up_hdmi_tx.v
View File

@ -249,7 +249,7 @@ module up_hdmi_tx (
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01a)) begin
up_clip_max <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h01b)) begin
up_clip_min <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin

254
library/cordic_demod/cordic_demod.v
View File

@ -1,14 +1,14 @@
module cordic_demod (
input clk,
input resetn,
input clk,
input resetn,
input s_axis_valid,
output s_axis_ready,
input [63:0] s_axis_data,
input s_axis_valid,
output s_axis_ready,
input [63:0] s_axis_data,
output m_axis_valid,
input m_axis_ready,
output [63:0] m_axis_data
output m_axis_valid,
input m_axis_ready,
output [63:0] m_axis_data
);
reg [4:0] step_counter;
@ -34,135 +34,135 @@ localparam STATE_DONE = 4;
reg [31:0] angle[0:30];
initial begin
angle[0] = 32'h20000000;
angle[1] = 32'h12e4051e;
angle[2] = 32'h09fb385b;
angle[3] = 32'h051111d4;
angle[4] = 32'h028b0d43;
angle[5] = 32'h0145d7e1;
angle[6] = 32'h00a2f61e;
angle[7] = 32'h00517c55;
angle[8] = 32'h0028be53;
angle[9] = 32'h00145f2f;
angle[10] = 32'h000a2f98;
angle[11] = 32'h000517cc;
angle[12] = 32'h00028be6;
angle[13] = 32'h000145f3;
angle[14] = 32'h0000a2fa;
angle[15] = 32'h0000517d;
angle[16] = 32'h000028be;
angle[17] = 32'h0000145f;
angle[18] = 32'h00000a30;
angle[19] = 32'h00000518;
angle[20] = 32'h0000028c;
angle[21] = 32'h00000146;
angle[22] = 32'h000000a3;
angle[23] = 32'h00000051;
angle[24] = 32'h00000029;
angle[25] = 32'h00000014;
angle[26] = 32'h0000000a;
angle[27] = 32'h00000005;
angle[28] = 32'h00000003;
angle[29] = 32'h00000001;
angle[30] = 32'h00000001;
angle[0] = 32'h20000000;
angle[1] = 32'h12e4051e;
angle[2] = 32'h09fb385b;
angle[3] = 32'h051111d4;
angle[4] = 32'h028b0d43;
angle[5] = 32'h0145d7e1;
angle[6] = 32'h00a2f61e;
angle[7] = 32'h00517c55;
angle[8] = 32'h0028be53;
angle[9] = 32'h00145f2f;
angle[10] = 32'h000a2f98;
angle[11] = 32'h000517cc;
angle[12] = 32'h00028be6;
angle[13] = 32'h000145f3;
angle[14] = 32'h0000a2fa;
angle[15] = 32'h0000517d;
angle[16] = 32'h000028be;
angle[17] = 32'h0000145f;
angle[18] = 32'h00000a30;
angle[19] = 32'h00000518;
angle[20] = 32'h0000028c;
angle[21] = 32'h00000146;
angle[22] = 32'h000000a3;
angle[23] = 32'h00000051;
angle[24] = 32'h00000029;
angle[25] = 32'h00000014;
angle[26] = 32'h0000000a;
angle[27] = 32'h00000005;
angle[28] = 32'h00000003;
angle[29] = 32'h00000001;
angle[30] = 32'h00000001;
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
state <= STATE_IDLE;
end else begin
case (state)
STATE_IDLE: begin
if (s_axis_valid == 1'b1) begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_SHIFT_LOAD: begin
if (step_counter == 'h00) begin
state <= STATE_ADD;
end else begin
state <= STATE_SHIFT;
end
end
STATE_SHIFT: begin
if (shift_counter == 'h01) begin
state <= STATE_ADD;
end
end
STATE_ADD: begin
if (step_counter == 'd30) begin
state <= STATE_DONE;
end else begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_DONE: begin
if (m_axis_ready == 1'b1)
state <= STATE_IDLE;
end
endcase
end
if (resetn == 1'b0) begin
state <= STATE_IDLE;
end else begin
case (state)
STATE_IDLE: begin
if (s_axis_valid == 1'b1) begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_SHIFT_LOAD: begin
if (step_counter == 'h00) begin
state <= STATE_ADD;
end else begin
state <= STATE_SHIFT;
end
end
STATE_SHIFT: begin
if (shift_counter == 'h01) begin
state <= STATE_ADD;
end
end
STATE_ADD: begin
if (step_counter == 'd30) begin
state <= STATE_DONE;
end else begin
state <= STATE_SHIFT_LOAD;
end
end
STATE_DONE: begin
if (m_axis_ready == 1'b1)
state <= STATE_IDLE;
end
endcase
end
end
always @(posedge clk) begin
case(state)
STATE_SHIFT_LOAD: begin
shift_counter <= step_counter;
end
STATE_SHIFT: begin
shift_counter <= shift_counter - 1'b1;
end
endcase
case(state)
STATE_SHIFT_LOAD: begin
shift_counter <= step_counter;
end
STATE_SHIFT: begin
shift_counter <= shift_counter - 1'b1;
end
endcase
end
always @(posedge clk)
begin
case(state)
STATE_IDLE:
if (s_axis_valid == 1'b1) begin
step_counter <= 'h00;
phase <= {1'b0,s_axis_data[61:32]};
step_counter <= 'h00;
case (s_axis_data[63:62])
2'b00: begin
i <= {s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b01: begin
i <= 'h00;
q <= ~{s_axis_data[31],s_axis_data[31:0]};
end
2'b10: begin
i <= ~{s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b11: begin
i <= 'h00;
q <= {s_axis_data[31],s_axis_data[31:0]};
end
endcase
end
STATE_SHIFT_LOAD: begin
i_shift <= i;
q_shift <= q;
end
STATE_SHIFT: begin
i_shift <= {i_shift[32],i_shift[32:1]};
q_shift <= {q_shift[32],q_shift[32:1]};
end
STATE_ADD: begin
if (phase[30] == 1'b0) begin
i <= i + q_shift;
q <= q - i_shift;
phase <= phase - angle[step_counter];
end else begin
i <= i - q_shift;
q <= q + i_shift;
phase <= phase + angle[step_counter];
end
step_counter <= step_counter + 1'b1;
end
endcase
case(state)
STATE_IDLE:
if (s_axis_valid == 1'b1) begin
step_counter <= 'h00;
phase <= {1'b0,s_axis_data[61:32]};
step_counter <= 'h00;
case (s_axis_data[63:62])
2'b00: begin
i <= {s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b01: begin
i <= 'h00;
q <= ~{s_axis_data[31],s_axis_data[31:0]};
end
2'b10: begin
i <= ~{s_axis_data[31],s_axis_data[31:0]};
q <= 'h00;
end
2'b11: begin
i <= 'h00;
q <= {s_axis_data[31],s_axis_data[31:0]};
end
endcase
end
STATE_SHIFT_LOAD: begin
i_shift <= i;
q_shift <= q;
end
STATE_SHIFT: begin
i_shift <= {i_shift[32],i_shift[32:1]};
q_shift <= {q_shift[32],q_shift[32:1]};
end
STATE_ADD: begin
if (phase[30] == 1'b0) begin
i <= i + q_shift;
q <= q - i_shift;
phase <= phase - angle[step_counter];
end else begin
i <= i - q_shift;
q <= q + i_shift;
phase <= phase + angle[step_counter];
end
step_counter <= step_counter + 1'b1;
end
endcase
end
endmodule

106
library/spi_engine/spi_engine_interconnect/spi_engine_interconnect.v
View File

@ -1,58 +1,58 @@
module spi_engine_interconnect (
input clk,
input resetn,
input clk,
input resetn,
output m_cmd_valid,
input m_cmd_ready,
output [15:0] m_cmd_data,
output m_cmd_valid,
input m_cmd_ready,
output [15:0] m_cmd_data,
output m_sdo_valid,
input m_sdo_ready,
output [(DATA_WIDTH-1):0] m_sdo_data,
output m_sdo_valid,
input m_sdo_ready,
output [(DATA_WIDTH-1):0] m_sdo_data,
input m_sdi_valid,
output m_sdi_ready,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
input m_sdi_valid,
output m_sdi_ready,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] m_sdi_data,
input m_sync_valid,
output m_sync_ready,
input [7:0] m_sync,
input m_sync_valid,
output m_sync_ready,
input [7:0] m_sync,
input s0_cmd_valid,
output s0_cmd_ready,
input [15:0] s0_cmd_data,
input s0_cmd_valid,
output s0_cmd_ready,
input [15:0] s0_cmd_data,
input s0_sdo_valid,
output s0_sdo_ready,
input [(DATA_WIDTH-1):0] s0_sdo_data,
input s0_sdo_valid,
output s0_sdo_ready,
input [(DATA_WIDTH-1):0] s0_sdo_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
output s0_sdi_valid,
input s0_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s0_sdi_data,
output s0_sync_valid,
input s0_sync_ready,
output [7:0] s0_sync,
output s0_sync_valid,
input s0_sync_ready,
output [7:0] s0_sync,
input s1_cmd_valid,
output s1_cmd_ready,
input [15:0] s1_cmd_data,
input s1_cmd_valid,
output s1_cmd_ready,
input [15:0] s1_cmd_data,
input s1_sdo_valid,
output s1_sdo_ready,
input [(DATA_WIDTH-1):0] s1_sdo_data,
input s1_sdo_valid,
output s1_sdo_ready,
input [(DATA_WIDTH-1):0] s1_sdo_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
output s1_sdi_valid,
input s1_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] s1_sdi_data,
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
output s1_sync_valid,
input s1_sync_ready,
output [7:0] s1_sync
);
parameter DATA_WIDTH = 8; // Valid data widths values are 8/16/24/32
@ -87,24 +87,24 @@ assign s0_sync_valid = `spi_engine_interconnect_mux(m_sync_valid, 1'b0);
assign s1_sync_valid = `spi_engine_interconnect_mux(1'b0, m_sync_valid);
always @(posedge clk) begin
if (idle == 1'b1) begin
if (s0_cmd_valid)
s_active <= 1'b0;
else if (s1_cmd_valid)
s_active <= 1'b1;
end
if (idle == 1'b1) begin
if (s0_cmd_valid)
s_active <= 1'b0;
else if (s1_cmd_valid)
s_active <= 1'b1;
end
end
always @(posedge clk) begin
if (resetn == 1'b0) begin
idle = 1'b1;
end else begin
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
idle <= 1'b1;
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
idle <= 1'b0;
end
end
if (resetn == 1'b0) begin
idle = 1'b1;
end else begin
if (m_sync_valid == 1'b1 && m_sync_ready == 1'b1) begin
idle <= 1'b1;
end else if (s0_cmd_valid == 1'b1 || s1_cmd_valid == 1'b1) begin
idle <= 1'b0;
end
end
end
endmodule

128
library/spi_engine/spi_engine_offload/spi_engine_offload.v
View File

@ -1,41 +1,41 @@
module spi_engine_offload (
input ctrl_clk,
input ctrl_clk,
input ctrl_cmd_wr_en,
input [15:0] ctrl_cmd_wr_data,
input ctrl_cmd_wr_en,
input [15:0] ctrl_cmd_wr_data,
input ctrl_sdo_wr_en,
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
input ctrl_sdo_wr_en,
input [(DATA_WIDTH-1):0] ctrl_sdo_wr_data,
input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset,
input ctrl_enable,
output ctrl_enabled,
input ctrl_mem_reset,
input spi_clk,
input spi_resetn,
input spi_clk,
input spi_resetn,
input trigger,
input trigger,
output cmd_valid,
input cmd_ready,
output [15:0] cmd,
output cmd_valid,
input cmd_ready,
output [15:0] cmd,
output sdo_data_valid,
input sdo_data_ready,
output [(DATA_WIDTH-1):0] sdo_data,
output sdo_data_valid,
input sdo_data_ready,
output [(DATA_WIDTH-1):0] sdo_data,
input sdi_data_valid,
output sdi_data_ready,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
input sdi_data_valid,
output sdi_data_ready,
input [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_data,
input sync_valid,
output sync_ready,
input [7:0] sync_data,
input sync_valid,
output sync_ready,
input [7:0] sync_data,
output offload_sdi_valid,
input offload_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
output offload_sdi_valid,
input offload_sdi_ready,
output [(NUM_OF_SDI * DATA_WIDTH-1):0] offload_sdi_data
);
parameter ASYNC_SPI_CLK = 0;
@ -84,17 +84,17 @@ wire ctrl_is_enabled;
reg spi_enabled = 1'b0;
always @(posedge ctrl_clk) begin
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
ctrl_do_enable <= 1'b0;
end
if (ctrl_enable == 1'b1) begin
ctrl_do_enable <= 1'b1;
end else if (ctrl_is_enabled == 1'b1) begin
ctrl_do_enable <= 1'b0;
end
end
assign ctrl_enabled = ctrl_is_enabled | ctrl_do_enable;
always @(posedge spi_clk) begin
spi_enabled <= spi_enable | spi_active;
spi_enabled <= spi_enable | spi_active;
end
sync_bits # (
@ -125,56 +125,56 @@ end endgenerate
assign spi_cmd_rd_addr_next = spi_cmd_rd_addr + 1;
always @(posedge spi_clk) begin
if (spi_resetn == 1'b0) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (trigger == 1'b1 && spi_enable == 1'b1)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0;
end
end
if (spi_resetn == 1'b0) begin
spi_active <= 1'b0;
end else begin
if (spi_active == 1'b0) begin
if (trigger == 1'b1 && spi_enable == 1'b1)
spi_active <= 1'b1;
end else if (cmd_ready == 1'b1 && spi_cmd_rd_addr_next == ctrl_cmd_wr_addr) begin
spi_active <= 1'b0;
end
end
end
always @(posedge spi_clk) begin
if (cmd_valid == 1'b0) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
if (cmd_valid == 1'b0) begin
spi_cmd_rd_addr <= 'h00;
end else if (cmd_ready == 1'b1) begin
spi_cmd_rd_addr <= spi_cmd_rd_addr_next;
end
end
always @(posedge spi_clk) begin
if (spi_active == 1'b0) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
if (spi_active == 1'b0) begin
spi_sdo_rd_addr <= 'h00;
end else if (sdo_data_ready == 1'b1) begin
spi_sdo_rd_addr <= spi_sdo_rd_addr + 1'b1;
end
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
if (ctrl_mem_reset == 1'b1)
ctrl_cmd_wr_addr <= 'h00;
else if (ctrl_cmd_wr_en == 1'b1)
ctrl_cmd_wr_addr <= ctrl_cmd_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_cmd_wr_en == 1'b1)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
if (ctrl_cmd_wr_en == 1'b1)
cmd_mem[ctrl_cmd_wr_addr] <= ctrl_cmd_wr_data;
end
always @(posedge ctrl_clk) begin
if (ctrl_mem_reset == 1'b1)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
if (ctrl_mem_reset == 1'b1)
ctrl_sdo_wr_addr <= 'h00;
else if (ctrl_sdo_wr_en == 1'b1)
ctrl_sdo_wr_addr <= ctrl_sdo_wr_addr + 1'b1;
end
always @(posedge ctrl_clk) begin
if (ctrl_sdo_wr_en == 1'b1)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
if (ctrl_sdo_wr_en == 1'b1)
sdo_mem[ctrl_sdo_wr_addr] <= ctrl_sdo_wr_data;
end
endmodule

116
library/util_axis_fifo/address_gray.v
View File

@ -37,19 +37,19 @@
// ***************************************************************************
module fifo_address_gray (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
parameter ADDRESS_WIDTH = 4;
@ -72,84 +72,84 @@ assign s_axis_waddr = _s_axis_waddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[ADDRESS_WIDTH:1];
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
s_axis_waddr_gray <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
s_axis_waddr_gray <= s_axis_waddr_gray_next;
end
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
s_axis_waddr_gray <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
s_axis_waddr_gray <= s_axis_waddr_gray_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[ADDRESS_WIDTH:1];
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
m_axis_raddr_gray <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
m_axis_raddr_gray <= m_axis_raddr_gray_next;
end
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
m_axis_raddr_gray <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
m_axis_raddr_gray <= m_axis_raddr_gray_next;
end
end
sync_bits #(
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr_gray),
.out(m_axis_waddr_gray)
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr_gray),
.out(m_axis_waddr_gray)
);
sync_bits #(
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
.NUM_OF_BITS(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr_gray),
.out(s_axis_raddr_gray)
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr_gray),
.out(s_axis_raddr_gray)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
end
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (s_axis_raddr_gray[ADDRESS_WIDTH] == s_axis_waddr_gray_next[ADDRESS_WIDTH] ||
s_axis_raddr_gray[ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[ADDRESS_WIDTH-1] ||
s_axis_raddr_gray[ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[ADDRESS_WIDTH-2:0]);
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
end
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
end
end
endmodule

124
library/util_axis_fifo/address_gray_pipelined.v
View File

@ -37,20 +37,20 @@
// ***************************************************************************
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [ADDRESS_WIDTH-1:0] s_axis_waddr,
output reg [ADDRESS_WIDTH:0] s_axis_room
);
parameter ADDRESS_WIDTH = 4;
@ -68,83 +68,83 @@ assign m_axis_raddr = _m_axis_raddr[ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(ADDRESS_WIDTH + 1)
.DATA_WIDTH(ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= 2**ADDRESS_WIDTH;
end else begin
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
end
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
s_axis_room <= 2**ADDRESS_WIDTH;
end else begin
s_axis_ready <= (_s_axis_raddr[ADDRESS_WIDTH] == _s_axis_waddr_next[ADDRESS_WIDTH] ||
_s_axis_raddr[ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
s_axis_room <= _s_axis_raddr - _s_axis_waddr_next + 2**ADDRESS_WIDTH;
end
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
if (m_axis_aresetn == 1'b0) begin
m_axis_valid <= 1'b0;
m_axis_level <= 'h00;
end else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
m_axis_level <= _m_axis_waddr - _m_axis_raddr_next;
end
end
endmodule

78
library/util_axis_fifo/address_sync.v
View File

@ -37,19 +37,19 @@
// ***************************************************************************
module fifo_address_sync (
input clk,
input resetn,
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
input m_axis_ready,
output reg m_axis_valid,
output reg [ADDRESS_WIDTH-1:0] m_axis_raddr,
output [ADDRESS_WIDTH:0] m_axis_level,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [ADDRESS_WIDTH-1:0] s_axis_waddr,
output [ADDRESS_WIDTH:0] s_axis_room
);
parameter ADDRESS_WIDTH = 4;
@ -66,42 +66,42 @@ wire write = s_axis_ready & s_axis_valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
if (read)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= 2**ADDRESS_WIDTH;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= 2**ADDRESS_WIDTH - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
s_axis_empty <= level_next == 0;
end
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
level <= 'h00;
room <= 2**ADDRESS_WIDTH;
s_axis_empty <= 'h00;
end else begin
level <= level_next;
room <= 2**ADDRESS_WIDTH - level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != 2**ADDRESS_WIDTH;
s_axis_empty <= level_next == 0;
end
end
endmodule

156
library/util_axis_fifo/util_axis_fifo.v
View File

@ -37,20 +37,20 @@
// ***************************************************************************
module util_axis_fifo (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [DATA_WIDTH-1:0] m_axis_data,
output [ADDRESS_WIDTH:0] m_axis_level,
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [DATA_WIDTH-1:0] m_axis_data,
output [ADDRESS_WIDTH:0] m_axis_level,
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty,
output [ADDRESS_WIDTH:0] s_axis_room
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty,
output [ADDRESS_WIDTH:0] s_axis_room
);
parameter DATA_WIDTH = 64;
@ -68,23 +68,23 @@ wire m_axis_waddr;
wire s_axis_raddr;
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr),
.out(m_axis_waddr)
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr),
.out(m_axis_waddr)
);
sync_bits #(
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
.NUM_OF_BITS(1),
.ASYNC_CLK(ASYNC_CLK)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr),
.out(s_axis_raddr)
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr),
.out(s_axis_raddr)
);
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
@ -94,27 +94,27 @@ assign s_axis_empty = s_axis_ready;
assign s_axis_room = s_axis_ready;
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
cdc_sync_fifo_ram <= s_axis_data;
if (s_axis_ready)
cdc_sync_fifo_ram <= s_axis_data;
end
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
end
end
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
end
end
end
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
assign m_axis_data = cdc_sync_fifo_ram;
@ -131,48 +131,48 @@ wire _m_axis_valid;
if (ASYNC_CLK == 1) begin
fifo_address_gray_pipelined #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_gray (
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
end else begin
fifo_address_sync #(
.ADDRESS_WIDTH(ADDRESS_WIDTH)
.ADDRESS_WIDTH(ADDRESS_WIDTH)
) i_address_sync (
.clk(m_axis_aclk),
.resetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.clk(m_axis_aclk),
.resetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.m_axis_level(m_axis_level),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr),
.s_axis_room(s_axis_room)
);
end
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
ram[s_axis_waddr] <= s_axis_data;
if (s_axis_ready)
ram[s_axis_waddr] <= s_axis_data;
end
if (S_AXIS_REGISTERED == 1) begin
@ -181,19 +181,19 @@ reg [DATA_WIDTH-1:0] data;
reg valid;
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
valid <= 1'b0;
end else begin
if (_m_axis_valid)
valid <= 1'b1;
else if (m_axis_ready)
valid <= 1'b0;
end
if (m_axis_aresetn == 1'b0) begin
valid <= 1'b0;
end else begin
if (_m_axis_valid)
valid <= 1'b1;
else if (m_axis_ready)
valid <= 1'b0;
end
end
always @(posedge m_axis_aclk) begin
if (~valid || m_axis_ready)
data <= ram[m_axis_raddr];
if (~valid || m_axis_ready)
data <= ram[m_axis_raddr];
end
assign _m_axis_ready = ~valid || m_axis_ready;

110
library/util_axis_resize/util_axis_resize.v
View File

@ -37,16 +37,16 @@
// ***************************************************************************
module util_axis_resize (
input clk,
input resetn,
input clk,
input resetn,
input s_valid,
output s_ready,
input [SLAVE_DATA_WIDTH-1:0] s_data,
input s_valid,
output s_ready,
input [SLAVE_DATA_WIDTH-1:0] s_data,
output m_valid,
input m_ready,
output [MASTER_DATA_WIDTH-1:0] m_data
output m_valid,
input m_ready,
output [MASTER_DATA_WIDTH-1:0] m_data
);
parameter MASTER_DATA_WIDTH = 64;
@ -69,32 +69,32 @@ reg valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
valid <= 1'b1;
else if (m_ready == 1'b1)
valid <= 1'b0;
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (count == 'h00 && s_ready == 1'b1 && s_valid == 1'b1)
valid <= 1'b1;
else if (m_ready == 1'b1)
valid <= 1'b0;
if (s_ready == 1'b1 && s_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
if (s_ready == 1'b1 && s_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
end
always @(posedge clk)
begin
if (s_ready == 1'b1 && s_valid == 1'b1)
if (BIG_ENDIAN == 1) begin
data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
end else begin
data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
end
if (s_ready == 1'b1 && s_valid == 1'b1)
if (BIG_ENDIAN == 1) begin
data <= {data[MASTER_DATA_WIDTH-SLAVE_DATA_WIDTH-1:0], s_data};
end else begin
data <= {s_data, data[MASTER_DATA_WIDTH-1:SLAVE_DATA_WIDTH]};
end
end
assign s_ready = ~valid || m_ready;
@ -111,42 +111,42 @@ reg valid;
always @(posedge clk)
begin
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (s_valid == 1'b1 && s_ready == 1'b1)
valid <= 1'b1;
else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
valid <= 1'b0;
if (resetn == 1'b0) begin
count <= RATIO - 1;
valid <= 1'b0;
end else begin
if (s_valid == 1'b1 && s_ready == 1'b1)
valid <= 1'b1;
else if (count == 'h0 && m_ready == 1'b1 && m_valid == 1'b1)
valid <= 1'b0;
if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (count == 'h00)
count <= RATIO - 1;
else
count <= count - 1'b1;
end
end
end
always @(posedge clk)
begin
if (s_ready == 1'b1 && s_valid == 1'b1) begin
data <= s_data;
end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (BIG_ENDIAN == 1) begin
data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
end else begin
data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
end
end
if (s_ready == 1'b1 && s_valid == 1'b1) begin
data <= s_data;
end else if (m_ready == 1'b1 && m_valid == 1'b1) begin
if (BIG_ENDIAN == 1) begin
data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH] <= data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0];
end else begin
data[SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH-1:0] <= data[SLAVE_DATA_WIDTH-1:MASTER_DATA_WIDTH];
end
end
end
assign s_ready = ~valid || (m_ready && count == 'h0);
assign m_valid = valid;
assign m_data = BIG_ENDIAN == 1 ?
data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
data[MASTER_DATA_WIDTH-1:0];
data[SLAVE_DATA_WIDTH-1:SLAVE_DATA_WIDTH-MASTER_DATA_WIDTH] :
data[MASTER_DATA_WIDTH-1:0];
end
endgenerate

4
library/util_clkdiv/util_clkdiv.v
View File

@ -40,8 +40,8 @@
`timescale 1ns/100ps
module util_clkdiv (
clk,
clk_out
clk,
clk_out
);
input clk;

62
library/util_sigma_delta_spi/util_sigma_delta_spi.v
View File

@ -1,23 +1,23 @@
module util_sigma_delta_spi (
input clk,
input resetn,
input clk,
input resetn,
input spi_active,
input spi_active,
input s_sclk,
input s_sdo,
input s_sdo_t,
output s_sdi,
input [NUM_OF_CS-1:0] s_cs,
input s_sclk,
input s_sdo,
input s_sdo_t,
output s_sdi,
input [NUM_OF_CS-1:0] s_cs,
output m_sclk,
output m_sdo,
output m_sdo_t,
input m_sdi,
output [NUM_OF_CS-1:0] m_cs,
output m_sclk,
output m_sdo,
output m_sdo_t,
input m_sdi,
output [NUM_OF_CS-1:0] m_cs,
output reg data_ready
output reg data_ready
);
parameter NUM_OF_CS = 1;
@ -46,29 +46,29 @@ reg [$clog2(IDLE_TIMEOUT)-1:0] counter = IDLE_TIMEOUT;
reg [2:0] sdi_d = 'h00;
always @(posedge clk) begin
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
if (resetn == 1'b0) begin
counter <= IDLE_TIMEOUT;
end else begin
if (s_cs[CS_PIN] == 1'b0 && spi_active == 1'b0) begin
if (counter != 'h00)
counter <= counter - 1'b1;
end else begin
counter <= IDLE_TIMEOUT;
end
end
end
always @(posedge clk) begin
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
/* The data ready signal is fully asynchronous */
sdi_d <= {sdi_d[1:0], m_sdi};
end
always @(posedge clk) begin
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
if (counter == 'h00 && sdi_d[2] == 1'b0) begin
data_ready <= 1'b1;
end else begin
data_ready <= 1'b0;
end
end
endmodule