zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

fmcomms2: Add a synchronization interface for TDD mode. 

Supported carrier are ZC706 and RFSOM.
The synchronization pulse is automatically generated by the master terminal, when TDD mode is enabled.
By default a terminal is slave, software must write  0x01 into TDD register 0x50.
main
Istvan Csomortani 2015-07-28 14:41:32 +03:00
parent 36f71ea59b
commit 8e631e56d6
8 changed files with 144 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
library/axi_ad9361/axi_ad9361.v
View File

@ -113,6 +113,10 @@ module axi_ad9361 (
enable,
txnrx,
tdd_sync_i,
tdd_sync_o,
tdd_sync_t,
// axi interface
s_axi_aclk,
@ -229,6 +233,10 @@ module axi_ad9361 (
output enable;
output txnrx;
input tdd_sync_i;
output tdd_sync_o;
output tdd_sync_t;
// axi interface
input s_axi_aclk;
@ -403,6 +411,9 @@ module axi_ad9361 (
.tdd_tx_rf_en(tdd_tx_rf_en_s),
.tdd_enable (tdd_enable),
.tdd_status(tdd_status_s),
.tdd_sync_i(tdd_sync_i),
.tdd_sync_o(tdd_sync_o),
.tdd_sync_t(tdd_sync_t),
.tx_valid_i0(dac_valid_i0_s),
.tx_valid_q0(dac_valid_q0_s),
.tx_valid_i1(dac_valid_i1_s),

104
library/axi_ad9361/axi_ad9361_tdd.v
View File

@ -58,6 +58,12 @@ module axi_ad9361_tdd (
tdd_enable,
tdd_status,
// sync signals
tdd_sync_i,
tdd_sync_o,
tdd_sync_t,
// tx/rx data flow control
tx_valid_i0,
@ -109,6 +115,10 @@ module axi_ad9361_tdd (
output tdd_enable;
input [ 7:0] tdd_status;
input tdd_sync_i;
output tdd_sync_o;
output tdd_sync_t;
// tx data flow control
input tx_valid_i0;
@ -148,40 +158,45 @@ module axi_ad9361_tdd (
output [34:0] tdd_dbg;
reg tdd_enable = 1'b0;
reg tdd_slave_synced = 1'b0;
reg tdd_sync_o = 1'b0;
// internal signals
wire rst;
wire tdd_enable_s;
wire tdd_secondary_s;
wire [ 7:0] tdd_burst_count_s;
wire [ 7:0] tdd_burst_count_s;
wire tdd_rx_only_s;
wire tdd_tx_only_s;
wire tdd_gated_rx_dmapath_s;
wire tdd_gated_tx_dmapath_s;
wire [23:0] tdd_counter_init_s;
wire [23:0] tdd_frame_length_s;
wire [23:0] tdd_vco_rx_on_1_s;
wire [23:0] tdd_vco_rx_off_1_s;
wire [23:0] tdd_vco_tx_on_1_s;
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_vco_rx_on_2_s;
wire [23:0] tdd_vco_rx_off_2_s;
wire [23:0] tdd_vco_tx_on_2_s;
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire [23:0] tdd_counter_init_s;
wire [23:0] tdd_frame_length_s;
wire tdd_terminal_type_s;
wire [23:0] tdd_vco_rx_on_1_s;
wire [23:0] tdd_vco_rx_off_1_s;
wire [23:0] tdd_vco_tx_on_1_s;
wire [23:0] tdd_vco_tx_off_1_s;
wire [23:0] tdd_rx_on_1_s;
wire [23:0] tdd_rx_off_1_s;
wire [23:0] tdd_tx_on_1_s;
wire [23:0] tdd_tx_off_1_s;
wire [23:0] tdd_tx_dp_on_1_s;
wire [23:0] tdd_tx_dp_off_1_s;
wire [23:0] tdd_vco_rx_on_2_s;
wire [23:0] tdd_vco_rx_off_2_s;
wire [23:0] tdd_vco_tx_on_2_s;
wire [23:0] tdd_vco_tx_off_2_s;
wire [23:0] tdd_rx_on_2_s;
wire [23:0] tdd_rx_off_2_s;
wire [23:0] tdd_tx_on_2_s;
wire [23:0] tdd_tx_off_2_s;
wire [23:0] tdd_tx_dp_on_2_s;
wire [23:0] tdd_tx_dp_off_2_s;
wire [23:0] tdd_counter_status;
wire [23:0] tdd_counter_status;
wire tdd_tx_dp_en_s;
@ -208,7 +223,45 @@ module axi_ad9361_tdd (
assign tdd_rx_valid_q1 = ((tdd_enable_s & tdd_gated_rx_dmapath_s) == 1'b1) ?
(rx_valid_q1 & tdd_rx_rf_en) : rx_valid_q1;
assign tdd_enable = tdd_enable_s;
// assign tdd_enable = tdd_enable_s;
assign tdd_sync_t = tdd_terminal_type_s;
// catch generated sync signal
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_slave_synced <= 1'b0;
end else begin
if(tdd_sync_i == 1) begin
tdd_slave_synced <= 1'b1;
end else begin
tdd_slave_synced <= tdd_slave_synced & tdd_enable_s;
end
end
end
// generate sync signal
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_o <= 1'b0;
end else begin
if(~tdd_enable & tdd_enable_s == 1'b1) begin
tdd_sync_o <= 1'b1;
end else begin
tdd_sync_o <= 1'b0;
end
end
end
// generate tdd enable in function of the terminal type
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_enable <= 1'b0;
end else begin
tdd_enable <= (tdd_terminal_type_s == 1'b1) ? tdd_enable_s :
(tdd_enable_s & tdd_slave_synced);
end
end
// instantiations
@ -224,6 +277,7 @@ module axi_ad9361_tdd (
.tdd_gated_tx_dmapath(tdd_gated_tx_dmapath_s),
.tdd_counter_init(tdd_counter_init_s),
.tdd_frame_length(tdd_frame_length_s),
.tdd_terminal_type(tdd_terminal_type_s),
.tdd_vco_rx_on_1(tdd_vco_rx_on_1_s),
.tdd_vco_rx_off_1(tdd_vco_rx_off_1_s),
.tdd_vco_tx_on_1(tdd_vco_tx_on_1_s),

16
library/common/up_tdd_cntrl.v
View File

@ -54,6 +54,7 @@ module up_tdd_cntrl (
tdd_burst_count,
tdd_counter_init,
tdd_frame_length,
tdd_terminal_type,
tdd_vco_rx_on_1,
tdd_vco_rx_off_1,
tdd_vco_tx_on_1,
@ -107,6 +108,7 @@ module up_tdd_cntrl (
output [ 7:0] tdd_burst_count;
output [23:0] tdd_counter_init;
output [23:0] tdd_frame_length;
output tdd_terminal_type;
output [23:0] tdd_vco_rx_on_1;
output [23:0] tdd_vco_rx_off_1;
output [23:0] tdd_vco_tx_on_1;
@ -156,6 +158,7 @@ module up_tdd_cntrl (
reg up_tdd_tx_only = 1'h0;
reg up_tdd_gated_tx_dmapath = 1'h0;
reg up_tdd_gated_rx_dmapath = 1'h0;
reg up_tdd_terminal_type = 1'h0;
reg [ 7:0] up_tdd_burst_count = 8'h0;
reg [23:0] up_tdd_counter_init = 24'h0;
@ -206,6 +209,7 @@ module up_tdd_cntrl (
up_tdd_tx_only <= 1'h0;
up_tdd_gated_tx_dmapath <= 1'h0;
up_tdd_gated_rx_dmapath <= 1'h0;
up_tdd_terminal_type <= 1'h0;
up_tdd_counter_init <= 24'h0;
up_tdd_frame_length <= 24'h0;
up_tdd_burst_count <= 8'h0;
@ -246,6 +250,9 @@ module up_tdd_cntrl (
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h13)) begin
up_tdd_frame_length <= up_wdata[23:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h14)) begin
up_tdd_terminal_type <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h20)) begin
up_tdd_vco_rx_on_1 <= up_wdata[23:0];
end
@ -328,6 +335,7 @@ module up_tdd_cntrl (
8'h11: up_rdata <= {24'h0, up_tdd_burst_count};
8'h12: up_rdata <= { 8'h0, up_tdd_counter_init};
8'h13: up_rdata <= { 8'h0, up_tdd_frame_length};
8'h14: up_rdata <= {31'h0, up_tdd_terminal_type};
8'h18: up_rdata <= {24'h0, up_tdd_status_s};
8'h20: up_rdata <= { 8'h0, up_tdd_vco_rx_on_1};
8'h21: up_rdata <= { 8'h0, up_tdd_vco_rx_off_1};
@ -357,7 +365,7 @@ module up_tdd_cntrl (
// rf tdd control signal CDC
up_xfer_cntrl #(.DATA_WIDTH(14)) i_tdd_control (
up_xfer_cntrl #(.DATA_WIDTH(15)) i_tdd_control (
.up_rstn(up_rstn),
.up_clk(up_clk),
.up_data_cntrl({up_tdd_enable,
@ -366,7 +374,8 @@ module up_tdd_cntrl (
up_tdd_tx_only,
up_tdd_gated_rx_dmapath,
up_tdd_gated_tx_dmapath,
up_tdd_burst_count
up_tdd_burst_count,
up_tdd_terminal_type
}),
.up_xfer_done(),
.d_rst(rst),
@ -377,7 +386,8 @@ module up_tdd_cntrl (
tdd_tx_only,
tdd_gated_rx_dmapath,
tdd_gated_tx_dmapath,
tdd_burst_count
tdd_burst_count,
tdd_terminal_type
}));
up_xfer_cntrl #(.DATA_WIDTH(528)) i_tdd_counter_values (

8
projects/fmcomms2/common/fmcomms2_bd.tcl
View File

@ -19,6 +19,10 @@ create_bd_port -dir O enable
create_bd_port -dir O txnrx
create_bd_port -dir O tdd_enable
create_bd_port -dir I tdd_sync_i
create_bd_port -dir O tdd_sync_o
create_bd_port -dir O tdd_sync_t
# ad9361 core
set axi_ad9361 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9361:1.0 axi_ad9361]
@ -136,6 +140,10 @@ ad_connect util_ad9361_dac_upack/dac_data_3 axi_ad9361/dac_data_q1
ad_connect util_ad9361_dac_upack/dac_valid axi_ad9361_dac_dma/fifo_rd_en
ad_connect util_ad9361_dac_upack/dac_data axi_ad9361_dac_dma/fifo_rd_dout
ad_connect axi_ad9361_dac_dma/fifo_rd_underflow axi_ad9361/dac_dunf
ad_connect tdd_sync_i axi_ad9361/tdd_sync_i
ad_connect tdd_sync_o axi_ad9361/tdd_sync_o
ad_connect tdd_sync_t axi_ad9361/tdd_sync_t
ad_connect tdd_enable axi_ad9361/tdd_enable
# interconnects

1
projects/fmcomms2/rfsom/system_constr.xdc
View File

@ -36,6 +36,7 @@ set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS} [get_ports tx_data_o
set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS} [get_ports tx_data_out_n[5]] ; ## IO_L18N_T2_AD13N_35
set_property -dict {PACKAGE_PIN G14 IOSTANDARD LVCMOS18} [get_ports enable] ; ## IO_L11P_T1_SRCC_35
set_property -dict {PACKAGE_PIN F14 IOSTANDARD LVCMOS18} [get_ports txnrx] ; ## IO_L11N_T1_SRCC_35
set_property -dict {PACKAGE_PIN AA18 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## IO_L24_13_JX2_N
set_property -dict {PACKAGE_PIN D13 IOSTANDARD LVCMOS18} [get_ports gpio_status[0]] ; ## IO_L19P_T3_35
set_property -dict {PACKAGE_PIN C13 IOSTANDARD LVCMOS18} [get_ports gpio_status[1]] ; ## IO_L19N_T3_VREF_35

17
projects/fmcomms2/rfsom/system_top.v
View File

@ -109,6 +109,7 @@ module system_top (
tx_data_out_n,
enable,
txnrx,
tdd_sync,
gpio_rf0,
gpio_rf1,
@ -196,6 +197,7 @@ module system_top (
output [ 5:0] tx_data_out_n;
output enable;
output txnrx;
inout tdd_sync;
inout gpio_rf0;
inout gpio_rf1;
@ -227,6 +229,10 @@ module system_top (
wire enable_s;
wire txnrx_s;
wire tdd_sync_t_s;
wire tdd_sync_o_s;
wire tdd_sync_i_s;
// assignments
assign hdmi_pd = 1'b0;
@ -259,6 +265,12 @@ module system_top (
.dio_o (gpio_i[11:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync (
.dio_t (tdd_sync_t_s),
.dio_i (tdd_sync_o_s),
.dio_o (tdd_sync_i_s),
.dio_p (tdd_sync));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -359,7 +371,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
.tdd_enable (tdd_enable_s),
.tdd_sync_i (tdd_sync_i_s),
.tdd_sync_o (tdd_sync_o_s),
.tdd_sync_t (tdd_sync_t_s));
endmodule

1
projects/fmcomms2/zc706/system_constr.xdc
View File

@ -36,6 +36,7 @@ set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_o
set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports enable] ; ## G18 FMC_LPC_LA16_P
set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports txnrx] ; ## G19 FMC_LPC_LA16_N
set_property -dict {PACKAGE_PIN AC19 IOSTANDARD LVCMOS25} [get_ports tdd_sync] ; ## PMOD1_7_LS
set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N

16
projects/fmcomms2/zc706/system_top.v
View File

@ -92,6 +92,7 @@ module system_top (
enable,
txnrx,
tdd_sync,
gpio_muxout_tx,
gpio_muxout_rx,
@ -162,6 +163,7 @@ module system_top (
output enable;
output txnrx;
inout tdd_sync;
inout gpio_muxout_tx;
inout gpio_muxout_rx;
@ -213,6 +215,9 @@ module system_top (
wire gpio_txnrx;
wire enable_s;
wire txnrx_s;
wire tdd_sync_t_s;
wire tdd_sync_o_s;
wire tdd_sync_i_s;
assign enable = (tdd_enable_s == 1'b1) ? enable_s : gpio_enable;
assign txnrx = (tdd_enable_s == 1'b1) ? txnrx_s : gpio_txnrx;
@ -239,6 +244,12 @@ module system_top (
.dio_o (gpio_i[14:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(1)) i_tdd_sync (
.dio_t (tdd_sync_t_s),
.dio_i (tdd_sync_o_s),
.dio_o (tdd_sync_i_s),
.dio_p (tdd_sync));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
@ -316,7 +327,10 @@ module system_top (
.tx_frame_out_n (tx_frame_out_n),
.tx_frame_out_p (tx_frame_out_p),
.txnrx (txnrx_s),
.tdd_enable (tdd_enable_s));
.tdd_enable (tdd_enable_s),
.tdd_sync_i (tdd_sync_i_s),
.tdd_sync_o (tdd_sync_o_s),
.tdd_sync_t (tdd_sync_t_s));
endmodule