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axi_ad9162: Infer clock signal for tx_clk port 

Fixes the following warning:
  [BD 41-1731] Type mismatch between connected pins: /util_fmcomms11_xcvr/tx_out_clk_0(clk) and /axi_ad9162_core/tx_clk(undef)

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2018-04-17 13:49:50 +02:00
parent bfac56199e
commit 8e90d5db20
1 changed files with 2 additions and 2 deletions
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4
library/axi_ad9162/axi_ad9162_ip.tcl
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@ -31,6 +31,6 @@ set_property driver_value 0 [ipx::get_ports *dovf* -of_objects [ipx::current_cor
set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *dunf* -of_objects [ipx::current_core]]
set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]] set_property driver_value 0 [ipx::get_ports *tx_ready* -of_objects [ipx::current_core]]
ipx::infer_bus_interface tx_clk xilinx.com:signal:clock_rtl:1.0 [ipx::current_core]
ipx::save_core [ipx::current_core] ipx::save_core [ipx::current_core]