fmcadc2: Updates

projects/fmcadc2/common/fmcadc2_bd.tcl

@@ -25,20 +25,21 @@ set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9625_dma
 set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9625_dma
 
 set util_fmcadc2_xcvr [create_bd_cell -type ip -vlnv analog.com:user:util_adxcvr:1.0 util_fmcadc2_xcvr]
-set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.QPLL_FBDIV {"0010000000"}] $util_fmcadc2_xcvr ;# N = 40
-set_property -dict [list CONFIG.CPLL_FBDIV {2}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.CPLL_FBDIV {1}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.TX_NUM_OF_LANES {0}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.TX_OUT_DIV {2}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_OUT_DIV {1}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.TX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.TX_CLK25_DIV {25}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_NUM_OF_LANES {8}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_OUT_DIV {1}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.RX_CLK25_DIV {10}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CLK25_DIV {25}] $util_fmcadc2_xcvr
 set_property -dict [list CONFIG.RX_DFE_LPM_CFG {0x0904}] $util_fmcadc2_xcvr
-set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff10200020}] $util_fmcadc2_xcvr
+set_property -dict [list CONFIG.RX_CDR_CFG {0x03000023ff20400020}] $util_fmcadc2_xcvr ;# DFE mode refclk +-200
 
 # reference clocks & resets
 
 create_bd_port -dir I rx_ref_clk_0
+create_bd_port -dir O rx_clk
 
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/qpll_ref_clk_*
 ad_xcvrpll  rx_ref_clk_0 util_fmcadc2_xcvr/cpll_ref_clk_*
@@ -46,6 +47,7 @@ ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_qpll_rst_*
 ad_xcvrpll  axi_ad9625_xcvr/up_pll_rst util_fmcadc2_xcvr/up_cpll_rst_*
 ad_connect  sys_cpu_resetn util_fmcadc2_xcvr/up_rstn
 ad_connect  sys_cpu_clk util_fmcadc2_xcvr/up_clk
+ad_connect  util_fmcadc2_xcvr/rx_out_clk_0 rx_clk
 
 # connections (adc)
 

projects/fmcadc2/vc707/system_constr.xdc

@@ -41,3 +41,6 @@ create_clock -name rx_ref_clk   -period  1.60 [get_ports rx_ref_clk_p]
 create_clock -name rx_div_clk   -period  6.40 [get_pins i_system_wrapper/system_i/util_fmcadc2_xcvr/inst/i_xch_0/i_gtxe2_channel/RXOUTCLK]
 
 set_false_path -from [get_cells i_system_wrapper/system_i/axi_ad9625_jesd_rstgen/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]]
+
+set_property shreg_extract no [get_cells -hier -filter {name =~ *rx_sysref_m*}]
+set_false_path -from [get_cells -hier -filter {name =~ *rx_sysref_m1_reg  && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *rx_sysref_reg     && IS_SEQUENTIAL}]

projects/fmcadc2/vc707/system_top.v

@@ -181,6 +181,13 @@ module system_top (
   output            spi_adf4355_le_or_clk;
   inout             spi_adf4355_ce_or_sdio;
 
+  // internal registers
+
+  reg             rx_sysref = 'd0;
+  reg             rx_sysref_m1 = 'd0;
+  reg             rx_sysref_m2 = 'd0;
+  reg             rx_sysref_m3 = 'd0;
+
   // internal signals
 
   wire    [63:0]    gpio_i;
@@ -190,7 +197,6 @@ module system_top (
   wire              spi_mosi;
   wire              spi_miso;
   wire              rx_ref_clk;
-  wire              rx_sysref;
   wire              rx_sync;
 
   // default logic
@@ -198,6 +204,14 @@ module system_top (
   assign fan_pwm = 1'b1;
   assign iic_rstn = 1'b1;
 
+  // sysref internal
+
+  always @(posedge rx_clk) begin
+    rx_sysref_m1 <= gpio_o[34];
+    rx_sysref_m2 <= rx_sysref_m1;
+    rx_sysref <= rx_sysref_m2;
+  end
+
   // instantiations
 
   IBUFDS_GTE2 i_ibufds_rx_ref_clk (
@@ -324,7 +338,8 @@ module system_top (
     .sys_clk_p (sys_clk_p),
     .sys_rst (sys_rst),
     .uart_sin (uart_sin),
-    .uart_sout (uart_sout));
+    .uart_sout (uart_sout),
+    .rx_clk (rx_clk));
 
 endmodule
 

projects/fmcadc2/zc706/system_project.tcl

@@ -8,8 +8,25 @@ adi_project_files fmcadc2_zc706 [list \
   "../common/fmcadc2_spi.v" \
   "system_top.v" \
   "system_constr.xdc" \
+  "$ad_hdl_dir/library/xilinx/common/ad_lvds_out.v" \
   "$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_mig_constr.xdc" \
   "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
 
 adi_project_run fmcadc2_zc706
+
+set ila_core [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.1 ila_core]
+set_property -dict [list CONFIG.C_MONITOR_TYPE {Native}] $ila_core
+set_property -dict [list CONFIG.C_TRIGIN_EN {false}] $ila_core
+set_property -dict [list CONFIG.C_EN_STRG_QUAL {1}] $ila_core
+set_property -dict [list CONFIG.C_NUM_OF_PROBES {4}] $ila_core
+set_property -dict [list CONFIG.C_PROBE0_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE1_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE2_WIDTH {1}] $ila_core
+set_property -dict [list CONFIG.C_PROBE3_WIDTH {256}] $ila_core
+
+ad_connect  axi_ad9625_core/adc_clk ila_core/clk
+ad_connect  axi_ad9625_core/adc_rst ila_core/probe0
+ad_connect  axi_ad9625_core/adc_valid ila_core/probe1
+ad_connect  axi_ad9625_core/rx_ready ila_core/probe2
+ad_connect  axi_ad9625_core/adc_data ila_core/probe3

projects/fmcadc2/zc706/system_top.v

@@ -195,6 +195,11 @@ module system_top (
   output          spi_adf4355_le_or_clk;
   inout           spi_adf4355_ce_or_sdio;
 
+  // internal registers
+
+  reg             rx_sysref = 'd0;
+  reg             rx_sysref_d = 'd0;
+
   // internal signals
 
   wire    [63:0]  gpio_i;
@@ -209,8 +214,15 @@ module system_top (
   wire            spi1_mosi;
   wire            spi1_miso;
   wire            rx_ref_clk;
-  wire            rx_sysref;
   wire            rx_sync;
+  wire            rx_clk;
+
+  // sysref internal
+
+  always @(posedge rx_clk) begin
+    rx_sysref_d <= gpio_o[34];
+    rx_sysref <= rx_sysref_d;
+  end
 
   // instantiations
 
@@ -362,7 +374,8 @@ module system_top (
     .spi1_sdo_o (spi1_mosi),
     .sys_clk_clk_n (sys_clk_n),
     .sys_clk_clk_p (sys_clk_p),
-    .sys_rst (sys_rst));
+    .sys_rst (sys_rst),
+    .rx_clk (rx_clk));
 
 endmodule