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library/tdd_control: Add common registers to the register map and fix init value of a register 

+ Software in general needs to have access to the VERSION register.
+ tdd_sync_d3 registers init value should be 1'b0
main
Istvan Csomortani 2015-10-16 11:55:22 +03:00
parent bbdc693954
commit 8ecdb4a4ca
2 changed files with 7 additions and 1 deletions
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2
library/common/ad_tdd_control.v
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@ -226,7 +226,7 @@ module ad_tdd_control(
// edge detection circuit
always @(posedge clk) begin
if (rst == 1'b1) begin
tdd_sync_d3 <= 1'b1;
tdd_sync_d3 <= 1'b0;
tdd_sync_pulse <= 1'b0;
end else begin
tdd_sync_d3 <= tdd_sync_d2;

6
library/common/up_tdd_cntrl.v
View File

@ -241,6 +241,9 @@ module up_tdd_cntrl (
up_tdd_tx_dp_on_2 <= 24'h0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_tdd_enable <= up_wdata[0];
up_tdd_secondary <= up_wdata[1];
@ -338,6 +341,9 @@ module up_tdd_cntrl (
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[7:0])
8'h00: up_rdata <= PCORE_VERSION;
8'h01: up_rdata <= ID;
8'h02: up_rdata <= up_scratch;
8'h10: up_rdata <= {28'h0, up_tdd_gated_tx_dmapath,
up_tdd_gated_rx_dmapath,
up_tdd_tx_only,