zcy
/
pluto_hdl_adi
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

pzsdr: ccpci: Add PCIe reset monitor 

For reliable and correct operation it is vital that the FPGA is fully
configured and up and running before the PCIe host de-asserts the reset.

Add a small logic circuit that detects de-assertion of the reset signal
that can be used to verify that the reset de-assertion was seen by the
FPGA.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
main
Lars-Peter Clausen 2016-07-14 17:20:09 +02:00
parent 91782989ad
commit 8f61e11a70
2 changed files with 34 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
projects/pzsdr/ccpci/system_constr.xdc
View File

@ -21,6 +21,7 @@ set_property -dict {PACKAGE_PIN AF8} [get_ports pcie_data_tx_p[3]]
set_property -dict {PACKAGE_PIN AF7} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN0_111 set_property -dict {PACKAGE_PIN AF7} [get_ports pcie_data_tx_n[3]] ; ## MGTXTXN0_111
set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports pcie_rstn] ; ## IO_L19P_T3_13 set_property -dict {PACKAGE_PIN W20 IOSTANDARD LVCMOS33} [get_ports pcie_rstn] ; ## IO_L19P_T3_13
set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports pcie_waken] ; ## IO_L20N_T3_13 set_property -dict {PACKAGE_PIN AB20 IOSTANDARD LVCMOS33} [get_ports pcie_waken] ; ## IO_L20N_T3_13
set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS33} [get_ports pcie_rstn_good] ; ## IO_L22N_T3_12
# Default constraints have LVCMOS25, overwite it # Default constraints have LVCMOS25, overwite it
set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl] ; ## IO_L5P_T0_13 set_property -dict {IOSTANDARD LVCMOS33} [get_ports iic_scl] ; ## IO_L5P_T0_13

35
projects/pzsdr/ccpci/system_top.v
View File

@ -101,7 +101,9 @@ module system_top (
pcie_data_rx_p, pcie_data_rx_p,
pcie_data_rx_n, pcie_data_rx_n,
pcie_data_tx_p, pcie_data_tx_p,
pcie_data_tx_n); pcie_data_tx_n,
pcie_rstn_good);
inout [14:0] ddr_addr; inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba; inout [ 2:0] ddr_ba;
@ -167,8 +169,14 @@ module system_top (
output [ 3:0] pcie_data_tx_p; output [ 3:0] pcie_data_tx_p;
output [ 3:0] pcie_data_tx_n; output [ 3:0] pcie_data_tx_n;
output pcie_rstn_good;
// internal signals // internal signals
reg [3:0] pcie_rstn_cnt0 = 'h00;
reg [3:0] pcie_rstn_cnt1 = 'h00;
reg pcie_rstn_good = 1'b0;
wire pcie_ref_clk; wire pcie_ref_clk;
wire [63:0] gpio_i; wire [63:0] gpio_i;
wire [63:0] gpio_o; wire [63:0] gpio_o;
@ -179,7 +187,30 @@ module system_top (
// assignments // assignments
assign pcie_waken = 1'bz; assign pcie_waken = 1'bz;
assign gpio_ps_i[63:0] = 'h00; assign gpio_ps_i[0] = pcie_rstn_good;
assign gpio_ps_i[63:1] = 'h00;
// PCIe reset monitor
always @(posedge pcie_ref_clk) begin
// If we see a stable low level followed by a stable high level we assume we
// got a good PCIe reset
if (pcie_rstn_cnt0 != 'hf) begin
if (pcie_rstn == 1'b0) begin
pcie_rstn_cnt0 <= pcie_rstn_cnt0 + 1'b1;
end else begin
pcie_rstn_cnt0 <= 'h00;
end
end else if (pcie_rstn_cnt1 != 'hf) begin
if (pcie_rstn == 1'b1) begin
pcie_rstn_cnt1 <= pcie_rstn_cnt1 + 1'b1;
end else begin
pcie_rstn_cnt1 <= 'h00;
end
end else begin
pcie_rstn_good <= 1'b1;
end
end
// instantiations // instantiations