diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xch.v b/library/xilinx/util_adxcvr/util_adxcvr_xch.v index 533d922d3..80ace5d4a 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xch.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xch.v @@ -1531,12 +1531,12 @@ module util_adxcvr_xch #( .ACJTAG_DEBUG_MODE (1'b0), .ACJTAG_MODE (1'b0), .ACJTAG_RESET (1'b0), - .ADAPT_CFG0 (16'h1000), - .ADAPT_CFG1 (16'hc800), - .ADAPT_CFG2 (16'h0000), + .ADAPT_CFG0 (16'b0001000000000000), + .ADAPT_CFG1 (16'b1100100000000000), + .ADAPT_CFG2 (16'b0000000000000000), .ALIGN_COMMA_DOUBLE ("FALSE"), .ALIGN_COMMA_ENABLE (10'b1111111111), - .ALIGN_COMMA_WORD (1'h1), + .ALIGN_COMMA_WORD (1), .ALIGN_MCOMMA_DET ("TRUE"), .ALIGN_MCOMMA_VALUE (10'b1010000011), .ALIGN_PCOMMA_DET ("TRUE"), @@ -1551,7 +1551,7 @@ module util_adxcvr_xch #( .CDR_SWAP_MODE_EN (1'b0), .CFOK_PWRSVE_EN (1'b1), .CHAN_BOND_KEEP_ALIGN ("FALSE"), - .CHAN_BOND_MAX_SKEW (1'h1), + .CHAN_BOND_MAX_SKEW (1), .CHAN_BOND_SEQ_1_1 (10'b0000000000), .CHAN_BOND_SEQ_1_2 (10'b0000000000), .CHAN_BOND_SEQ_1_3 (10'b0000000000), @@ -1563,8 +1563,8 @@ module util_adxcvr_xch #( .CHAN_BOND_SEQ_2_4 (10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE (4'b1111), .CHAN_BOND_SEQ_2_USE ("FALSE"), - .CHAN_BOND_SEQ_LEN (1'h1), - .CH_HSPMUX (16'h2424), + .CHAN_BOND_SEQ_LEN (1), + .CH_HSPMUX (16'b0010010000100100), .CKCAL1_CFG_0 (16'b1100000011000000), .CKCAL1_CFG_1 (16'b0101000011000000), .CKCAL1_CFG_2 (16'b0000000000001010), @@ -1574,14 +1574,14 @@ module util_adxcvr_xch #( .CKCAL2_CFG_2 (16'b0000000000000000), .CKCAL2_CFG_3 (16'b0000000000000000), .CKCAL2_CFG_4 (16'b0000000000000000), - .CKCAL_RSVD0 (16'h0080), - .CKCAL_RSVD1 (16'h0400), + .CKCAL_RSVD0 (16'b0000000010000000), + .CKCAL_RSVD1 (16'b0000010000000000), .CLK_CORRECT_USE ("FALSE"), .CLK_COR_KEEP_IDLE ("FALSE"), .CLK_COR_MAX_LAT (12), .CLK_COR_MIN_LAT (8), .CLK_COR_PRECEDENCE ("TRUE"), - .CLK_COR_REPEAT_WAIT (1'h0), + .CLK_COR_REPEAT_WAIT (0), .CLK_COR_SEQ_1_1 (10'b0100000000), .CLK_COR_SEQ_1_2 (10'b0100000000), .CLK_COR_SEQ_1_3 (10'b0100000000), @@ -1593,16 +1593,16 @@ module util_adxcvr_xch #( .CLK_COR_SEQ_2_4 (10'b0100000000), .CLK_COR_SEQ_2_ENABLE (4'b1111), .CLK_COR_SEQ_2_USE ("FALSE"), - .CLK_COR_SEQ_LEN (1'h1), - .CPLL_CFG0 (16'h01fa), - .CPLL_CFG1 (16'h0023), - .CPLL_CFG2 (16'h0002), - .CPLL_CFG3 (16'h0000), + .CLK_COR_SEQ_LEN (1), + .CPLL_CFG0 (16'b0000000111111010), + .CPLL_CFG1 (16'b0000000000100011), + .CPLL_CFG2 (16'b0000000000000010), + .CPLL_CFG3 (16'b0000000000000000), .CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV_45 (CPLL_FBDIV_4_5), - .CPLL_INIT_CFG0 (16'h02b2), - .CPLL_LOCK_CFG (16'h01e8), - .CPLL_REFCLK_DIV (1'h1), + .CPLL_INIT_CFG0 (16'b0000001010110010), + .CPLL_LOCK_CFG (16'b0000000111101000), + .CPLL_REFCLK_DIV (1), .CTLE3_OCAP_EXT_CTRL (3'b000), .CTLE3_OCAP_EXT_EN (1'b0), .DDI_CTRL (2'b00), @@ -1611,44 +1611,44 @@ module util_adxcvr_xch #( .DEC_PCOMMA_DETECT ("TRUE"), .DEC_VALID_COMMA_ONLY ("FALSE"), .DELAY_ELEC (1'b0), - .DMONITOR_CFG0 (10'h000), - .DMONITOR_CFG1 (8'h00), + .DMONITOR_CFG0 (10'b0000000000), + .DMONITOR_CFG1 (8'b00000000), .ES_CLK_PHASE_SEL (1'b0), .ES_CONTROL (6'b000000), .ES_ERRDET_EN ("TRUE"), .ES_EYE_SCAN_EN ("TRUE"), - .ES_HORZ_OFFSET (12'h000), + .ES_HORZ_OFFSET (12'b000000000000), .ES_PRESCALE (5'b00000), - .ES_QUALIFIER0 (16'h0000), - .ES_QUALIFIER1 (16'h0000), - .ES_QUALIFIER2 (16'h0000), - .ES_QUALIFIER3 (16'h0000), - .ES_QUALIFIER4 (16'h0000), - .ES_QUALIFIER5 (16'h0000), - .ES_QUALIFIER6 (16'h0000), - .ES_QUALIFIER7 (16'h0000), - .ES_QUALIFIER8 (16'h0000), - .ES_QUALIFIER9 (16'h0000), - .ES_QUAL_MASK0 (16'h0000), - .ES_QUAL_MASK1 (16'h0000), - .ES_QUAL_MASK2 (16'h0000), - .ES_QUAL_MASK3 (16'h0000), - .ES_QUAL_MASK4 (16'h0000), - .ES_QUAL_MASK5 (16'h0000), - .ES_QUAL_MASK6 (16'h0000), - .ES_QUAL_MASK7 (16'h0000), - .ES_QUAL_MASK8 (16'h0000), - .ES_QUAL_MASK9 (16'h0000), - .ES_SDATA_MASK0 (16'hffff), - .ES_SDATA_MASK1 (16'hffff), - .ES_SDATA_MASK2 (16'h00ff), - .ES_SDATA_MASK3 (16'h0000), - .ES_SDATA_MASK4 (16'h0000), - .ES_SDATA_MASK5 (16'hffff), - .ES_SDATA_MASK6 (16'hffff), - .ES_SDATA_MASK7 (16'hffff), - .ES_SDATA_MASK8 (16'hffff), - .ES_SDATA_MASK9 (16'hffff), + .ES_QUALIFIER0 (16'b0000000000000000), + .ES_QUALIFIER1 (16'b0000000000000000), + .ES_QUALIFIER2 (16'b0000000000000000), + .ES_QUALIFIER3 (16'b0000000000000000), + .ES_QUALIFIER4 (16'b0000000000000000), + .ES_QUALIFIER5 (16'b0000000000000000), + .ES_QUALIFIER6 (16'b0000000000000000), + .ES_QUALIFIER7 (16'b0000000000000000), + .ES_QUALIFIER8 (16'b0000000000000000), + .ES_QUALIFIER9 (16'b0000000000000000), + .ES_QUAL_MASK0 (16'b0000000000000000), + .ES_QUAL_MASK1 (16'b0000000000000000), + .ES_QUAL_MASK2 (16'b0000000000000000), + .ES_QUAL_MASK3 (16'b0000000000000000), + .ES_QUAL_MASK4 (16'b0000000000000000), + .ES_QUAL_MASK5 (16'b0000000000000000), + .ES_QUAL_MASK6 (16'b0000000000000000), + .ES_QUAL_MASK7 (16'b0000000000000000), + .ES_QUAL_MASK8 (16'b0000000000000000), + .ES_QUAL_MASK9 (16'b0000000000000000), + .ES_SDATA_MASK0 (16'b1111111111111111), + .ES_SDATA_MASK1 (16'b1111111111111111), + .ES_SDATA_MASK2 (16'b0000000011111111), + .ES_SDATA_MASK3 (16'b0000000000000000), + .ES_SDATA_MASK4 (16'b0000000000000000), + .ES_SDATA_MASK5 (16'b1111111111111111), + .ES_SDATA_MASK6 (16'b1111111111111111), + .ES_SDATA_MASK7 (16'b1111111111111111), + .ES_SDATA_MASK8 (16'b1111111111111111), + .ES_SDATA_MASK9 (16'b1111111111111111), .EYE_SCAN_SWAP_EN (1'b0), .FTS_DESKEW_SEQ_ENABLE (4'b1111), .FTS_LANE_DESKEW_CFG (4'b1111), @@ -1679,20 +1679,20 @@ module util_adxcvr_xch #( .PCIE3_CLK_COR_MAX_LAT (5'b00100), .PCIE3_CLK_COR_MIN_LAT (5'b00000), .PCIE3_CLK_COR_THRSH_TIMER (6'b001000), - .PCIE_BUFG_DIV_CTRL (16'h3500), - .PCIE_PLL_SEL_MODE_GEN12 (2'h2), - .PCIE_PLL_SEL_MODE_GEN3 (2'h2), - .PCIE_PLL_SEL_MODE_GEN4 (2'h2), - .PCIE_RXPCS_CFG_GEN3 (16'h0aa5), - .PCIE_RXPMA_CFG (16'h280a), - .PCIE_TXPCS_CFG_GEN3 (16'h24a4), - .PCIE_TXPMA_CFG (16'h280a), + .PCIE_BUFG_DIV_CTRL (16'b0011010100000000), + .PCIE_PLL_SEL_MODE_GEN12 (2'b10), + .PCIE_PLL_SEL_MODE_GEN3 (2'b10), + .PCIE_PLL_SEL_MODE_GEN4 (2'b10), + .PCIE_RXPCS_CFG_GEN3 (16'b0000101010100101), + .PCIE_RXPMA_CFG (16'b0010100000001010), + .PCIE_TXPCS_CFG_GEN3 (16'b0010010010100100), + .PCIE_TXPMA_CFG (16'b0010100000001010), .PCS_PCIE_EN ("FALSE"), .PCS_RSVD0 (16'b0000000000000000), - .PD_TRANS_TIME_FROM_P2 (12'h03c), - .PD_TRANS_TIME_NONE_P2 (8'h19), - .PD_TRANS_TIME_TO_P2 (8'h64), - .PREIQ_FREQ_BST (1'h0), + .PD_TRANS_TIME_FROM_P2 (12'b000000111100), + .PD_TRANS_TIME_NONE_P2 (8'b00011001), + .PD_TRANS_TIME_TO_P2 (8'b01100100), + .PREIQ_FREQ_BST (0), .PROCESS_PAR (3'b010), .RATE_SW_USE_DRP (1'b1), .RCLK_SIPO_DLY_ENB (1'b0), @@ -1714,111 +1714,111 @@ module util_adxcvr_xch #( .RXBUF_THRESH_UNDFLW (3), .RXCDRFREQRESET_TIME (5'b00001), .RXCDRPHRESET_TIME (5'b00001), - .RXCDR_CFG0 (16'h0002), - .RXCDR_CFG0_GEN3 (16'h0003), - .RXCDR_CFG1 (16'h0000), - .RXCDR_CFG1_GEN3 (16'h0000), - .RXCDR_CFG2 (16'h0265), - .RXCDR_CFG2_GEN3 (16'h0265), - .RXCDR_CFG2_GEN4 (16'h00b4), - .RXCDR_CFG3 (16'h0012), - .RXCDR_CFG3_GEN3 (16'h0012), - .RXCDR_CFG3_GEN4 (16'h0024), - .RXCDR_CFG4 (16'h5cf6), - .RXCDR_CFG4_GEN3 (16'h5cf6), - .RXCDR_CFG5 (16'hb46b), - .RXCDR_CFG5_GEN3 (16'h146b), + .RXCDR_CFG0 (16'b0000000000000010), + .RXCDR_CFG0_GEN3 (16'b0000000000000011), + .RXCDR_CFG1 (16'b0000000000000000), + .RXCDR_CFG1_GEN3 (16'b0000000000000000), + .RXCDR_CFG2 (16'b0000001001100101), + .RXCDR_CFG2_GEN3 (16'b0000001001100101), + .RXCDR_CFG2_GEN4 (16'b0000000010110100), + .RXCDR_CFG3 (16'b0000000000010010), + .RXCDR_CFG3_GEN3 (16'b0000000000010010), + .RXCDR_CFG3_GEN4 (16'b0000000000100100), + .RXCDR_CFG4 (16'b0101110011110110), + .RXCDR_CFG4_GEN3 (16'b0101110011110110), + .RXCDR_CFG5 (16'b1011010001101011), + .RXCDR_CFG5_GEN3 (16'b0001010001101011), .RXCDR_FR_RESET_ON_EIDLE (1'b0), .RXCDR_HOLD_DURING_EIDLE (1'b0), - .RXCDR_LOCK_CFG0 (16'h2201), - .RXCDR_LOCK_CFG1 (16'h9fff), - .RXCDR_LOCK_CFG2 (16'h77c3), - .RXCDR_LOCK_CFG3 (16'h0001), - .RXCDR_LOCK_CFG4 (16'h0000), + .RXCDR_LOCK_CFG0 (16'b0010001000000001), + .RXCDR_LOCK_CFG1 (16'b1001111111111111), + .RXCDR_LOCK_CFG2 (16'b0111011111000011), + .RXCDR_LOCK_CFG3 (16'b0000000000000001), + .RXCDR_LOCK_CFG4 (16'b0000000000000000), .RXCDR_PH_RESET_ON_EIDLE (1'b0), - .RXCFOK_CFG0 (16'h0000), - .RXCFOK_CFG1 (16'h8015), - .RXCFOK_CFG2 (16'h02ae), - .RXCKCAL1_IQ_LOOP_RST_CFG (16'h0004), - .RXCKCAL1_I_LOOP_RST_CFG (16'h0004), - .RXCKCAL1_Q_LOOP_RST_CFG (16'h0004), - .RXCKCAL2_DX_LOOP_RST_CFG (16'h0004), - .RXCKCAL2_D_LOOP_RST_CFG (16'h0004), - .RXCKCAL2_S_LOOP_RST_CFG (16'h0004), - .RXCKCAL2_X_LOOP_RST_CFG (16'h0004), + .RXCFOK_CFG0 (16'b0000000000000000), + .RXCFOK_CFG1 (16'b1000000000010101), + .RXCFOK_CFG2 (16'b0000001010101110), + .RXCKCAL1_IQ_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL1_I_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL1_Q_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_DX_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_D_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_S_LOOP_RST_CFG (16'b0000000000000100), + .RXCKCAL2_X_LOOP_RST_CFG (16'b0000000000000100), .RXDFELPMRESET_TIME (7'b0001111), - .RXDFELPM_KL_CFG0 (16'h0000), - .RXDFELPM_KL_CFG1 (16'ha0e2), - .RXDFELPM_KL_CFG2 (16'h0100), - .RXDFE_CFG0 (16'h0a00), - .RXDFE_CFG1 (16'h0280), - .RXDFE_GC_CFG0 (16'h0000), - .RXDFE_GC_CFG1 (16'h8000), - .RXDFE_GC_CFG2 (16'hffe0), - .RXDFE_H2_CFG0 (16'h0000), - .RXDFE_H2_CFG1 (16'h0002), - .RXDFE_H3_CFG0 (16'h0000), - .RXDFE_H3_CFG1 (16'h8002), - .RXDFE_H4_CFG0 (16'h0000), - .RXDFE_H4_CFG1 (16'h8002), - .RXDFE_H5_CFG0 (16'h0000), - .RXDFE_H5_CFG1 (16'h8002), - .RXDFE_H6_CFG0 (16'h0000), - .RXDFE_H6_CFG1 (16'h8002), - .RXDFE_H7_CFG0 (16'h0000), - .RXDFE_H7_CFG1 (16'h8002), - .RXDFE_H8_CFG0 (16'h0000), - .RXDFE_H8_CFG1 (16'h8002), - .RXDFE_H9_CFG0 (16'h0000), - .RXDFE_H9_CFG1 (16'h8002), - .RXDFE_HA_CFG0 (16'h0000), - .RXDFE_HA_CFG1 (16'h8002), - .RXDFE_HB_CFG0 (16'h0000), - .RXDFE_HB_CFG1 (16'h8002), - .RXDFE_HC_CFG0 (16'h0000), - .RXDFE_HC_CFG1 (16'h8002), - .RXDFE_HD_CFG0 (16'h0000), - .RXDFE_HD_CFG1 (16'h8002), - .RXDFE_HE_CFG0 (16'h0000), - .RXDFE_HE_CFG1 (16'h8002), - .RXDFE_HF_CFG0 (16'h0000), - .RXDFE_HF_CFG1 (16'h8002), - .RXDFE_KH_CFG0 (16'h0000), - .RXDFE_KH_CFG1 (16'h8000), - .RXDFE_KH_CFG2 (16'h2613), - .RXDFE_KH_CFG3 (16'h411c), - .RXDFE_OS_CFG0 (16'h0000), - .RXDFE_OS_CFG1 (16'h8002), + .RXDFELPM_KL_CFG0 (16'b0000000000000000), + .RXDFELPM_KL_CFG1 (16'b1010000011100010), + .RXDFELPM_KL_CFG2 (16'b0000000100000000), + .RXDFE_CFG0 (16'b0000101000000000), + .RXDFE_CFG1 (16'b0000000000000000), + .RXDFE_GC_CFG0 (16'b0000000000000000), + .RXDFE_GC_CFG1 (16'b1000000000000000), + .RXDFE_GC_CFG2 (16'b1111111111100000), + .RXDFE_H2_CFG0 (16'b0000000000000000), + .RXDFE_H2_CFG1 (16'b0000000000000010), + .RXDFE_H3_CFG0 (16'b0000000000000000), + .RXDFE_H3_CFG1 (16'b1000000000000010), + .RXDFE_H4_CFG0 (16'b0000000000000000), + .RXDFE_H4_CFG1 (16'b1000000000000010), + .RXDFE_H5_CFG0 (16'b0000000000000000), + .RXDFE_H5_CFG1 (16'b1000000000000010), + .RXDFE_H6_CFG0 (16'b0000000000000000), + .RXDFE_H6_CFG1 (16'b1000000000000010), + .RXDFE_H7_CFG0 (16'b0000000000000000), + .RXDFE_H7_CFG1 (16'b1000000000000010), + .RXDFE_H8_CFG0 (16'b0000000000000000), + .RXDFE_H8_CFG1 (16'b1000000000000010), + .RXDFE_H9_CFG0 (16'b0000000000000000), + .RXDFE_H9_CFG1 (16'b1000000000000010), + .RXDFE_HA_CFG0 (16'b0000000000000000), + .RXDFE_HA_CFG1 (16'b1000000000000010), + .RXDFE_HB_CFG0 (16'b0000000000000000), + .RXDFE_HB_CFG1 (16'b1000000000000010), + .RXDFE_HC_CFG0 (16'b0000000000000000), + .RXDFE_HC_CFG1 (16'b1000000000000010), + .RXDFE_HD_CFG0 (16'b0000000000000000), + .RXDFE_HD_CFG1 (16'b1000000000000010), + .RXDFE_HE_CFG0 (16'b0000000000000000), + .RXDFE_HE_CFG1 (16'b1000000000000010), + .RXDFE_HF_CFG0 (16'b0000000000000000), + .RXDFE_HF_CFG1 (16'b1000000000000010), + .RXDFE_KH_CFG0 (16'b0000000000000000), + .RXDFE_KH_CFG1 (16'b1000000000000000), + .RXDFE_KH_CFG2 (16'b0010011000010011), + .RXDFE_KH_CFG3 (16'b0100000100011100), + .RXDFE_OS_CFG0 (16'b0000000000000000), + .RXDFE_OS_CFG1 (16'b1000000000000010), .RXDFE_PWR_SAVING (1'b1), - .RXDFE_UT_CFG0 (16'h0000), - .RXDFE_UT_CFG1 (16'h0003), - .RXDFE_UT_CFG2 (16'h0000), - .RXDFE_VP_CFG0 (16'h0000), - .RXDFE_VP_CFG1 (16'h8033), - .RXDLY_CFG (16'h0010), - .RXDLY_LCFG (16'h0030), + .RXDFE_UT_CFG0 (16'b0000000000000000), + .RXDFE_UT_CFG1 (16'b0000000000000011), + .RXDFE_UT_CFG2 (16'b0000000000000000), + .RXDFE_VP_CFG0 (16'b0000000000000000), + .RXDFE_VP_CFG1 (16'b1000000000110011), + .RXDLY_CFG (16'b0000000000010000), + .RXDLY_LCFG (16'b0000000000110000), .RXELECIDLE_CFG ("SIGCFG_4"), .RXGBOX_FIFO_INIT_RD_ADDR (4), .RXGEARBOX_EN ("FALSE"), .RXISCANRESET_TIME (5'b00001), - .RXLPM_CFG (16'h0000), - .RXLPM_GC_CFG (16'h8000), - .RXLPM_KH_CFG0 (16'h0000), - .RXLPM_KH_CFG1 (16'h0002), - .RXLPM_OS_CFG0 (16'h0000), - .RXLPM_OS_CFG1 (16'h8002), + .RXLPM_CFG (16'b0000000000000000), + .RXLPM_GC_CFG (16'b1000000000000000), + .RXLPM_KH_CFG0 (16'b0000000000000000), + .RXLPM_KH_CFG1 (16'b0000000000000010), + .RXLPM_OS_CFG0 (16'b0000000000000000), + .RXLPM_OS_CFG1 (16'b1000000000000010), .RXOOB_CFG (9'b000000110), .RXOOB_CLK_CFG ("PMA"), .RXOSCALRESET_TIME (5'b00011), .RXOUT_DIV (RX_OUT_DIV), .RXPCSRESET_TIME (5'b00011), - .RXPHBEACON_CFG (16'h0000), - .RXPHDLY_CFG (16'h2070), - .RXPHSAMP_CFG (16'h2100), - .RXPHSLIP_CFG (16'h9933), + .RXPHBEACON_CFG (16'b0000000000000000), + .RXPHDLY_CFG (16'b0010000001110000), + .RXPHSAMP_CFG (16'b0010000100000000), + .RXPHSLIP_CFG (16'b1001100100110011), .RXPH_MONITOR_SEL (5'b00000), .RXPI_AUTO_BW_SEL_BYPASS (1'b0), - .RXPI_CFG0 (16'h0002), + .RXPI_CFG0 (16'b0000000000000010), .RXPI_CFG1 (16'b0000000000010101), .RXPI_LPM (1'b0), .RXPI_SEL_LC (2'b00), @@ -1835,7 +1835,7 @@ module util_adxcvr_xch #( .RXSYNC_OVRD (1'b0), .RXSYNC_SKIP_DA (1'b0), .RX_AFE_CM_EN (1'b0), - .RX_BIAS_CFG0 (16'h1554), + .RX_BIAS_CFG0 (16'b0001010101010100), .RX_BUFFER_CFG (6'b000000), .RX_CAPFF_SARC_ENB (1'b0), .RX_CLK25_DIV (RX_CLK25_DIV), @@ -1855,7 +1855,7 @@ module util_adxcvr_xch #( .RX_DFELPM_KLKH_AGC_STUP_EN (1'b1), .RX_DFE_AGC_CFG0 (2'b10), .RX_DFE_AGC_CFG1 (4), - .RX_DFE_KL_LPM_KH_CFG0 (1'h1), + .RX_DFE_KL_LPM_KH_CFG0 (1), .RX_DFE_KL_LPM_KH_CFG1 (4), .RX_DFE_KL_LPM_KL_CFG0 (2'b01), .RX_DFE_KL_LPM_KL_CFG1 (4), @@ -1871,11 +1871,11 @@ module util_adxcvr_xch #( .RX_EYESCAN_VS_RANGE (2'b00), .RX_EYESCAN_VS_UT_SIGN (1'b0), .RX_FABINT_USRCLK_FLOP (1'b0), - .RX_INT_DATAWIDTH (1'h1), + .RX_INT_DATAWIDTH (1), .RX_PMA_POWER_SAVE (1'b0), - .RX_PMA_RSV0 (16'h0000), - .RX_PROGDIV_CFG (0.000000), - .RX_PROGDIV_RATE (16'h0001), + .RX_PMA_RSV0 (16'b0000000000000000), + .RX_PROGDIV_CFG (0.0), + .RX_PROGDIV_RATE (16'b0000000000000001), .RX_RESLOAD_CTRL (4'b0000), .RX_RESLOAD_OVRD (1'b0), .RX_SAMPLE_PERIOD (3'b111), @@ -1906,29 +1906,29 @@ module util_adxcvr_xch #( .SIM_RESET_SPEEDUP ("TRUE"), .SIM_TX_EIDLE_DRIVE_LEVEL ("Z"), .SRSTMODE (1'b0), - .TAPDLY_SET_TX (2'h0), + .TAPDLY_SET_TX (2'b00), .TEMPERATURE_PAR (4'b0010), .TERM_RCAL_CFG (15'b100001000010001), .TERM_RCAL_OVRD (3'b000), - .TRANS_TIME_RATE (8'h0e), - .TST_RSV0 (8'h00), - .TST_RSV1 (8'h00), + .TRANS_TIME_RATE (8'b00001110), + .TST_RSV0 (8'b00000000), + .TST_RSV1 (8'b00000000), .TXBUF_EN ("TRUE"), .TXBUF_RESET_ON_RATE_CHANGE ("TRUE"), - .TXDLY_CFG (16'h8010), - .TXDLY_LCFG (16'h0030), + .TXDLY_CFG (16'b1000000000010000), + .TXDLY_LCFG (16'b0000000000110000), .TXDRVBIAS_N (4'b1010), .TXFIFO_ADDR_CFG ("LOW"), .TXGBOX_FIFO_INIT_RD_ADDR (4), .TXGEARBOX_EN ("FALSE"), .TXOUT_DIV (TX_OUT_DIV), .TXPCSRESET_TIME (5'b00011), - .TXPHDLY_CFG0 (16'h6070), - .TXPHDLY_CFG1 (16'h000f), - .TXPH_CFG (16'h0323), - .TXPH_CFG2 (16'h0000), + .TXPHDLY_CFG0 (16'b0110000001110000), + .TXPHDLY_CFG1 (16'b0000000000001111), + .TXPH_CFG (16'b0000001100100011), + .TXPH_CFG2 (16'b0000000000000000), .TXPH_MONITOR_SEL (5'b00000), - .TXPI_CFG (16'h0054), + .TXPI_CFG (16'b0000000001010100), .TXPI_CFG0 (2'b00), .TXPI_CFG1 (2'b00), .TXPI_CFG2 (2'b00), @@ -1951,7 +1951,7 @@ module util_adxcvr_xch #( .TX_CLK25_DIV (TX_CLK25_DIV), .TX_CLKMUX_EN (1'b1), .TX_DATA_WIDTH (40), - .TX_DCC_LOOP_RST_CFG (16'h0004), + .TX_DCC_LOOP_RST_CFG (16'b0000000000000100), .TX_DEEMPH0 (6'b000000), .TX_DEEMPH1 (6'b000000), .TX_DEEMPH2 (6'b000000), @@ -1964,7 +1964,7 @@ module util_adxcvr_xch #( .TX_FABINT_USRCLK_FLOP (1'b0), .TX_FIFO_BYP_EN (1'b0), .TX_IDLE_DATA_ZERO (1'b0), - .TX_INT_DATAWIDTH (1'h1), + .TX_INT_DATAWIDTH (1), .TX_LOOPBACK_DRIVE_HIZ ("FALSE"), .TX_MAINCURSOR_SEL (1'b0), .TX_MARGIN_FULL_0 (7'b1011111), @@ -1977,20 +1977,20 @@ module util_adxcvr_xch #( .TX_MARGIN_LOW_2 (7'b1000011), .TX_MARGIN_LOW_3 (7'b1000010), .TX_MARGIN_LOW_4 (7'b1000000), - .TX_PHICAL_CFG0 (16'h0000), - .TX_PHICAL_CFG1 (16'h7e00), - .TX_PHICAL_CFG2 (16'h0201), - .TX_PI_BIASSET (1'h1), + .TX_PHICAL_CFG0 (16'b0000000000000000), + .TX_PHICAL_CFG1 (16'b0111111000000000), + .TX_PHICAL_CFG2 (16'b0000001000000001), + .TX_PI_BIASSET (1), .TX_PI_IBIAS_MID (2'b00), .TX_PMADATA_OPT (1'b0), .TX_PMA_POWER_SAVE (1'b0), - .TX_PMA_RSV0 (16'h0008), + .TX_PMA_RSV0 (16'b0000000000001000), .TX_PREDRV_CTRL (2), .TX_PROGCLK_SEL ("PREPI"), - .TX_PROGDIV_CFG (0.000000), - .TX_PROGDIV_RATE (16'h0001), + .TX_PROGDIV_CFG (0.0), + .TX_PROGDIV_RATE (16'b0000000000000001), .TX_QPI_STATUS_EN (1'b0), - .TX_RXDETECT_CFG (14'h0032), + .TX_RXDETECT_CFG (14'b00000000110010), .TX_RXDETECT_REF (4), .TX_SAMPLE_PERIOD (3'b111), .TX_SARC_LPBK_ENB (1'b0), diff --git a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v index 9e8381b5e..aecd42a74 100644 --- a/library/xilinx/util_adxcvr/util_adxcvr_xcm.v +++ b/library/xilinx/util_adxcvr/util_adxcvr_xcm.v @@ -345,69 +345,69 @@ module util_adxcvr_xcm #( .A_SDM1DATA_HIGH (9'b000000000), .A_SDM1DATA_LOW (16'b0000000000000000), .A_SDM1TOGGLE (1'b0), - .BIAS_CFG0 (16'h0000), - .BIAS_CFG1 (16'h0000), - .BIAS_CFG2 (16'h0124), - .BIAS_CFG3 (16'h0041), - .BIAS_CFG4 (16'h0010), - .BIAS_CFG_RSVD (16'h0000), - .COMMON_CFG0 (16'h0000), - .COMMON_CFG1 (16'h0000), - .POR_CFG (16'h0006), - .PPF0_CFG (16'h0600), - .PPF1_CFG (16'h0600), + .BIAS_CFG0 (16'b0000000000000000), + .BIAS_CFG1 (16'b0000000000000000), + .BIAS_CFG2 (16'b0000000100100100), + .BIAS_CFG3 (16'b0000000001000001), + .BIAS_CFG4 (16'b0000000000010000), + .BIAS_CFG_RSVD (16'b0000000000000000), + .COMMON_CFG0 (16'b0000000000000000), + .COMMON_CFG1 (16'b0000000000000000), + .POR_CFG (16'b0000000000000110), + .PPF0_CFG (16'b0000011000000000), + .PPF1_CFG (16'b0000011000000000), .QPLL0CLKOUT_RATE ("HALF"), - .QPLL0_CFG0 (16'h331c), - .QPLL0_CFG1 (16'hd038), - .QPLL0_CFG1_G3 (16'hd038), - .QPLL0_CFG2 (16'h0fc0), - .QPLL0_CFG2_G3 (16'h0fc0), - .QPLL0_CFG3 (16'h0120), - .QPLL0_CFG4 (16'h0003), + .QPLL0_CFG0 (16'b0011001100011100), + .QPLL0_CFG1 (16'b1101000000111000), + .QPLL0_CFG1_G3 (16'b1101000000111000), + .QPLL0_CFG2 (16'b0000111111000000), + .QPLL0_CFG2_G3 (16'b0000111111000000), + .QPLL0_CFG3 (16'b0000000100100000), + .QPLL0_CFG4 (16'b0000000000000011), .QPLL0_CP (10'b0001111111), .QPLL0_CP_G3 (10'b0000011111), .QPLL0_FBDIV (QPLL_FBDIV), .QPLL0_FBDIV_G3 (160), - .QPLL0_INIT_CFG0 (16'h02b2), - .QPLL0_INIT_CFG1 (8'h00), - .QPLL0_LOCK_CFG (16'h25e8), - .QPLL0_LOCK_CFG_G3 (16'h25e8), + .QPLL0_INIT_CFG0 (16'b0000001010110010), + .QPLL0_INIT_CFG1 (8'b00000000), + .QPLL0_LOCK_CFG (16'b0010010111101000), + .QPLL0_LOCK_CFG_G3 (16'b0010010111101000), .QPLL0_LPF (10'b0100110111), .QPLL0_LPF_G3 (10'b0111010101), .QPLL0_PCI_EN (1'b0), .QPLL0_RATE_SW_USE_DRP (1'b1), .QPLL0_REFCLK_DIV (QPLL_REFCLK_DIV), - .QPLL0_SDM_CFG0 (16'h0080), - .QPLL0_SDM_CFG1 (16'h0000), - .QPLL0_SDM_CFG2 (16'h0000), + .QPLL0_SDM_CFG0 (16'b0000000010000000), + .QPLL0_SDM_CFG1 (16'b0000000000000000), + .QPLL0_SDM_CFG2 (16'b0000000000000000), .QPLL1CLKOUT_RATE ("HALF"), - .QPLL1_CFG0 (16'h331c), - .QPLL1_CFG1 (16'hd038), - .QPLL1_CFG1_G3 (16'hd038), - .QPLL1_CFG2 (16'h0fc0), - .QPLL1_CFG2_G3 (16'h0fc0), - .QPLL1_CFG3 (16'h0120), - .QPLL1_CFG4 (16'h0003), + .QPLL1_CFG0 (16'b0011001100011100), + .QPLL1_CFG1 (16'b1101000000111000), + .QPLL1_CFG1_G3 (16'b1101000000111000), + .QPLL1_CFG2 (16'b0000111111000000), + .QPLL1_CFG2_G3 (16'b0000111111000000), + .QPLL1_CFG3 (16'b0000000100100000), + .QPLL1_CFG4 (16'b0000000000000011), .QPLL1_CP (10'b1111111111), .QPLL1_CP_G3 (10'b0011111111), .QPLL1_FBDIV (QPLL_FBDIV), .QPLL1_FBDIV_G3 (80), - .QPLL1_INIT_CFG0 (16'h02b2), - .QPLL1_INIT_CFG1 (8'h00), - .QPLL1_LOCK_CFG (16'h25e8), - .QPLL1_LOCK_CFG_G3 (16'h25e8), + .QPLL1_INIT_CFG0 (16'b0000001010110010), + .QPLL1_INIT_CFG1 (8'b00000000), + .QPLL1_LOCK_CFG (16'b0010010111101000), + .QPLL1_LOCK_CFG_G3 (16'b0010010111101000), .QPLL1_LPF (10'b0100110101), .QPLL1_LPF_G3 (10'b0111010100), .QPLL1_PCI_EN (1'b0), .QPLL1_RATE_SW_USE_DRP (1'b1), .QPLL1_REFCLK_DIV (QPLL_REFCLK_DIV), - .QPLL1_SDM_CFG0 (16'h0080), - .QPLL1_SDM_CFG1 (16'h0000), - .QPLL1_SDM_CFG2 (16'h0000), - .RSVD_ATTR0 (16'h0000), - .RSVD_ATTR1 (16'h0000), - .RSVD_ATTR2 (16'h0000), - .RSVD_ATTR3 (16'h0000), + .QPLL1_SDM_CFG0 (16'b0000000010000000), + .QPLL1_SDM_CFG1 (16'b0000000000000000), + .QPLL1_SDM_CFG2 (16'b0000000000000000), + .RSVD_ATTR0 (16'b0000000000000000), + .RSVD_ATTR1 (16'b0000000000000000), + .RSVD_ATTR2 (16'b0000000000000000), + .RSVD_ATTR3 (16'b0000000000000000), .RXRECCLKOUT0_SEL (2'b00), .RXRECCLKOUT1_SEL (2'b00), .SARC_ENB (1'b0),