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axi_ad9361: ad_pps_receiver integration 

The ad_pps_receiver is instantiated at the top of core.
The rcounter is placed into adc/dac_common registers space, at the
address 0x30 (word aligned).
The interrupt mask is placed into adc/dac_common, at the address 0x04
(word aligned). Because the core has an instance of both modules, the
interrupt masks are OR-ed together.
main
Istvan Csomortani 2017-07-28 07:57:13 +01:00
parent c7304922d5
commit 8ffc35735a
8 changed files with 61 additions and 0 deletions
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1
library/axi_ad9361/Makefile
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@ -15,6 +15,7 @@ M_DEPS += ../common/ad_iqcor.v
M_DEPS += ../common/ad_pnmon.v
M_DEPS += ../common/ad_rst.v
M_DEPS += ../common/ad_tdd_control.v
M_DEPS += ../common/ad_pps_receiver.v
M_DEPS += ../common/up_adc_channel.v
M_DEPS += ../common/up_adc_common.v
M_DEPS += ../common/up_axi.v

24
library/axi_ad9361/axi_ad9361.v
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@ -103,6 +103,9 @@ module axi_ad9361 #(
input tdd_sync,
output tdd_sync_cntr,
input gps_pps,
output gps_pps_irq,
// delay clock
input delay_clk,
@ -280,6 +283,11 @@ module axi_ad9361 #(
wire up_drp_ready;
wire up_drp_locked;
wire [31:0] up_pps_rcounter_s;
wire up_irq_mask_s;
wire adc_up_pps_irq_mask_s;
wire dac_up_pps_irq_mask_s;
// signal name changes
assign up_clk = s_axi_aclk;
@ -527,6 +535,18 @@ module axi_ad9361 #(
end
endgenerate
// GPS's 1PPS receiver
ad_pps_receiver i_pps_receiver (
.clk (clk),
.rst (rst),
.gps_pps (gps_pps),
.up_clk (up_clk),
.up_rstn (up_rstn),
.up_pps_rcounter (up_pps_rcounter_s),
.up_irq_mask (up_irq_mask_s),
.up_irq (gps_pps_irq));
assign up_irq_mask_s = adc_up_pps_irq_mask_s | dac_up_pps_irq_mask_s;
// receive
axi_ad9361_rx #(
@ -569,6 +589,8 @@ module axi_ad9361 #(
.adc_dunf (adc_dunf),
.up_adc_gpio_in (up_adc_gpio_in),
.up_adc_gpio_out (up_adc_gpio_out),
.up_pps_rcounter(up_pps_rcounter_s),
.up_pps_irq_mask (adc_up_pps_irq_mask_s),
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_wreq (up_wreq_s),
@ -626,6 +648,8 @@ module axi_ad9361 #(
.dac_data_q1 (dac_data_q1),
.dac_dovf(dac_dovf),
.dac_dunf(dac_dunf),
.up_pps_rcounter(up_pps_rcounter_s),
.up_pps_irq_mask (dac_up_pps_irq_mask_s),
.up_dac_gpio_in (up_dac_gpio_in),
.up_dac_gpio_out (up_dac_gpio_out),
.up_rstn (up_rstn),

6
library/axi_ad9361/axi_ad9361_constr.xdc
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@ -8,3 +8,9 @@ set_false_path -from [get_cells -hier -filter {name =~ *up_enable_int_reg && I
set_false_path -from [get_cells -hier -filter {name =~ *up_txnrx_int_reg && IS_SEQUENTIAL}] -to [get_cells -hier -filter {name =~ *txnrx_up_m1_reg && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *tdd_sync_d1_reg && IS_SEQUENTIAL}]
set_property ASYNC_REG TRUE \
[get_cells -hier *_pps_m*]
set_false_path -to [get_cells -hier -filter {name =~ *_pps_m_reg[0] && IS_SEQUENTIAL}]
set_false_path -to [get_cells -hier -filter {name =~ *up_pps_rcounter_reg* && IS_SEQUENTIAL}]

1
library/axi_ad9361/axi_ad9361_ip.tcl
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@ -19,6 +19,7 @@ adi_ip_files axi_ad9361 [list \
"$ad_hdl_dir/library/common/ad_iqcor.v" \
"$ad_hdl_dir/library/common/ad_addsub.v" \
"$ad_hdl_dir/library/common/ad_tdd_control.v" \
"$ad_hdl_dir/library/common/ad_pps_receiver.v" \
"$ad_hdl_dir/library/common/up_axi.v" \
"$ad_hdl_dir/library/common/up_xfer_cntrl.v" \
"$ad_hdl_dir/library/common/up_xfer_status.v" \

7
library/axi_ad9361/axi_ad9361_rx.v
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@ -94,6 +94,11 @@ module axi_ad9361_rx #(
input [31:0] up_adc_gpio_in,
output [31:0] up_adc_gpio_out,
// 1PPS reporting counter and interrupt
input [31:0] up_pps_rcounter,
output up_pps_irq_mask,
// processor interface
input up_rstn,
@ -343,6 +348,8 @@ module axi_ad9361_rx #(
.adc_sref_sync (),
.adc_sync (),
.up_adc_ce (),
.up_pps_rcounter (up_pps_rcounter),
.up_pps_irq_mask (up_pps_irq_mask),
.up_status_pn_err (up_status_pn_err),
.up_status_pn_oos (up_status_pn_oos),
.up_status_or (up_status_or),

7
library/axi_ad9361/axi_ad9361_tx.v
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@ -92,6 +92,11 @@ module axi_ad9361_tx #(
input [31:0] up_dac_gpio_in,
output [31:0] up_dac_gpio_out,
// 1PPS reporting counter and interrupt
input [31:0] up_pps_rcounter,
output up_pps_irq_mask,
// processor interface
input up_rstn,
@ -345,6 +350,8 @@ module axi_ad9361_tx #(
.dac_status_unf (dac_dunf),
.dac_clk_ratio (32'd1),
.up_dac_ce (),
.up_pps_rcounter (up_pps_rcounter),
.up_pps_irq_mask (up_pps_irq_mask),
.up_drp_sel (),
.up_drp_wr (),
.up_drp_addr (),

8
library/common/up_adc_common.v
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@ -66,6 +66,8 @@ module up_adc_common #(
output [31:0] adc_start_code,
output adc_sref_sync,
output adc_sync,
input [31:0] up_pps_rcounter,
output reg up_pps_irq_mask,
// channel interface
@ -174,6 +176,7 @@ module up_adc_common #(
up_adc_r1_mode <= 'd0;
up_adc_ddr_edgesel <= 'd0;
up_adc_pin_mode <= 'd0;
up_pps_irq_mask <= 1'b1;
end else begin
up_adc_clk_enb_int <= ~up_adc_clk_enb;
up_core_preset <= ~up_resetn;
@ -182,6 +185,9 @@ module up_adc_common #(
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_pps_irq_mask <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_adc_clk_enb <= up_wdata[2];
up_mmcm_resetn <= up_wdata[1];
@ -350,6 +356,7 @@ module up_adc_common #(
8'h01: up_rdata_int <= ID;
8'h02: up_rdata_int <= up_scratch;
8'h03: up_rdata_int <= CONFIG;
8'h04: up_rdata_int <= {31'b0, up_pps_irq_mask};
8'h10: up_rdata_int <= {29'd0, up_adc_clk_enb, up_mmcm_resetn, up_resetn};
8'h11: up_rdata_int <= {27'd0, up_adc_sref_sync, up_adc_sync, up_adc_r1_mode,
up_adc_ddr_edgesel, up_adc_pin_mode};
@ -367,6 +374,7 @@ module up_adc_common #(
8'h29: up_rdata_int <= up_adc_start_code;
8'h2e: up_rdata_int <= up_adc_gpio_in;
8'h2f: up_rdata_int <= up_adc_gpio_out_int;
8'h30: up_rdata_int <= up_pps_rcounter;
default: up_rdata_int <= 0;
endcase
end else begin

7
library/common/up_dac_common.v
View File

@ -67,6 +67,8 @@ module up_dac_common #(
input dac_status_unf,
input [31:0] dac_clk_ratio,
output up_dac_ce,
input [31:0] up_pps_rcounter,
output reg up_pps_irq_mask,
// drp interface
@ -182,6 +184,7 @@ module up_dac_common #(
up_dac_datarate <= 'd0;
up_dac_frame <= 'd0;
up_dac_clksel <= 'd0;
up_pps_irq_mask <= 1'b1;
end else begin
up_dac_clk_enb_int <= ~up_dac_clk_enb;
up_core_preset <= ~up_resetn;
@ -190,6 +193,9 @@ module up_dac_common #(
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h02)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h04)) begin
up_pps_irq_mask <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[7:0] == 8'h10)) begin
up_dac_clk_enb <= up_wdata[2];
up_mmcm_resetn <= up_wdata[1];
@ -371,6 +377,7 @@ module up_dac_common #(
8'h28: up_rdata_int <= {24'd0, dac_usr_chanmax};
8'h2e: up_rdata_int <= up_dac_gpio_in;
8'h2f: up_rdata_int <= up_dac_gpio_out_int;
8'h30: up_rdata_int <= up_pps_rcounter;
default: up_rdata_int <= 0;
endcase
end else begin