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fifo: removed

main
Rejeesh Kutty 2015-04-07 15:52:31 -04:00
parent 86a70b3054
commit 9098e3ebca
4 changed files with 0 additions and 605 deletions
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156
library/axi_fifo/address_gray.v
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@ -1,156 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <lars@metafoo.de>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module fifo_address_gray (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
reg [C_ADDRESS_WIDTH:0] s_axis_waddr_gray = 'h00;
wire [C_ADDRESS_WIDTH:0] s_axis_waddr_gray_next;
wire [C_ADDRESS_WIDTH:0] s_axis_raddr_gray;
reg [C_ADDRESS_WIDTH:0] m_axis_raddr_gray = 'h00;
wire [C_ADDRESS_WIDTH:0] m_axis_raddr_gray_next;
wire [C_ADDRESS_WIDTH:0] m_axis_waddr_gray;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
assign s_axis_waddr_gray_next = _s_axis_waddr_next ^ _s_axis_waddr_next[C_ADDRESS_WIDTH:1];
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
s_axis_waddr_gray <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
s_axis_waddr_gray <= s_axis_waddr_gray_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
assign m_axis_raddr_gray_next = _m_axis_raddr_next ^ _m_axis_raddr_next[C_ADDRESS_WIDTH:1];
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
m_axis_raddr_gray <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
m_axis_raddr_gray <= m_axis_raddr_gray_next;
end
end
sync_bits #(
.NUM_BITS(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(s_axis_waddr_gray),
.out(m_axis_waddr_gray)
);
sync_bits #(
.NUM_BITS(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(m_axis_raddr_gray),
.out(s_axis_raddr_gray)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (s_axis_raddr_gray[C_ADDRESS_WIDTH] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH] ||
s_axis_raddr_gray[C_ADDRESS_WIDTH-1] == s_axis_waddr_gray_next[C_ADDRESS_WIDTH-1] ||
s_axis_raddr_gray[C_ADDRESS_WIDTH-2:0] != s_axis_waddr_gray_next[C_ADDRESS_WIDTH-2:0]);
s_axis_empty <= s_axis_raddr_gray == s_axis_waddr_gray_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= m_axis_waddr_gray != m_axis_raddr_gray_next;
end
end
endmodule

147
library/axi_fifo/address_gray_pipelined.v
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// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <lars@metafoo.de>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module fifo_address_gray_pipelined (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output reg m_axis_valid,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
output [C_ADDRESS_WIDTH-1:0] m_axis_raddr,
input s_axis_aclk,
input s_axis_aresetn,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _s_axis_waddr_next;
wire [C_ADDRESS_WIDTH:0] _s_axis_raddr;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr = 'h00;
reg [C_ADDRESS_WIDTH:0] _m_axis_raddr_next;
wire [C_ADDRESS_WIDTH:0] _m_axis_waddr;
assign s_axis_waddr = _s_axis_waddr[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr_next = _m_axis_raddr_next[C_ADDRESS_WIDTH-1:0];
assign m_axis_raddr = _m_axis_raddr[C_ADDRESS_WIDTH-1:0];
always @(*)
begin
if (s_axis_ready && s_axis_valid)
_s_axis_waddr_next <= _s_axis_waddr + 1;
else
_s_axis_waddr_next <= _s_axis_waddr;
end
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
_s_axis_waddr <= 'h00;
end else begin
_s_axis_waddr <= _s_axis_waddr_next;
end
end
always @(*)
begin
if (m_axis_ready && m_axis_valid)
_m_axis_raddr_next <= _m_axis_raddr + 1;
else
_m_axis_raddr_next <= _m_axis_raddr;
end
always @(posedge m_axis_aclk)
begin
if (m_axis_aresetn == 1'b0) begin
_m_axis_raddr <= 'h00;
end else begin
_m_axis_raddr <= _m_axis_raddr_next;
end
end
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_waddr_sync (
.in_clk(s_axis_aclk),
.in_resetn(s_axis_aresetn),
.out_clk(m_axis_aclk),
.out_resetn(m_axis_aresetn),
.in_count(_s_axis_waddr),
.out_count(_m_axis_waddr)
);
sync_gray #(
.DATA_WIDTH(C_ADDRESS_WIDTH + 1)
) i_raddr_sync (
.in_clk(m_axis_aclk),
.in_resetn(m_axis_aresetn),
.out_clk(s_axis_aclk),
.out_resetn(s_axis_aresetn),
.in_count(_m_axis_raddr),
.out_count(_s_axis_raddr)
);
always @(posedge s_axis_aclk)
begin
if (s_axis_aresetn == 1'b0) begin
s_axis_ready <= 1'b1;
s_axis_empty <= 1'b1;
end else begin
s_axis_ready <= (_s_axis_raddr[C_ADDRESS_WIDTH] == _s_axis_waddr_next[C_ADDRESS_WIDTH] ||
_s_axis_raddr[C_ADDRESS_WIDTH-1:0] != _s_axis_waddr_next[C_ADDRESS_WIDTH-1:0]);
s_axis_empty <= _s_axis_raddr == _s_axis_waddr_next;
end
end
always @(posedge m_axis_aclk)
begin
if (s_axis_aresetn == 1'b0)
m_axis_valid <= 1'b0;
else begin
m_axis_valid <= _m_axis_waddr != _m_axis_raddr_next;
end
end
endmodule

106
library/axi_fifo/address_sync.v
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@ -1,106 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <lars@metafoo.de>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module fifo_address_sync (
input clk,
input resetn,
input m_axis_ready,
output reg m_axis_valid,
output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr,
output reg [C_ADDRESS_WIDTH-1:0] m_axis_raddr_next,
output reg s_axis_ready,
input s_axis_valid,
output reg s_axis_empty,
output reg [C_ADDRESS_WIDTH-1:0] s_axis_waddr
);
parameter C_ADDRESS_WIDTH = 4;
reg [C_ADDRESS_WIDTH:0] level;
reg [C_ADDRESS_WIDTH:0] level_next;
wire read = m_axis_ready & m_axis_valid;
wire write = s_axis_ready & s_axis_valid;
always @(*)
begin
if (read)
m_axis_raddr_next <= m_axis_raddr + 1'b1;
else
m_axis_raddr_next <= m_axis_raddr;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
s_axis_waddr <= 'h00;
m_axis_raddr <= 'h00;
end else begin
if (write)
s_axis_waddr <= s_axis_waddr + 1'b1;
m_axis_raddr <= m_axis_raddr_next;
end
end
always @(*)
begin
if (read & ~write)
level_next <= level - 1'b1;
else if (~read & write)
level_next <= level + 1'b1;
else
level_next <= level;
end
always @(posedge clk)
begin
if (resetn == 1'b0) begin
m_axis_valid <= 1'b0;
s_axis_ready <= 1'b0;
end else begin
level <= level_next;
m_axis_valid <= level_next != 0;
s_axis_ready <= level_next != 2**C_ADDRESS_WIDTH;
s_axis_empty <= level_next == 0;
end
end
endmodule

196
library/axi_fifo/axi_fifo.v
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@ -1,196 +0,0 @@
// ***************************************************************************
// ***************************************************************************
// Copyright 2013(c) Analog Devices, Inc.
// Author: Lars-Peter Clausen <lars@metafoo.de>
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
module axi_fifo (
input m_axis_aclk,
input m_axis_aresetn,
input m_axis_ready,
output m_axis_valid,
output [C_DATA_WIDTH-1:0] m_axis_data,
input s_axis_aclk,
input s_axis_aresetn,
output s_axis_ready,
input s_axis_valid,
input [C_DATA_WIDTH-1:0] s_axis_data,
output s_axis_empty
);
parameter C_DATA_WIDTH = 64;
parameter C_CLKS_ASYNC = 1;
parameter C_ADDRESS_WIDTH = 4;
generate if (C_ADDRESS_WIDTH == 0) begin
reg [C_DATA_WIDTH-1:0] ram;
reg s_axis_waddr = 1'b0;
reg m_axis_raddr = 1'b0;
wire m_axis_waddr;
wire s_axis_raddr;
sync_bits #(
.NUM_BITS(1),
.CLK_ASYNC(C_CLKS_ASYNC)
) i_waddr_sync (
.out_clk(m_axis_aclk),
.out_resetn(s_axis_aresetn),
.in(s_axis_waddr),
.out(m_axis_waddr)
);
sync_bits #(
.NUM_BITS(1),
.CLK_ASYNC(C_CLKS_ASYNC)
) i_raddr_sync (
.out_clk(s_axis_aclk),
.out_resetn(m_axis_aresetn),
.in(m_axis_raddr),
.out(s_axis_raddr)
);
assign m_axis_valid = m_axis_raddr != m_axis_waddr;
assign s_axis_ready = s_axis_raddr == s_axis_waddr;
assign s_axis_empty = s_axis_raddr == s_axis_waddr;
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
ram <= s_axis_data;
end
always @(posedge s_axis_aclk) begin
if (s_axis_aresetn == 1'b0) begin
s_axis_waddr <= 1'b0;
end else begin
if (s_axis_ready & s_axis_valid) begin
s_axis_waddr <= s_axis_waddr + 1'b1;
end
end
end
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
m_axis_raddr <= 1'b0;
end else begin
if (m_axis_valid & m_axis_ready)
m_axis_raddr <= m_axis_raddr + 1'b1;
end
end
assign m_axis_data = ram;
end else begin
reg [C_DATA_WIDTH-1:0] ram[0:2**C_ADDRESS_WIDTH-1];
wire [C_ADDRESS_WIDTH-1:0] s_axis_waddr;
wire [C_ADDRESS_WIDTH-1:0] m_axis_raddr;
wire _m_axis_ready;
wire _m_axis_valid;
if (C_CLKS_ASYNC == 1) begin
fifo_address_gray_pipelined #(
.C_ADDRESS_WIDTH(C_ADDRESS_WIDTH)
) i_address_gray (
.m_axis_aclk(m_axis_aclk),
.m_axis_aresetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.s_axis_aclk(s_axis_aclk),
.s_axis_aresetn(s_axis_aresetn),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr)
);
end else begin
fifo_address_sync #(
.C_ADDRESS_WIDTH(C_ADDRESS_WIDTH)
) i_address_sync (
.clk(m_axis_aclk),
.resetn(m_axis_aresetn),
.m_axis_ready(_m_axis_ready),
.m_axis_valid(_m_axis_valid),
.m_axis_raddr(m_axis_raddr),
.s_axis_ready(s_axis_ready),
.s_axis_valid(s_axis_valid),
.s_axis_empty(s_axis_empty),
.s_axis_waddr(s_axis_waddr)
);
end
always @(posedge s_axis_aclk) begin
if (s_axis_ready)
ram[s_axis_waddr] <= s_axis_data;
end
reg [C_DATA_WIDTH-1:0] data;
reg valid;
always @(posedge m_axis_aclk) begin
if (m_axis_aresetn == 1'b0) begin
valid <= 1'b0;
end else begin
if (_m_axis_valid)
valid <= 1'b1;
else if (m_axis_ready)
valid <= 1'b0;
end
end
always @(posedge m_axis_aclk) begin
if (~valid || m_axis_ready)
data <= ram[m_axis_raddr];
end
assign _m_axis_ready = ~valid || m_axis_ready;
assign m_axis_data = data;
assign m_axis_valid = valid;
end endgenerate
endmodule