From 915fe036f20cab4cade35d5b9ed2f3e25e4089b0 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 7 Aug 2017 11:19:57 +0300 Subject: [PATCH] util_axis_resize: Coding style updates + update to verilog-2001 coding standard + define RATIO outside the generate block + $clog2 macro is not supported by some tools, define function locally --- library/util_axis_resize/util_axis_resize.v | 30 ++++++++++++++------- 1 file changed, 20 insertions(+), 10 deletions(-) diff --git a/library/util_axis_resize/util_axis_resize.v b/library/util_axis_resize/util_axis_resize.v index 546c56221..e744eee88 100644 --- a/library/util_axis_resize/util_axis_resize.v +++ b/library/util_axis_resize/util_axis_resize.v @@ -33,7 +33,12 @@ // *************************************************************************** // *************************************************************************** -module util_axis_resize ( +module util_axis_resize # ( + + parameter MASTER_DATA_WIDTH = 64, + parameter SLAVE_DATA_WIDTH = 64, + parameter BIG_ENDIAN = 0)( + input clk, input resetn, @@ -46,9 +51,18 @@ module util_axis_resize ( output [MASTER_DATA_WIDTH-1:0] m_data ); -parameter MASTER_DATA_WIDTH = 64; -parameter SLAVE_DATA_WIDTH = 64; -parameter BIG_ENDIAN = 0; +localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ? + MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH : + SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH; + +function integer clog2; + input integer value; + begin + value = value-1; + for (clog2=0; value>0; clog2=clog2+1) + value = value>>1; + end +endfunction generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin @@ -58,10 +72,8 @@ assign m_data = s_data; end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin -localparam RATIO = MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH; - reg [MASTER_DATA_WIDTH-1:0] data; -reg [$clog2(RATIO)-1:0] count; +reg [clog2(RATIO)-1:0] count; reg valid; always @(posedge clk) @@ -100,10 +112,8 @@ assign m_data = data; end else begin -localparam RATIO = SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH; - reg [SLAVE_DATA_WIDTH-1:0] data; -reg [$clog2(RATIO)-1:0] count; +reg [clog2(RATIO)-1:0] count; reg valid; always @(posedge clk)