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util_axis_resize: Coding style updates 

+ update to verilog-2001 coding standard
  + define RATIO outside the generate block
  + $clog2 macro is not supported by some tools, define function
locally
main
Istvan Csomortani 2017-08-07 11:19:57 +03:00
parent d0503536a8
commit 915fe036f2
1 changed files with 20 additions and 10 deletions
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30
library/util_axis_resize/util_axis_resize.v
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@ -33,7 +33,12 @@
// *************************************************************************** // ***************************************************************************
// *************************************************************************** // ***************************************************************************
module util_axis_resize ( module util_axis_resize # (
parameter MASTER_DATA_WIDTH = 64,
parameter SLAVE_DATA_WIDTH = 64,
parameter BIG_ENDIAN = 0)(
input clk, input clk,
input resetn, input resetn,
@ -46,9 +51,18 @@ module util_axis_resize (
output [MASTER_DATA_WIDTH-1:0] m_data output [MASTER_DATA_WIDTH-1:0] m_data
); );
parameter MASTER_DATA_WIDTH = 64; localparam RATIO = (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) ?
parameter SLAVE_DATA_WIDTH = 64; MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH :
parameter BIG_ENDIAN = 0; SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH;
function integer clog2;
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin generate if (SLAVE_DATA_WIDTH == MASTER_DATA_WIDTH) begin
@ -58,10 +72,8 @@ assign m_data = s_data;
end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin end else if (SLAVE_DATA_WIDTH < MASTER_DATA_WIDTH) begin
localparam RATIO = MASTER_DATA_WIDTH / SLAVE_DATA_WIDTH;
reg [MASTER_DATA_WIDTH-1:0] data; reg [MASTER_DATA_WIDTH-1:0] data;
reg [$clog2(RATIO)-1:0] count; reg [clog2(RATIO)-1:0] count;
reg valid; reg valid;
always @(posedge clk) always @(posedge clk)
@ -100,10 +112,8 @@ assign m_data = data;
end else begin end else begin
localparam RATIO = SLAVE_DATA_WIDTH / MASTER_DATA_WIDTH;
reg [SLAVE_DATA_WIDTH-1:0] data; reg [SLAVE_DATA_WIDTH-1:0] data;
reg [$clog2(RATIO)-1:0] count; reg [clog2(RATIO)-1:0] count;
reg valid; reg valid;
always @(posedge clk) always @(posedge clk)