From 9169e20b5ea6b673a9d65146e7d405a731c49d2f Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Wed, 6 Jul 2016 09:16:18 +0300 Subject: [PATCH] daq1: Fix the data width on the DMAC interfaces + HP ports maximum width is 64 bits + DMAC's default width is 64, no need for redefinition --- projects/daq1/common/daq1_bd.tcl | 3 --- 1 file changed, 3 deletions(-) diff --git a/projects/daq1/common/daq1_bd.tcl b/projects/daq1/common/daq1_bd.tcl index 74b8ad4f9..350d0b17e 100644 --- a/projects/daq1/common/daq1_bd.tcl +++ b/projects/daq1/common/daq1_bd.tcl @@ -34,7 +34,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9122_dma set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9122_dma set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9122_dma set_property -dict [list CONFIG.CYCLIC {1}] $axi_ad9122_dma -set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {128}] $axi_ad9122_dma set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {128}] $axi_ad9122_dma set util_upack_ad9122 [create_bd_cell -type ip -vlnv analog.com:user:util_upack:1.0 util_upack_ad9122] @@ -55,8 +54,6 @@ set_property -dict [list CONFIG.AXI_SLICE_DEST {0}] $axi_ad9684_dma set_property -dict [list CONFIG.DMA_LENGTH_WIDTH {24}] $axi_ad9684_dma set_property -dict [list CONFIG.DMA_2D_TRANSFER {0}] $axi_ad9684_dma set_property -dict [list CONFIG.CYCLIC {0}] $axi_ad9684_dma -set_property -dict [list CONFIG.DMA_DATA_WIDTH_SRC {64}] $axi_ad9684_dma -set_property -dict [list CONFIG.DMA_DATA_WIDTH_DEST {64}] $axi_ad9684_dma set util_cpack_ad9684 [create_bd_cell -type ip -vlnv analog.com:user:util_cpack:1.0 util_cpack_ad9684] set_property -dict [list CONFIG.CHANNEL_DATA_WIDTH {32}] $util_cpack_ad9684