From 9180d4dd391853ebd9a4e0a88db1faa9a8fcd562 Mon Sep 17 00:00:00 2001
From: Laszlo Nagy <laszlo.nagy@analog.com>
Date: Tue, 7 Jan 2020 08:14:41 +0000
Subject: [PATCH] library/axi_clkgen: Fix second clock output

A typo prevents the usage of second clock output.
---
 library/axi_clkgen/bd/bd.tcl | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/library/axi_clkgen/bd/bd.tcl b/library/axi_clkgen/bd/bd.tcl
index 5e3f5a91a..bb8b8d92d 100644
--- a/library/axi_clkgen/bd/bd.tcl
+++ b/library/axi_clkgen/bd/bd.tcl
@@ -137,7 +137,7 @@ proc propagate {cellpath otherinfo} {
     set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
 
     if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
-      set clk0_out [get_bd_pins "$ip/clk_1"]
+      set clk1_out [get_bd_pins "$ip/clk_1"]
       set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
       set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
     }