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library/axi_clkgen: Fix second clock output 

A typo prevents the usage of second clock output.
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Laszlo Nagy 2020-01-07 08:14:41 +00:00 committed by Laszlo Nagy
parent 8db77d8f3a
commit 9180d4dd39
1 changed files with 1 additions and 1 deletions
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2
library/axi_clkgen/bd/bd.tcl
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@ -137,7 +137,7 @@ proc propagate {cellpath otherinfo} {
set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out set_property CONFIG.FREQ_HZ $clk0_out_freq $clk0_out
if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} { if {[get_property "CONFIG.ENABLE_CLKOUT1" $ip] == "true"} {
set clk0_out [get_bd_pins "$ip/clk_1"] set clk1_out [get_bd_pins "$ip/clk_1"]
set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)] set clk1_out_freq [expr ($clk_freq + 0.0) * $vco_mul / ($vco_div * $clk1_div)]
set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out set_property CONFIG.FREQ_HZ $clk1_out_freq $clk1_out
} }