axi_intr_monitor: Initial commit
Adrian Costina
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f03675cdab
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91ee4394e4
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2014(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// IP used to monitor interrupt handling latency for a system.
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// Control register, bit 0 enables the core. If it's set to 0, the interrupt
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// won't be activated and all counters will be reset to 0
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// ***************************************************************************
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`timescale 1ns/100ps
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module axi_intr_monitor
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(
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output irq,
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// axi interface
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input s_axi_aclk,
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input s_axi_aresetn,
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input s_axi_awvalid,
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input [31:0] s_axi_awaddr,
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output s_axi_awready,
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input s_axi_wvalid,
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input [31:0] s_axi_wdata,
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input [3:0] s_axi_wstrb,
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output s_axi_wready,
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output s_axi_bvalid,
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output [1:0] s_axi_bresp,
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input s_axi_bready,
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input s_axi_arvalid,
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input [31:0] s_axi_araddr,
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output s_axi_arready,
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output s_axi_rvalid,
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output [1:0] s_axi_rresp,
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output [31:0] s_axi_rdata,
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input s_axi_rready,
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input [ 2:0] s_axi_awprot,
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input [ 2:0] s_axi_arprot
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);
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parameter VERSION = 32'h00010000;
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//------------------------------------------------------------------------------
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//----------- Registers Declarations -------------------------------------------
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//------------------------------------------------------------------------------
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reg [31:0] up_rdata = 'd0;
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reg up_wack = 'd0;
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reg up_rack = 'd0;
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reg pwm_gen_clk = 'd0;
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reg [31:0] scratch = 'd0;
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reg [31:0] control = 'd0;
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reg interrupt = 'd0;
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reg [31:0] counter_to_interrupt = 'd0;
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reg [31:0] counter_to_interrupt_cnt = 'd0;
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reg [31:0] counter_from_interrupt = 'd0;
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reg [31:0] counter_interrupt_handling = 'd0;
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reg [31:0] min_interrupt_handling = 'd0;
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reg [31:0] max_interrupt_handling = 'd0;
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reg interrupt_d1 = 'd0;
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//------------------------------------------------------------------------------
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//----------- Wires Declarations -----------------------------------------------
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//------------------------------------------------------------------------------
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wire up_rreq_s;
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wire up_wreq_s;
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wire [13:0] up_raddr_s;
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wire [13:0] up_waddr_s;
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wire [31:0] up_wdata_s;
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//------------------------------------------------------------------------------
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//----------- Assign/Always Blocks ---------------------------------------------
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//------------------------------------------------------------------------------
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assign irq = interrupt & control[0];
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always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
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if (s_axi_aresetn == 1'b0 || control[0] == 1'b0) begin
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counter_to_interrupt_cnt <= 0;
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counter_interrupt_handling <= 'd0;
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counter_from_interrupt <= 32'h0;
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min_interrupt_handling <= 'd0;
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max_interrupt_handling <= 'd0;
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interrupt_d1 <= 0;
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end else begin
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interrupt_d1 <= irq;
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if (irq == 1'b1) begin
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counter_to_interrupt_cnt <= counter_to_interrupt;
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end else if (counter_to_interrupt_cnt > 0) begin
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counter_to_interrupt_cnt <= counter_to_interrupt_cnt - 1;
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end
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if (irq == 1'b0 && interrupt_d1 == 1'b1) begin
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counter_from_interrupt <= 32'h0;
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counter_interrupt_handling <= counter_from_interrupt;
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if (min_interrupt_handling > counter_from_interrupt) begin
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min_interrupt_handling <= counter_from_interrupt;
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end
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if (max_interrupt_handling < counter_from_interrupt) begin
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max_interrupt_handling <= counter_from_interrupt;
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end
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end else begin
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counter_from_interrupt <= counter_from_interrupt + 1;
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end
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end
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end
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always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
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if (s_axi_aresetn == 0) begin
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up_wack <= 1'b0;
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scratch <= 'd0;
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control <= 'd0;
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interrupt <= 'd0;
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counter_to_interrupt <= 'd0;
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end else begin
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up_wack <= up_wreq_s;
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if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h1)) begin
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scratch <= up_wdata_s;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h2)) begin
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control <= up_wdata_s;
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h3)) begin
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interrupt <= interrupt & ~up_wdata_s[0];
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end else begin
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if (counter_to_interrupt_cnt == 32'h0 && control[0] == 1'b1) begin
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interrupt <= 1'b1;
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr_s[3:0] == 4'h4)) begin
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counter_to_interrupt <= up_wdata_s;
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end
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end
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end
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always @(negedge s_axi_aresetn or posedge s_axi_aclk) begin
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if (s_axi_aresetn == 0) begin
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up_rack <= 'd0;
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up_rdata <= 'd0;
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end else begin
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up_rack <= up_rreq_s;
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if (up_rreq_s == 1'b1) begin
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case (up_raddr_s[3:0])
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4'h0: up_rdata <= VERSION;
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4'h1: up_rdata <= scratch;
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4'h2: up_rdata <= control;
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4'h3: up_rdata <= {31'h0,interrupt};
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4'h4: up_rdata <= counter_to_interrupt;
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4'h5: up_rdata <= counter_from_interrupt;
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4'h6: up_rdata <= counter_interrupt_handling;
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4'h7: up_rdata <= min_interrupt_handling;
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4'h8: up_rdata <= max_interrupt_handling;
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default: up_rdata <= 0;
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endcase
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end else begin
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up_rdata <= 32'd0;
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end
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end
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end
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// up bus interface
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up_axi i_up_axi(
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.up_rstn(s_axi_aresetn),
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.up_clk(s_axi_aclk),
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.up_axi_awvalid(s_axi_awvalid),
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.up_axi_awaddr(s_axi_awaddr),
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.up_axi_awready(s_axi_awready),
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.up_axi_wvalid(s_axi_wvalid),
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.up_axi_wdata(s_axi_wdata),
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.up_axi_wstrb(s_axi_wstrb),
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.up_axi_wready(s_axi_wready),
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.up_axi_bvalid(s_axi_bvalid),
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.up_axi_bresp(s_axi_bresp),
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.up_axi_bready(s_axi_bready),
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.up_axi_arvalid(s_axi_arvalid),
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.up_axi_araddr(s_axi_araddr),
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.up_axi_arready(s_axi_arready),
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.up_axi_rvalid(s_axi_rvalid),
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.up_axi_rresp(s_axi_rresp),
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.up_axi_rdata(s_axi_rdata),
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.up_axi_rready(s_axi_rready),
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.up_wreq (up_wreq_s),
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.up_waddr (up_waddr_s),
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.up_wdata (up_wdata_s),
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.up_wack (up_wack),
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.up_rreq (up_rreq_s),
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.up_raddr (up_raddr_s),
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.up_rdata (up_rdata),
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.up_rack (up_rack));
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endmodule
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// ***************************************************************************
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// ***************************************************************************
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@ -0,0 +1,17 @@
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# ip
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source ../scripts/adi_env.tcl
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source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_intr_monitor
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adi_ip_files axi_intr_monitor [list \
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"$ad_hdl_dir/library/common/up_axi.v" \
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"axi_intr_monitor.v" ]
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adi_ip_properties axi_intr_monitor
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ipx::infer_bus_interface irq xilinx.com:signal:interrupt_rtl:1.0 [ipx::current_core]
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ipx::save_core [ipx::current_core]
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