From 927508404e764b983538b3aef5f552eacfd6c875 Mon Sep 17 00:00:00 2001 From: Lars-Peter Clausen Date: Fri, 24 Mar 2017 16:49:13 +0100 Subject: [PATCH] axi_adc_decimate: Move processing pipeline to own sub-module Move the processing pipeline of the axi_adc_decimate core to its own sub-module. This makes it easier to simulate the processing independent of the register map. --- library/axi_adc_decimate/axi_adc_decimate.v | 139 ++----------- .../axi_adc_decimate_filter.v | 184 ++++++++++++++++++ .../axi_adc_decimate/axi_adc_decimate_ip.tcl | 1 + 3 files changed, 202 insertions(+), 122 deletions(-) create mode 100644 library/axi_adc_decimate/axi_adc_decimate_filter.v diff --git a/library/axi_adc_decimate/axi_adc_decimate.v b/library/axi_adc_decimate/axi_adc_decimate.v index 38a974837..fc47966cf 100644 --- a/library/axi_adc_decimate/axi_adc_decimate.v +++ b/library/axi_adc_decimate/axi_adc_decimate.v @@ -47,10 +47,10 @@ module axi_adc_decimate( input adc_valid_a, input adc_valid_b, - output reg [15:0] adc_dec_data_a, - output reg [15:0] adc_dec_data_b, - output reg adc_dec_valid_a, - output reg adc_dec_valid_b, + output [15:0] adc_dec_data_a, + output [15:0] adc_dec_data_b, + output adc_dec_valid_a, + output adc_dec_valid_b, // axi interface @@ -92,132 +92,27 @@ module axi_adc_decimate( wire [31:0] decimation_ratio; wire [31:0] filter_mask; - wire [105:0] adc_cic_data_a; - wire adc_cic_valid_a; - wire [105:0] adc_cic_data_b; - wire adc_cic_valid_b; - - wire [25:0] adc_fir_data_a; - wire adc_fir_valid_a; - wire [25:0] adc_fir_data_b; - wire adc_fir_valid_b; - - reg adc_dec_valid_a_filter; - reg adc_dec_valid_b_filter; - - reg [31:0] decimation_counter; - reg [15:0] decim_rate_cic; - // signal name changes assign up_clk = s_axi_aclk; assign up_rstn = s_axi_aresetn; - cic_decim cic_decimation_a ( - .clk(adc_clk), - .clk_enable(adc_valid_a), - .reset(adc_rst), - .filter_in(adc_data_a[11:0]), - .rate(decim_rate_cic), - .load_rate(1'b0), - .filter_out(adc_cic_data_a), - .ce_out(adc_cic_valid_a)); + axi_adc_decimate_filter axi_adc_decimate_filter ( + .adc_clk (adc_clk), + .adc_rst (adc_rst), - cic_decim cic_decimation_b ( - .clk(adc_clk), - .clk_enable(adc_valid_b), - .reset(adc_rst), - .filter_in(adc_data_b[11:0]), - .rate(decim_rate_cic), - .load_rate(1'b0), - .filter_out(adc_cic_data_b), - .ce_out(adc_cic_valid_b)); + .decimation_ratio (decimation_ratio), + .filter_mask (filter_mask), - fir_decim fir_decimation_a ( - .clk(adc_clk), - .clk_enable(adc_cic_valid_a), - .reset(adc_rst), - .filter_in(adc_cic_data_a[11:0]), - .filter_out(adc_fir_data_a), - .ce_out(adc_fir_valid_a)); + .adc_valid_a(adc_valid_a), + .adc_valid_b(adc_valid_b), + .adc_data_a(adc_data_a[11:0]), + .adc_data_b(adc_data_b[11:0]), - fir_decim fir_decimation_b ( - .clk(adc_clk), - .clk_enable(adc_cic_valid_b), - .reset(adc_rst), - .filter_in(adc_cic_data_b[11:0]), - .filter_out(adc_fir_data_b), - .ce_out(adc_fir_valid_b)); - - always @(*) begin - case (filter_mask) - 16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; - 16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; - 16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; - 16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; - 16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; - default: adc_dec_data_a = adc_data_a; - endcase - - case (filter_mask) - 16'h1: adc_dec_valid_a_filter = adc_fir_valid_a; - 16'h2: adc_dec_valid_a_filter = adc_fir_valid_a; - 16'h3: adc_dec_valid_a_filter = adc_fir_valid_a; - 16'h6: adc_dec_valid_a_filter = adc_fir_valid_a; - 16'h7: adc_dec_valid_a_filter = adc_fir_valid_a; - default: adc_dec_valid_a_filter = adc_valid_a; - endcase - - case (filter_mask) - 16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; - 16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; - 16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; - 16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; - 16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; - default: adc_dec_data_b = adc_data_b; - endcase - - case (filter_mask) - 16'h1: adc_dec_valid_b_filter = adc_fir_valid_b; - 16'h2: adc_dec_valid_b_filter = adc_fir_valid_b; - 16'h3: adc_dec_valid_b_filter = adc_fir_valid_b; - 16'h6: adc_dec_valid_b_filter = adc_fir_valid_b; - 16'h7: adc_dec_valid_b_filter = adc_fir_valid_b; - default: adc_dec_valid_b_filter = adc_valid_b; - endcase - - case (filter_mask) - 16'h1: decim_rate_cic = 16'd5; - 16'h2: decim_rate_cic = 16'd50; - 16'h3: decim_rate_cic = 16'd500; - 16'h6: decim_rate_cic = 16'd5000; - 16'h7: decim_rate_cic = 16'd50000; - default: decim_rate_cic = 16'd1; - endcase - end - - always @(posedge adc_clk) begin - if (adc_rst == 1'b1) begin - decimation_counter <= 32'b0; - adc_dec_valid_a <= 1'b0; - adc_dec_valid_b <= 1'b0; - end else begin - if (adc_dec_valid_a_filter == 1'b1) begin - if (decimation_counter < decimation_ratio) begin - decimation_counter <= decimation_counter + 1; - adc_dec_valid_a <= 1'b0; - adc_dec_valid_b <= 1'b0; - end else begin - decimation_counter <= 0; - adc_dec_valid_a <= 1'b1; - adc_dec_valid_b <= 1'b1; - end - end else begin - adc_dec_valid_a <= 1'b0; - adc_dec_valid_b <= 1'b0; - end - end - end + .adc_dec_data_a(adc_dec_data_a), + .adc_dec_data_b(adc_dec_data_b), + .adc_dec_valid_a(adc_dec_valid_a), + .adc_dec_valid_b(adc_dec_valid_b)); axi_adc_decimate_reg axi_adc_decimate_reg ( diff --git a/library/axi_adc_decimate/axi_adc_decimate_filter.v b/library/axi_adc_decimate/axi_adc_decimate_filter.v new file mode 100644 index 000000000..6370ad203 --- /dev/null +++ b/library/axi_adc_decimate/axi_adc_decimate_filter.v @@ -0,0 +1,184 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2017(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + + +module axi_adc_decimate_filter ( + input adc_clk, + input adc_rst, + + input [31:0] decimation_ratio, + input [31:0] filter_mask, + + input adc_valid_a, + input adc_valid_b, + input [11:0] adc_data_a, + input [11:0] adc_data_b, + + output reg [15:0] adc_dec_data_a, + output reg [15:0] adc_dec_data_b, + output reg adc_dec_valid_a, + output reg adc_dec_valid_b +); + + // internal signals + + reg [31:0] decimation_counter; + reg [15:0] decim_rate_cic; + + reg adc_dec_valid_a_filter; + reg adc_dec_valid_b_filter; + + wire [25:0] adc_fir_data_a; + wire adc_fir_valid_a; + wire [25:0] adc_fir_data_b; + wire adc_fir_valid_b; + + wire [105:0] adc_cic_data_a; + wire adc_cic_valid_a; + wire [105:0] adc_cic_data_b; + wire adc_cic_valid_b; + + cic_decim cic_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_valid_a), + .reset(adc_rst), + .filter_in(adc_data_a[11:0]), + .rate(decim_rate_cic), + .load_rate(1'b0), + .filter_out(adc_cic_data_a), + .ce_out(adc_cic_valid_a)); + + cic_decim cic_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_valid_b), + .reset(adc_rst), + .filter_in(adc_data_b[11:0]), + .rate(decim_rate_cic), + .load_rate(1'b0), + .filter_out(adc_cic_data_b), + .ce_out(adc_cic_valid_b)); + + fir_decim fir_decimation_a ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_a), + .reset(adc_rst), + .filter_in(adc_cic_data_a[11:0]), + .filter_out(adc_fir_data_a), + .ce_out(adc_fir_valid_a)); + + fir_decim fir_decimation_b ( + .clk(adc_clk), + .clk_enable(adc_cic_valid_b), + .reset(adc_rst), + .filter_in(adc_cic_data_b[11:0]), + .filter_out(adc_fir_data_b), + .ce_out(adc_fir_valid_b)); + + always @(*) begin + case (filter_mask) + 16'h1: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h2: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h3: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h6: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + 16'h7: adc_dec_data_a = {adc_fir_data_a[25], adc_fir_data_a[25:11]}; + default: adc_dec_data_a = adc_data_a; + endcase + + case (filter_mask) + 16'h1: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h2: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h3: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h6: adc_dec_valid_a_filter = adc_fir_valid_a; + 16'h7: adc_dec_valid_a_filter = adc_fir_valid_a; + default: adc_dec_valid_a_filter = adc_valid_a; + endcase + + case (filter_mask) + 16'h1: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h2: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h3: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h6: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + 16'h7: adc_dec_data_b = {adc_fir_data_b[25], adc_fir_data_b[25:11]}; + default: adc_dec_data_b = adc_data_b; + endcase + + case (filter_mask) + 16'h1: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h2: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h3: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h6: adc_dec_valid_b_filter = adc_fir_valid_b; + 16'h7: adc_dec_valid_b_filter = adc_fir_valid_b; + default: adc_dec_valid_b_filter = adc_valid_b; + endcase + + case (filter_mask) + 16'h1: decim_rate_cic = 16'd5; + 16'h2: decim_rate_cic = 16'd50; + 16'h3: decim_rate_cic = 16'd500; + 16'h6: decim_rate_cic = 16'd5000; + 16'h7: decim_rate_cic = 16'd50000; + default: decim_rate_cic = 16'd1; + endcase + end + + always @(posedge adc_clk) begin + if (adc_rst == 1'b1) begin + decimation_counter <= 32'b0; + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end else begin + if (adc_dec_valid_a_filter == 1'b1) begin + if (decimation_counter < decimation_ratio) begin + decimation_counter <= decimation_counter + 1; + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end else begin + decimation_counter <= 0; + adc_dec_valid_a <= 1'b1; + adc_dec_valid_b <= 1'b1; + end + end else begin + adc_dec_valid_a <= 1'b0; + adc_dec_valid_b <= 1'b0; + end + end + end + + +endmodule diff --git a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl index 0c4f5a492..a63b84ef8 100644 --- a/library/axi_adc_decimate/axi_adc_decimate_ip.tcl +++ b/library/axi_adc_decimate/axi_adc_decimate_ip.tcl @@ -10,6 +10,7 @@ adi_ip_files axi_adc_decimate [list \ "axi_adc_decimate_constr.xdc" \ "fir_decim.v" \ "cic_decim.v" \ + "axi_adc_decimate_filter.v" \ "axi_adc_decimate_reg.v" \ "axi_adc_decimate.v" ]