From 93044adddfb435d245ec857348dbf125a45b345c Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Mon, 15 Feb 2021 15:36:43 +0000 Subject: [PATCH] axi_spi_engine: almost full and almost empty is generated by the util_axis_fifo --- .../axi_spi_engine/axi_spi_engine.v | 58 +++++++++++++------ .../axi_spi_engine/axi_spi_engine_constr.ttcl | 3 + 2 files changed, 42 insertions(+), 19 deletions(-) diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine.v b/library/spi_engine/axi_spi_engine/axi_spi_engine.v index 398dd283f..0f6411242 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine.v +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine.v @@ -136,6 +136,7 @@ module axi_spi_engine #( wire [CMD_FIFO_ADDRESS_WIDTH-1:0] cmd_fifo_room; wire cmd_fifo_almost_empty; + wire up_cmd_fifo_almost_empty; wire [15:0] cmd_fifo_in_data; wire cmd_fifo_in_ready; @@ -143,6 +144,7 @@ module axi_spi_engine #( wire [SDO_FIFO_ADDRESS_WIDTH-1:0] sdo_fifo_room; wire sdo_fifo_almost_empty; + wire up_sdo_fifo_almost_empty; wire [(DATA_WIDTH-1):0] sdo_fifo_in_data; wire sdo_fifo_in_ready; @@ -151,6 +153,7 @@ module axi_spi_engine #( wire sdi_fifo_out_data_msb_s; wire [SDI_FIFO_ADDRESS_WIDTH-1:0] sdi_fifo_level; wire sdi_fifo_almost_full; + wire up_sdi_fifo_almost_full; wire [(NUM_OF_SDI * DATA_WIDTH-1):0] sdi_fifo_out_data; wire sdi_fifo_out_ready; @@ -258,9 +261,9 @@ module axi_spi_engine #( assign up_irq_source = { offload_sync_id_pending, sync_id_pending, - sdi_fifo_almost_full, - sdo_fifo_almost_empty, - cmd_fifo_almost_empty + up_sdi_fifo_almost_full, + up_sdo_fifo_almost_empty, + up_cmd_fifo_almost_empty }; assign up_irq_pending = up_irq_mask & up_irq_source; @@ -340,7 +343,7 @@ module axi_spi_engine #( 8'h31: up_rdata_ff <= offload_sync_id; 8'h34: up_rdata_ff <= cmd_fifo_room; 8'h35: up_rdata_ff <= sdo_fifo_room; - 8'h36: up_rdata_ff <= sdi_fifo_level; + 8'h36: up_rdata_ff <= (sdi_fifo_out_valid == 1) ? sdi_fifo_level + 1 : sdi_fifo_level; /* beacuse of first-word-fall-through */ 8'h3a: up_rdata_ff <= sdi_fifo_out_data[DATA_WIDTH-1:0]; 8'h3b: up_rdata_ff <= sdi_fifo_out_data_msb_s; /* store SDI's 32 bits MSB, if exists */ 8'h3c: up_rdata_ff <= sdi_fifo_out_data; /* PEEK register */ @@ -393,20 +396,16 @@ module axi_spi_engine #( end endgenerate - /* Evaluates to true if FIFO level/room is 3/4 or above */ - `define axi_spi_engine_check_watermark(x, n) \ - (x[n] == 1'b1 || x[n-1:n-2] == 2'b11) - assign cmd_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h38; assign cmd_fifo_in_data = up_wdata_s[15:0]; - assign cmd_fifo_almost_empty = - `axi_spi_engine_check_watermark(cmd_fifo_room, CMD_FIFO_ADDRESS_WIDTH-1); util_axis_fifo #( .DATA_WIDTH(16), .ADDRESS_WIDTH(CMD_FIFO_ADDRESS_WIDTH), .ASYNC_CLK(ASYNC_SPI_CLK), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(1) ) i_cmd_fifo ( .s_axis_aclk(clk), .s_axis_aresetn(up_sw_resetn), @@ -414,26 +413,30 @@ module axi_spi_engine #( .s_axis_valid(cmd_fifo_in_valid), .s_axis_data(cmd_fifo_in_data), .s_axis_room(cmd_fifo_room), + .s_axis_tlast(1'b0), .s_axis_full(), + .s_axis_almost_full(), .m_axis_aclk(spi_clk), .m_axis_aresetn(spi_resetn), .m_axis_ready(cmd_ready), .m_axis_valid(cmd_valid), .m_axis_data(cmd_data), + .m_axis_tlast(), .m_axis_empty(), + .m_axis_almost_empty(cmd_fifo_almost_empty), .m_axis_level() ); assign sdo_fifo_in_valid = up_wreq_s == 1'b1 && up_waddr_s == 8'h39; assign sdo_fifo_in_data = up_wdata_s[(DATA_WIDTH-1):0]; - assign sdo_fifo_almost_empty = - `axi_spi_engine_check_watermark(sdo_fifo_room, SDO_FIFO_ADDRESS_WIDTH-1); util_axis_fifo #( .DATA_WIDTH(DATA_WIDTH), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SDO_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(1) ) i_sdo_fifo ( .s_axis_aclk(clk), .s_axis_aresetn(up_sw_resetn), @@ -441,25 +444,29 @@ module axi_spi_engine #( .s_axis_valid(sdo_fifo_in_valid), .s_axis_data(sdo_fifo_in_data), .s_axis_room(sdo_fifo_room), + .s_axis_tlast(1'b0), .s_axis_full(), + .s_axis_almost_full(), .m_axis_aclk(spi_clk), .m_axis_aresetn(spi_resetn), .m_axis_ready(sdo_data_ready), .m_axis_valid(sdo_data_valid), .m_axis_data(sdo_data), + .m_axis_tlast(), .m_axis_level(), - .m_axis_empty() + .m_axis_empty(), + .m_axis_almost_empty(sdo_fifo_almost_empty) ); assign sdi_fifo_out_ready = up_rreq_s == 1'b1 && up_raddr_s == 8'h3a; - assign sdi_fifo_almost_full = - `axi_spi_engine_check_watermark(sdi_fifo_level, SDI_FIFO_ADDRESS_WIDTH-1); util_axis_fifo #( .DATA_WIDTH(NUM_OF_SDI * DATA_WIDTH), .ASYNC_CLK(ASYNC_SPI_CLK), .ADDRESS_WIDTH(SDI_FIFO_ADDRESS_WIDTH), - .M_AXIS_REGISTERED(0) + .M_AXIS_REGISTERED(0), + .ALMOST_EMPTY_THRESHOLD(1), + .ALMOST_FULL_THRESHOLD(1) ) i_sdi_fifo ( .s_axis_aclk(spi_clk), .s_axis_aresetn(spi_resetn), @@ -467,14 +474,18 @@ module axi_spi_engine #( .s_axis_valid(sdi_data_valid), .s_axis_data(sdi_data), .s_axis_room(), + .s_axis_tlast(), .s_axis_full(), + .s_axis_almost_full(sdi_fifo_almost_full), .m_axis_aclk(clk), .m_axis_aresetn(up_sw_resetn), .m_axis_ready(sdi_fifo_out_ready), .m_axis_valid(sdi_fifo_out_valid), .m_axis_data(sdi_fifo_out_data), + .m_axis_tlast(), .m_axis_level(sdi_fifo_level), - .m_axis_empty() + .m_axis_empty(), + .m_axis_almost_empty() ); generate if (ASYNC_SPI_CLK) begin @@ -629,4 +640,13 @@ module axi_spi_engine #( .out_clk (spi_clk), .out_bits (offload0_mem_reset)); + sync_bits #( + .NUM_OF_BITS (3), + .ASYNC_CLK (ASYNC_SPI_CLK) + ) i_fifo_status ( + .in_bits ({cmd_fifo_almost_empty, sdi_fifo_almost_full, sdo_fifo_almost_empty}), + .out_resetn (up_sw_resetn), + .out_clk (clk), + .out_bits ({up_cmd_fifo_almost_empty, up_sdi_fifo_almost_full, up_sdo_fifo_almost_empty})); + endmodule diff --git a/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl b/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl index 3a3cee0d4..55bc9dafc 100644 --- a/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl +++ b/library/spi_engine/axi_spi_engine/axi_spi_engine_constr.ttcl @@ -24,4 +24,7 @@ set_false_path -quiet \ set_false_path -quiet \ -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_offload_mem_reset_sync/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] +set_false_path -quiet \ + -to [get_cells -quiet -hierarchical -filter {NAME =~ *i_fifo_status/cdc_sync_stage1_reg* && IS_SEQUENTIAL}] + <: } :>