fmcadc2/vc707: Add adf4355 access, update design to Vivado 2016.2
parent
dc21384002
commit
93fa5aeec3
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@ -27,10 +27,10 @@ set_property -dict {PACKAGE_PIN L41 IOSTANDARD LVDS DIFF_TERM TRUE} [get_por
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set_property -dict {PACKAGE_PIN N41 IOSTANDARD LVCMOS18} [get_ports spi_adc_csn] ; ## H08 FMC1_HPC_LA02_N
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set_property -dict {PACKAGE_PIN J40 IOSTANDARD LVCMOS18} [get_ports spi_adc_clk] ; ## D08 FMC1_HPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN J41 IOSTANDARD LVCMOS18} [get_ports spi_adc_sdio] ; ## D09 FMC1_HPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_0] ; ## H07 FMC1_HPC_LA02_P
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set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports spi_ext_csn_1] ; ## C10 FMC1_HPC_LA06_P
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set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports spi_ext_clk] ; ## G06 FMC1_HPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports spi_ext_sdio] ; ## G07 FMC1_HPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN P41 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_data_or_csn_0] ; ## H07 FMC1_HPC_LA02_P
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set_property -dict {PACKAGE_PIN K42 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_clk_or_csn_1] ; ## C10 FMC1_HPC_LA06_P
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set_property -dict {PACKAGE_PIN K39 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_le_or_clk] ; ## G06 FMC1_HPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN K40 IOSTANDARD LVCMOS18} [get_ports spi_adf4355_ce_or_sdio] ; ## G07 FMC1_HPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN M42 IOSTANDARD LVCMOS18} [get_ports adc_irq] ; ## G09 FMC1_HPC_LA03_P
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set_property -dict {PACKAGE_PIN L42 IOSTANDARD LVCMOS18} [get_ports adc_fd] ; ## G10 FMC1_HPC_LA03_N
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@ -104,10 +104,11 @@ module system_top (
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spi_adc_csn,
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spi_adc_clk,
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spi_adc_sdio,
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spi_ext_csn_0,
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spi_ext_csn_1,
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spi_ext_clk,
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spi_ext_sdio);
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spi_adf4355_data_or_csn_0,
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spi_adf4355_clk_or_csn_1,
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spi_adf4355_le_or_clk,
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spi_adf4355_ce_or_sdio);
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input sys_rst;
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input sys_clk_p;
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@ -174,10 +175,11 @@ module system_top (
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output spi_adc_csn;
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output spi_adc_clk;
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inout spi_adc_sdio;
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output spi_ext_csn_0;
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output spi_ext_csn_1;
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output spi_ext_clk;
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inout spi_ext_sdio;
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output spi_adf4355_data_or_csn_0;
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output spi_adf4355_clk_or_csn_1;
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output spi_adf4355_le_or_clk;
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inout spi_adf4355_ce_or_sdio;
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// internal signals
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@ -191,14 +193,6 @@ module system_top (
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wire rx_sysref;
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wire rx_sync;
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// spi
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assign spi_adc_csn = spi_csn[0];
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assign spi_adc_clk = spi_clk;
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assign spi_ext_csn_0 = spi_csn[1];
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assign spi_ext_csn_1 = spi_csn[2];
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assign spi_ext_clk = spi_clk;
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// default logic
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assign fan_pwm = 1'b1;
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@ -223,22 +217,30 @@ module system_top (
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.O (rx_sync_p),
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.OB (rx_sync_n));
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// spi
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assign gpio_i[37:36] = gpio_o[37:36];
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fmcadc2_spi i_fmcadc2_spi (
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.spi_adc_csn (spi_adc_csn),
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.spi_ext_csn_0 (spi_ext_csn_0),
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.spi_ext_csn_1 (spi_ext_csn_1),
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.spi_adf4355 (gpio_o[36]),
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.spi_adf4355_ce (gpio_o[37]),
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.spi_clk (spi_clk),
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.spi_csn (spi_csn),
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.spi_mosi (spi_mosi),
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.spi_miso (spi_miso),
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.spi_adc_csn (spi_adc_csn),
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.spi_adc_clk (spi_adc_clk),
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.spi_adc_sdio (spi_adc_sdio),
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.spi_ext_sdio (spi_ext_sdio));
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.spi_adf4355_data_or_csn_0 (spi_adf4355_data_or_csn_0),
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.spi_adf4355_clk_or_csn_1 (spi_adf4355_clk_or_csn_1),
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.spi_adf4355_le_or_clk (spi_adf4355_le_or_clk),
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.spi_adf4355_ce_or_sdio (spi_adf4355_ce_or_sdio));
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ad_iobuf #(.DATA_WIDTH(2)) i_iobuf (
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.dio_t (gpio_t[33:32]),
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.dio_i (gpio_o[33:32]),
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.dio_o (gpio_i[33:32]),
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.dio_p ({ adc_irq, // 33
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adc_fd})); // 32
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.dio_p ({adc_irq, adc_fd}));
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ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
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.dio_t (gpio_t[20:0]),
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