parent
c1213ffe71
commit
9404e93126
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@ -49,8 +49,7 @@ module axi_ad9434_pnmon (
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// pn interface
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// pn interface
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adc_pnseq_sel,
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adc_pnseq_sel,
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adc_pn_err,
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adc_pn_err,
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adc_pn_oos
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adc_pn_oos);
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);
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// adc interface
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// adc interface
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input adc_clk;
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input adc_clk;
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@ -62,7 +61,6 @@ module axi_ad9434_pnmon (
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output adc_pn_oos;
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output adc_pn_oos;
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// internal registers
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// internal registers
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reg [47:0] adc_pn_data_in = 'd0;
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reg [47:0] adc_pn_data_pn = 'd0;
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reg [47:0] adc_pn_data_pn = 'd0;
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// internal signals
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// internal signals
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@ -183,11 +181,9 @@ module axi_ad9434_pnmon (
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endfunction
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endfunction
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// pn sequence selection
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// pn sequence selection
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assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_pn_data_in : adc_pn_data_pn;
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assign adc_pn_data_pn_s = (adc_pn_oos == 1'b1) ? adc_data : adc_pn_data_pn;
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always @(posedge adc_clk) begin
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always @(posedge adc_clk) begin
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// TODO: verify if this works
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adc_pn_data_in <= adc_data;
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if(adc_pnseq_sel == 4'b0) begin
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if(adc_pnseq_sel == 4'b0) begin
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adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
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adc_pn_data_pn <= pn9(adc_pn_data_pn_s);
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end else begin
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end else begin
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@ -199,7 +195,7 @@ module axi_ad9434_pnmon (
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ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
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ad_pnmon #(.DATA_WIDTH(48)) i_pnmon (
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.adc_clk (adc_clk),
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.adc_clk (adc_clk),
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.adc_valid_in (1'b1),
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.adc_valid_in (1'b1),
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.adc_data_in (adc_pn_data_in),
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.adc_data_in (adc_data),
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.adc_data_pn (adc_pn_data_pn),
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.adc_data_pn (adc_pn_data_pn),
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.adc_pn_oos (adc_pn_oos),
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.adc_pn_oos (adc_pn_oos),
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.adc_pn_err (adc_pn_err));
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.adc_pn_err (adc_pn_err));
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