adrv9009_zu11eg: Initial commit
Observation and RX should never run at the same time. Given that there is no FIFO on the RX and OBS paths, they will use the higheste performance HP ports, which are HP1 and HP2main
Adrian Costina
parent
369974f2e7
commit
9409df6a6f
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####################################################################################
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## Copyright 2018(c) Analog Devices, Inc.
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## Auto-generated, do not modify!
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####################################################################################
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PROJECT_NAME := adrv9009_zu11eg_som
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M_DEPS += adrv9009_zu11eg_som_spi.v
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M_DEPS += adrv9009_zu11eg_som_bd.tcl
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M_DEPS += carrier_bd.tcl
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M_DEPS += adrv9009_zu11eg_som_constr.xdc
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M_DEPS += carrier_constr.xdc
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M_DEPS += ../../library/xilinx/common/ad_iobuf.v
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M_DEPS += ../../library/jesd204/scripts/jesd204.tcl
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LIB_DEPS += axi_dmac
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_adc
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LIB_DEPS += jesd204/ad_ip_jesd204_tpl_dac
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LIB_DEPS += jesd204/axi_jesd204_rx
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LIB_DEPS += jesd204/axi_jesd204_tx
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LIB_DEPS += jesd204/jesd204_rx
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LIB_DEPS += jesd204/jesd204_tx
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LIB_DEPS += util_pack/util_cpack2
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LIB_DEPS += util_pack/util_upack2
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LIB_DEPS += xilinx/axi_adxcvr
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LIB_DEPS += xilinx/axi_dacfifo
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LIB_DEPS += xilinx/util_adxcvr
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include ../scripts/project-xilinx.mk
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disconnect_bd_net /sys_cpu_clk [get_bd_pins sys_ps8/maxihpm0_lpd_aclk]
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add_files -fileset constrs_1 -norecurse ./adrv9009_zu11eg_som_constr.xdc
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create_bd_port -dir I sys_reset
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create_bd_port -dir I ref_clk_a
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create_bd_port -dir I ref_clk_b
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create_bd_port -dir I core_clk_a
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create_bd_port -dir I core_clk_b
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# TX parameters
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set TX_NUM_OF_LANES 8 ; # L
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set TX_NUM_OF_CONVERTERS 8 ; # M
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set TX_SAMPLES_PER_FRAME 1 ; # S
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set TX_SAMPLE_WIDTH 16 ; # N/NP
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set TX_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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# RX parameters
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set RX_NUM_OF_LANES 4 ; # L
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set RX_NUM_OF_CONVERTERS 8 ; # M
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set RX_SAMPLES_PER_FRAME 1 ; # S
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set RX_SAMPLE_WIDTH 16 ; # N/NP
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set RX_SAMPLES_PER_CHANNEL 1 ; # L * 32 / (M * N)
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# RX Observation parameters
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set OBS_NUM_OF_LANES 4 ; # L
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set OBS_NUM_OF_CONVERTERS 4 ; # M
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set OBS_SAMPLES_PER_FRAME 1 ; # S
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set OBS_SAMPLE_WIDTH 16 ; # N/NP
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set OBS_SAMPLES_PER_CHANNEL 2 ; # L * 32 / (M * N)
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create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddr4_rtl:1.0 ddr4_rtl_1
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create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:diff_clock_rtl:1.0 ddr4_ref_1
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ad_ip_instance ip:ddr4 ddr4_1
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_DataWidth {32}
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiDataWidth {256}
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_AxiAddressWidth {31}
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_InputClockPeriod {3332}
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_MemoryPart {MT40A512M16HA-083E}
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ad_ip_parameter ddr4_1 CONFIG.C0.BANK_GROUP_WIDTH {1}
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ad_ip_parameter ddr4_1 CONFIG.C0.DDR4_CasLatency {16}
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ad_connect ddr4_rtl_1 ddr4_1/C0_DDR4
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set_property -dict [list CONFIG.FREQ_HZ {300000000}] [get_bd_intf_ports ddr4_ref_1]
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ad_connect ddr4_ref_1 ddr4_1/C0_SYS_CLK
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set dac_fifo_name axi_tx_fifo
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set dac_data_width [expr 32*$TX_NUM_OF_LANES]
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set dac_dma_data_width 256
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set dac_fifo_address_width 31
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ad_ip_instance axi_dacfifo $dac_fifo_name
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ad_ip_parameter $dac_fifo_name CONFIG.DAC_DATA_WIDTH $dac_data_width
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ad_ip_parameter $dac_fifo_name CONFIG.DMA_DATA_WIDTH $dac_dma_data_width
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ad_ip_parameter $dac_fifo_name CONFIG.AXI_DATA_WIDTH 256
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ad_ip_parameter $dac_fifo_name CONFIG.AXI_SIZE 5
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ad_ip_parameter $dac_fifo_name CONFIG.AXI_LENGTH 255
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ad_ip_parameter $dac_fifo_name CONFIG.AXI_ADDRESS 0x80000000
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create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 ddr4_1_rstgen
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ad_connect ddr4_1_rstgen/slowest_sync_clk ddr4_1/c0_ddr4_ui_clk
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ad_connect ddr4_1/c0_ddr4_ui_clk_sync_rst ddr4_1_rstgen/ext_reset_in
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ad_connect ddr4_1_rstgen/peripheral_aresetn axi_tx_fifo/axi_resetn
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ad_connect sys_reset ddr4_1/sys_rst
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source $ad_hdl_dir/library/jesd204/scripts/jesd204.tcl
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create_bd_port -dir I dac_fifo_bypass
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ad_ip_instance axi_adxcvr axi_adrv9009_som_tx_xcvr
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.QPLL_ENABLE 1
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ad_ip_parameter axi_adrv9009_som_tx_xcvr CONFIG.TX_OR_RX_N 1
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adi_axi_jesd204_tx_create axi_adrv9009_som_tx_jesd $TX_NUM_OF_LANES
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set_property -dict [list CONFIG.SYSREF_IOB {false}] [get_bd_cells axi_adrv9009_som_tx_jesd/tx]
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ad_ip_instance util_upack2 util_som_tx_upack [list \
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NUM_OF_CHANNELS $TX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $TX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $TX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_tx_create tx_adrv9009_som_tpl_core $TX_NUM_OF_LANES \
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$TX_NUM_OF_CONVERTERS \
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$TX_SAMPLES_PER_FRAME \
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$TX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_som_tx_dma
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_TYPE_SRC 0
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_TYPE_DEST 1
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.CYCLIC 1
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_DEST $dac_dma_data_width
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ad_ip_parameter axi_adrv9009_som_tx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_instance axi_adxcvr axi_adrv9009_som_rx_xcvr
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ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_som_rx_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_som_rx_jesd $RX_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_som_rx_cpack [list \
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NUM_OF_CHANNELS $RX_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $RX_SAMPLES_PER_CHANNEL \
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SAMPLE_DATA_WIDTH $RX_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create rx_adrv9009_som_tpl_core $RX_NUM_OF_LANES \
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$RX_NUM_OF_CONVERTERS \
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$RX_SAMPLES_PER_FRAME \
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$RX_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_som_rx_dma
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_rx_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_som_rx_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance axi_adxcvr axi_adrv9009_som_obs_xcvr
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ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.NUM_OF_LANES $RX_NUM_OF_LANES
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ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.QPLL_ENABLE 0
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ad_ip_parameter axi_adrv9009_som_obs_xcvr CONFIG.TX_OR_RX_N 0
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adi_axi_jesd204_rx_create axi_adrv9009_som_obs_jesd $OBS_NUM_OF_LANES
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ad_ip_instance util_cpack2 util_som_obs_cpack [list \
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NUM_OF_CHANNELS $OBS_NUM_OF_CONVERTERS \
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SAMPLES_PER_CHANNEL $OBS_SAMPLES_PER_CHANNEL\
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SAMPLE_DATA_WIDTH $OBS_SAMPLE_WIDTH \
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]
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adi_tpl_jesd204_rx_create obs_adrv9009_som_tpl_core $OBS_NUM_OF_LANES \
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$OBS_NUM_OF_CONVERTERS \
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$OBS_SAMPLES_PER_FRAME \
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$OBS_SAMPLE_WIDTH
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ad_ip_instance axi_dmac axi_adrv9009_som_obs_dma
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_TYPE_SRC 2
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_TYPE_DEST 0
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.CYCLIC 0
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.SYNC_TRANSFER_START 1
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_SLICE_SRC 1
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.AXI_SLICE_DEST 1
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_2D_TRANSFER 0
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.FIFO_SIZE 32
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ad_ip_parameter axi_adrv9009_som_obs_dma MAX_BYTES_PER_BURST 256
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_SRC 128
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ad_ip_parameter axi_adrv9009_som_obs_dma CONFIG.DMA_DATA_WIDTH_DEST 128
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ad_ip_instance util_adxcvr util_adrv9009_som_xcvr
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.RX_NUM_OF_LANES [expr $RX_NUM_OF_LANES+$OBS_NUM_OF_LANES]
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.TX_NUM_OF_LANES $TX_NUM_OF_LANES
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.TX_OUT_DIV 2
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.CPLL_FBDIV 4
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.RX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.TX_CLK25_DIV 10
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.QPLL_FBDIV 80
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ad_ip_parameter util_adrv9009_som_xcvr CONFIG.QPLL_REFCLK_DIV 1
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/qpll_ref_clk_0
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ad_xcvrpll ref_clk_b util_adrv9009_som_xcvr/cpll_ref_clk_0
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ad_xcvrpll ref_clk_b util_adrv9009_som_xcvr/cpll_ref_clk_1
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/cpll_ref_clk_2
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/cpll_ref_clk_3
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/qpll_ref_clk_4
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ad_xcvrpll ref_clk_b util_adrv9009_som_xcvr/cpll_ref_clk_4
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ad_xcvrpll ref_clk_b util_adrv9009_som_xcvr/cpll_ref_clk_5
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/cpll_ref_clk_6
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ad_xcvrpll ref_clk_a util_adrv9009_som_xcvr/cpll_ref_clk_7
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ad_xcvrpll axi_adrv9009_som_tx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_qpll_rst_0
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ad_xcvrpll axi_adrv9009_som_rx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_0
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ad_xcvrpll axi_adrv9009_som_rx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_1
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ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_2
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ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_3
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ad_xcvrpll axi_adrv9009_som_tx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_qpll_rst_4
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ad_xcvrpll axi_adrv9009_som_rx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_4
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ad_xcvrpll axi_adrv9009_som_rx_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_5
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ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_6
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ad_xcvrpll axi_adrv9009_som_obs_xcvr/up_pll_rst util_adrv9009_som_xcvr/up_cpll_rst_7
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ad_connect sys_cpu_resetn util_adrv9009_som_xcvr/up_rstn
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ad_connect sys_cpu_clk util_adrv9009_som_xcvr/up_clk
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_tx_xcvr axi_adrv9009_som_tx_jesd {} core_clk_a
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_rx_xcvr axi_adrv9009_som_rx_jesd {} core_clk_b
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ad_xcvrcon util_adrv9009_som_xcvr axi_adrv9009_som_obs_xcvr axi_adrv9009_som_obs_jesd {} core_clk_a
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ad_connect core_clk_a tx_adrv9009_som_tpl_core/link_clk
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ad_connect axi_adrv9009_som_tx_jesd/tx_data tx_adrv9009_som_tpl_core/link
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ad_connect core_clk_a util_som_tx_upack/clk
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ad_connect core_clk_a_rstgen/peripheral_reset util_som_tx_upack/reset
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ad_connect tx_adrv9009_som_tpl_core/dac_valid_0 util_som_tx_upack/fifo_rd_en
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for {set i 0} {$i < $TX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect util_som_tx_upack/fifo_rd_data_$i tx_adrv9009_som_tpl_core/dac_data_$i
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ad_connect tx_adrv9009_som_tpl_core/dac_enable_$i util_som_tx_upack/enable_$i
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}
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ad_connect tx_adrv9009_som_tpl_core/dac_dunf util_som_tx_upack/fifo_rd_underflow
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# connections (adc)
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ad_connect core_clk_b rx_adrv9009_som_tpl_core/link_clk
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ad_connect axi_adrv9009_som_rx_jesd/rx_sof rx_adrv9009_som_tpl_core/link_sof
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ad_connect axi_adrv9009_som_rx_jesd/rx_data_tdata rx_adrv9009_som_tpl_core/link_data
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ad_connect axi_adrv9009_som_rx_jesd/rx_data_tvalid rx_adrv9009_som_tpl_core/link_valid
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ad_connect core_clk_b util_som_rx_cpack/clk
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ad_connect core_clk_b_rstgen/peripheral_reset util_som_rx_cpack/reset
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ad_connect rx_adrv9009_som_tpl_core/adc_valid_0 util_som_rx_cpack/fifo_wr_en
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for {set i 0} {$i < $RX_NUM_OF_CONVERTERS} {incr i} {
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ad_connect rx_adrv9009_som_tpl_core/adc_enable_$i util_som_rx_cpack/enable_$i
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ad_connect rx_adrv9009_som_tpl_core/adc_data_$i util_som_rx_cpack/fifo_wr_data_$i
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}
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ad_connect rx_adrv9009_som_tpl_core/adc_dovf util_som_rx_cpack/fifo_wr_overflow
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# connections (adc-os)
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ad_connect core_clk_a obs_adrv9009_som_tpl_core/link_clk
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ad_connect axi_adrv9009_som_obs_jesd/rx_sof obs_adrv9009_som_tpl_core/link_sof
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ad_connect axi_adrv9009_som_obs_jesd/rx_data_tdata obs_adrv9009_som_tpl_core/link_data
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ad_connect axi_adrv9009_som_obs_jesd/rx_data_tvalid obs_adrv9009_som_tpl_core/link_valid
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ad_connect core_clk_a util_som_obs_cpack/clk
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ad_connect core_clk_a_rstgen/peripheral_reset util_som_obs_cpack/reset
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ad_connect core_clk_a axi_adrv9009_som_obs_dma/fifo_wr_clk
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ad_connect obs_adrv9009_som_tpl_core/adc_valid_0 util_som_obs_cpack/fifo_wr_en
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for {set i 0} {$i < $OBS_NUM_OF_CONVERTERS} {incr i} {
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ad_connect obs_adrv9009_som_tpl_core/adc_enable_$i util_som_obs_cpack/enable_$i
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ad_connect obs_adrv9009_som_tpl_core/adc_data_$i util_som_obs_cpack/fifo_wr_data_$i
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}
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ad_connect obs_adrv9009_som_tpl_core/adc_dovf util_som_obs_cpack/fifo_wr_overflow
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ad_connect util_som_obs_cpack/packed_fifo_wr axi_adrv9009_som_obs_dma/fifo_wr
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|
||||
ad_connect core_clk_a axi_adrv9009_som_tx_dma/m_axis_aclk
|
||||
|
||||
ad_connect axi_adrv9009_som_rx_dma/fifo_wr_clk core_clk_b
|
||||
ad_connect util_som_rx_cpack/packed_fifo_wr axi_adrv9009_som_rx_dma/fifo_wr
|
||||
|
||||
ad_connect axi_tx_fifo/axi ddr4_1/C0_DDR4_S_AXI
|
||||
ad_connect ddr4_1/c0_ddr4_aresetn ddr4_1_rstgen/peripheral_aresetn
|
||||
ad_connect core_clk_a axi_tx_fifo/dma_clk
|
||||
ad_connect axi_tx_fifo/dma_rst core_clk_a_rstgen/peripheral_reset
|
||||
ad_connect axi_tx_fifo/dma_valid axi_adrv9009_som_tx_dma/m_axis_valid
|
||||
ad_connect axi_tx_fifo/dma_ready axi_adrv9009_som_tx_dma/m_axis_ready
|
||||
ad_connect axi_adrv9009_som_tx_dma/m_axis_data axi_tx_fifo/dma_data
|
||||
ad_connect axi_adrv9009_som_tx_dma/m_axis_last axi_tx_fifo/dma_xfer_last
|
||||
ad_connect axi_adrv9009_som_tx_dma/m_axis_xfer_req axi_tx_fifo/dma_xfer_req
|
||||
ad_connect core_clk_a axi_tx_fifo/dac_clk
|
||||
ad_connect axi_tx_fifo/dac_rst core_clk_a_rstgen/peripheral_reset
|
||||
ad_connect util_som_tx_upack/s_axis_data axi_tx_fifo/dac_data
|
||||
ad_connect util_som_tx_upack/s_axis_ready axi_tx_fifo/dac_valid
|
||||
ad_connect axi_tx_fifo/axi_clk ddr4_1/c0_ddr4_ui_clk
|
||||
ad_connect dac_fifo_bypass axi_tx_fifo/bypass
|
||||
ad_connect util_som_tx_upack/s_axis_valid VCC_1/dout
|
||||
|
||||
ad_ip_instance clk_wiz dma_clk_wiz
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.PRIMITIVE MMCM
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.RESET_TYPE ACTIVE_LOW
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.USE_LOCKED false
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.CLKOUT1_REQUESTED_OUT_FREQ 332.9
|
||||
ad_ip_parameter dma_clk_wiz CONFIG.PRIM_SOURCE No_buffer
|
||||
|
||||
ad_connect sys_cpu_clk dma_clk_wiz/clk_in1
|
||||
ad_connect sys_cpu_resetn dma_clk_wiz/resetn
|
||||
|
||||
ad_ip_instance proc_sys_reset sys_dma_rstgen
|
||||
ad_ip_parameter sys_dma_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
ad_connect sys_dma_clk dma_clk_wiz/clk_out1
|
||||
ad_connect sys_dma_rstgen/ext_reset_in sys_rstgen/peripheral_reset
|
||||
ad_connect sys_dma_clk sys_dma_rstgen/slowest_sync_clk
|
||||
ad_connect sys_dma_resetn sys_dma_rstgen/peripheral_aresetn
|
||||
|
||||
# interconnect (cpu)
|
||||
|
||||
ad_cpu_interconnect 0x44A00000 rx_adrv9009_som_tpl_core
|
||||
ad_cpu_interconnect 0x44A04000 tx_adrv9009_som_tpl_core
|
||||
ad_cpu_interconnect 0x44A08000 obs_adrv9009_som_tpl_core
|
||||
ad_cpu_interconnect 0x44A20000 axi_adrv9009_som_tx_xcvr
|
||||
ad_cpu_interconnect 0x44A30000 axi_adrv9009_som_tx_jesd
|
||||
ad_cpu_interconnect 0x44A40000 axi_adrv9009_som_rx_xcvr
|
||||
ad_cpu_interconnect 0x44A50000 axi_adrv9009_som_rx_jesd
|
||||
ad_cpu_interconnect 0x44A60000 axi_adrv9009_som_obs_xcvr
|
||||
ad_cpu_interconnect 0x44A70000 axi_adrv9009_som_obs_jesd
|
||||
ad_cpu_interconnect 0x7c400000 axi_adrv9009_som_tx_dma
|
||||
ad_cpu_interconnect 0x7c420000 axi_adrv9009_som_rx_dma
|
||||
ad_cpu_interconnect 0x7c440000 axi_adrv9009_som_obs_dma
|
||||
|
||||
# gt uses hp0, and 100MHz clock for both DRP and AXI4
|
||||
|
||||
ad_mem_hp0_interconnect sys_cpu_clk sys_ps8/S_AXI_HP0
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_adrv9009_som_rx_xcvr/m_axi
|
||||
ad_mem_hp0_interconnect sys_cpu_clk axi_adrv9009_som_obs_xcvr/m_axi
|
||||
|
||||
# interconnect (mem/dac)
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP3 1
|
||||
ad_connect sys_dma_clk sys_ps8/saxihp1_fpd_aclk
|
||||
ad_connect sys_dma_clk axi_adrv9009_som_obs_dma/m_dest_axi_aclk
|
||||
ad_connect sys_dma_resetn axi_adrv9009_som_obs_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_adrv9009_som_obs_dma/m_dest_axi sys_ps8/S_AXI_HP1_FPD
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP4 1
|
||||
ad_connect sys_dma_clk sys_ps8/saxihp2_fpd_aclk
|
||||
ad_connect sys_dma_clk axi_adrv9009_som_rx_dma/m_dest_axi_aclk
|
||||
ad_connect sys_dma_resetn axi_adrv9009_som_rx_dma/m_dest_axi_aresetn
|
||||
ad_connect axi_adrv9009_som_rx_dma/m_dest_axi sys_ps8/S_AXI_HP2_FPD
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__S_AXI_GP5 1
|
||||
ad_connect sys_dma_clk sys_ps8/saxihp3_fpd_aclk
|
||||
ad_connect sys_dma_clk axi_adrv9009_som_tx_dma/m_src_axi_aclk
|
||||
ad_connect sys_dma_resetn axi_adrv9009_som_tx_dma/m_src_axi_aresetn
|
||||
ad_connect axi_adrv9009_som_tx_dma/m_src_axi sys_ps8/S_AXI_HP3_FPD
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_cpu_interrupt ps-8 mb-8 axi_adrv9009_som_obs_dma/irq
|
||||
ad_cpu_interrupt ps-9 mb-9 axi_adrv9009_som_tx_dma/irq
|
||||
ad_cpu_interrupt ps-10 mb-15 axi_adrv9009_som_rx_dma/irq
|
||||
ad_cpu_interrupt ps-11 mb-14 axi_adrv9009_som_obs_jesd/irq
|
||||
ad_cpu_interrupt ps-12 mb-13 axi_adrv9009_som_tx_jesd/irq
|
||||
ad_cpu_interrupt ps-13 mb-12 axi_adrv9009_som_rx_jesd/irq
|
||||
|
||||
#FIXME
|
||||
delete_bd_objs [get_bd_intf_nets util_adrv9009_som_xcvr_rx_3]
|
||||
delete_bd_objs [get_bd_intf_nets util_adrv9009_som_xcvr_rx_2]
|
||||
delete_bd_objs [get_bd_intf_nets util_adrv9009_som_xcvr_rx_4]
|
||||
delete_bd_objs [get_bd_intf_nets util_adrv9009_som_xcvr_rx_5]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_rx_xcvr_up_es_2]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_rx_xcvr_up_ch_2]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_rx_xcvr_up_es_3]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_rx_xcvr_up_ch_3]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_obs_xcvr_up_es_0]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_obs_xcvr_up_ch_0]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_obs_xcvr_up_es_1]
|
||||
delete_bd_objs [get_bd_intf_nets axi_adrv9009_som_obs_xcvr_up_ch_1]
|
||||
|
||||
ad_connect util_adrv9009_som_xcvr/rx_2 axi_adrv9009_som_obs_jesd/rx_phy0
|
||||
ad_connect util_adrv9009_som_xcvr/rx_3 axi_adrv9009_som_obs_jesd/rx_phy1
|
||||
ad_connect util_adrv9009_som_xcvr/rx_4 axi_adrv9009_som_rx_jesd/rx_phy2
|
||||
ad_connect util_adrv9009_som_xcvr/rx_5 axi_adrv9009_som_rx_jesd/rx_phy3
|
||||
ad_connect axi_adrv9009_som_obs_xcvr/up_es_0 util_adrv9009_som_xcvr/up_es_2
|
||||
ad_connect axi_adrv9009_som_obs_xcvr/up_ch_0 util_adrv9009_som_xcvr/up_rx_2
|
||||
ad_connect axi_adrv9009_som_obs_xcvr/up_es_1 util_adrv9009_som_xcvr/up_es_3
|
||||
ad_connect axi_adrv9009_som_obs_xcvr/up_ch_1 util_adrv9009_som_xcvr/up_rx_3
|
||||
ad_connect axi_adrv9009_som_rx_xcvr/up_es_2 util_adrv9009_som_xcvr/up_es_4
|
||||
ad_connect axi_adrv9009_som_rx_xcvr/up_ch_2 util_adrv9009_som_xcvr/up_rx_4
|
||||
ad_connect axi_adrv9009_som_rx_xcvr/up_es_3 util_adrv9009_som_xcvr/up_es_5
|
||||
ad_connect axi_adrv9009_som_rx_xcvr/up_ch_3 util_adrv9009_som_xcvr/up_rx_5
|
||||
disconnect_bd_net /core_clk_b_1 [get_bd_pins util_adrv9009_som_xcvr/rx_clk_2]
|
||||
disconnect_bd_net /core_clk_b_1 [get_bd_pins util_adrv9009_som_xcvr/rx_clk_3]
|
||||
disconnect_bd_net /core_clk_a_1 [get_bd_pins util_adrv9009_som_xcvr/rx_clk_4]
|
||||
disconnect_bd_net /core_clk_a_1 [get_bd_pins util_adrv9009_som_xcvr/rx_clk_5]
|
||||
connect_bd_net [get_bd_ports core_clk_a] [get_bd_pins util_adrv9009_som_xcvr/rx_clk_2]
|
||||
connect_bd_net [get_bd_ports core_clk_a] [get_bd_pins util_adrv9009_som_xcvr/rx_clk_3]
|
||||
connect_bd_net [get_bd_ports core_clk_b] [get_bd_pins util_adrv9009_som_xcvr/rx_clk_4]
|
||||
connect_bd_net [get_bd_ports core_clk_b] [get_bd_pins util_adrv9009_som_xcvr/rx_clk_5]
|
||||
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \
|
||||
[get_bd_addr_spaces axi_adrv9009_som_obs_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP3/HP1_DDR_LOW] SEG_sys_ps8_HP1_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \
|
||||
[get_bd_addr_spaces axi_adrv9009_som_rx_dma/m_dest_axi] [get_bd_addr_segs sys_ps8/SAXIGP4/HP2_DDR_LOW] SEG_sys_ps8_HP2_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x00000000 \
|
||||
[get_bd_addr_spaces axi_adrv9009_som_tx_dma/m_src_axi] [get_bd_addr_segs sys_ps8/SAXIGP5/HP3_DDR_LOW] SEG_sys_ps8_HP3_DDR_LOW
|
||||
create_bd_addr_seg -range 0x80000000 -offset 0x80000000 \
|
||||
[get_bd_addr_spaces axi_tx_fifo/axi] [get_bd_addr_segs ddr4_1/C0_DDR4_MEMORY_MAP/C0_DDR4_ADDRESS_BLOCK] SEG_ddr4_1_C0_DDR4_ADDRESS_BLOCK
|
||||
|
|
@ -0,0 +1,215 @@
|
|||
|
||||
set_property PACKAGE_PIN G24 [get_ports {ddr4_rtl_1_adr[0]}]
|
||||
set_property PACKAGE_PIN G25 [get_ports {ddr4_rtl_1_adr[1]}]
|
||||
set_property PACKAGE_PIN G20 [get_ports {ddr4_rtl_1_adr[2]}]
|
||||
set_property PACKAGE_PIN G21 [get_ports {ddr4_rtl_1_adr[3]}]
|
||||
set_property PACKAGE_PIN J24 [get_ports {ddr4_rtl_1_adr[4]}]
|
||||
set_property PACKAGE_PIN H24 [get_ports {ddr4_rtl_1_adr[5]}]
|
||||
set_property PACKAGE_PIN J21 [get_ports {ddr4_rtl_1_adr[6]}]
|
||||
set_property PACKAGE_PIN H21 [get_ports {ddr4_rtl_1_adr[7]}]
|
||||
set_property PACKAGE_PIN J22 [get_ports {ddr4_rtl_1_adr[8]}]
|
||||
set_property PACKAGE_PIN H22 [get_ports {ddr4_rtl_1_adr[9]}]
|
||||
set_property PACKAGE_PIN J20 [get_ports {ddr4_rtl_1_adr[10]}]
|
||||
set_property PACKAGE_PIN N21 [get_ports {ddr4_rtl_1_adr[11]}]
|
||||
set_property PACKAGE_PIN M21 [get_ports {ddr4_rtl_1_adr[12]}]
|
||||
set_property PACKAGE_PIN K23 [get_ports {ddr4_rtl_1_adr[13]}]
|
||||
set_property PACKAGE_PIN K24 [get_ports {ddr4_rtl_1_adr[14]}]
|
||||
set_property PACKAGE_PIN L21 [get_ports {ddr4_rtl_1_adr[15]}]
|
||||
set_property PACKAGE_PIN M20 [get_ports {ddr4_rtl_1_adr[16]}]
|
||||
set_property PACKAGE_PIN E20 [get_ports {ddr4_rtl_1_dq[0]}]
|
||||
set_property PACKAGE_PIN D16 [get_ports {ddr4_rtl_1_dq[1]}]
|
||||
set_property PACKAGE_PIN G18 [get_ports {ddr4_rtl_1_dq[2]}]
|
||||
set_property PACKAGE_PIN E17 [get_ports {ddr4_rtl_1_dq[3]}]
|
||||
set_property PACKAGE_PIN G19 [get_ports {ddr4_rtl_1_dq[4]}]
|
||||
set_property PACKAGE_PIN F18 [get_ports {ddr4_rtl_1_dq[5]}]
|
||||
set_property PACKAGE_PIN F20 [get_ports {ddr4_rtl_1_dq[6]}]
|
||||
set_property PACKAGE_PIN D17 [get_ports {ddr4_rtl_1_dq[7]}]
|
||||
set_property PACKAGE_PIN B19 [get_ports {ddr4_rtl_1_dq[8]}]
|
||||
set_property PACKAGE_PIN A16 [get_ports {ddr4_rtl_1_dq[9]}]
|
||||
set_property PACKAGE_PIN B20 [get_ports {ddr4_rtl_1_dq[10]}]
|
||||
set_property PACKAGE_PIN C17 [get_ports {ddr4_rtl_1_dq[11]}]
|
||||
set_property PACKAGE_PIN A20 [get_ports {ddr4_rtl_1_dq[12]}]
|
||||
set_property PACKAGE_PIN B16 [get_ports {ddr4_rtl_1_dq[13]}]
|
||||
set_property PACKAGE_PIN B18 [get_ports {ddr4_rtl_1_dq[14]}]
|
||||
set_property PACKAGE_PIN C16 [get_ports {ddr4_rtl_1_dq[15]}]
|
||||
set_property PACKAGE_PIN B25 [get_ports {ddr4_rtl_1_dq[16]}]
|
||||
set_property PACKAGE_PIN C21 [get_ports {ddr4_rtl_1_dq[17]}]
|
||||
set_property PACKAGE_PIN B24 [get_ports {ddr4_rtl_1_dq[18]}]
|
||||
set_property PACKAGE_PIN C22 [get_ports {ddr4_rtl_1_dq[19]}]
|
||||
set_property PACKAGE_PIN B26 [get_ports {ddr4_rtl_1_dq[20]}]
|
||||
set_property PACKAGE_PIN A21 [get_ports {ddr4_rtl_1_dq[21]}]
|
||||
set_property PACKAGE_PIN B21 [get_ports {ddr4_rtl_1_dq[23]}]
|
||||
set_property PACKAGE_PIN B23 [get_ports {ddr4_rtl_1_dq[22]}]
|
||||
set_property PACKAGE_PIN E23 [get_ports {ddr4_rtl_1_dq[24]}]
|
||||
set_property PACKAGE_PIN F21 [get_ports {ddr4_rtl_1_dq[25]}]
|
||||
set_property PACKAGE_PIN F23 [get_ports {ddr4_rtl_1_dq[26]}]
|
||||
set_property PACKAGE_PIN F22 [get_ports {ddr4_rtl_1_dq[27]}]
|
||||
set_property PACKAGE_PIN E25 [get_ports {ddr4_rtl_1_dq[28]}]
|
||||
set_property PACKAGE_PIN D22 [get_ports {ddr4_rtl_1_dq[29]}]
|
||||
set_property PACKAGE_PIN F25 [get_ports {ddr4_rtl_1_dq[30]}]
|
||||
set_property PACKAGE_PIN D21 [get_ports {ddr4_rtl_1_dq[31]}]
|
||||
set_property PACKAGE_PIN E19 [get_ports {ddr4_rtl_1_dqs_t[0]}]
|
||||
set_property PACKAGE_PIN A18 [get_ports {ddr4_rtl_1_dqs_t[1]}]
|
||||
set_property PACKAGE_PIN A25 [get_ports {ddr4_rtl_1_dqs_t[2]}]
|
||||
set_property PACKAGE_PIN D24 [get_ports {ddr4_rtl_1_dqs_t[3]}]
|
||||
set_property PACKAGE_PIN L22 [get_ports {ddr4_rtl_1_ba[0]}]
|
||||
set_property PACKAGE_PIN L23 [get_ports {ddr4_rtl_1_ba[1]}]
|
||||
set_property PACKAGE_PIN L20 [get_ports {ddr4_rtl_1_bg[0]}]
|
||||
set_property PACKAGE_PIN N22 [get_ports {ddr4_rtl_1_ck_t[0]}]
|
||||
set_property PACKAGE_PIN D25 [get_ports {ddr4_rtl_1_odt[0]}]
|
||||
set_property PACKAGE_PIN F17 [get_ports {ddr4_rtl_1_dm_n[0]}]
|
||||
set_property PACKAGE_PIN C19 [get_ports {ddr4_rtl_1_dm_n[1]}]
|
||||
set_property PACKAGE_PIN A22 [get_ports {ddr4_rtl_1_dm_n[2]}]
|
||||
set_property PACKAGE_PIN E24 [get_ports {ddr4_rtl_1_dm_n[3]}]
|
||||
set_property PACKAGE_PIN A23 [get_ports {ddr4_rtl_1_cs_n[0]}]
|
||||
set_property PACKAGE_PIN E22 [get_ports ddr4_rtl_1_act_n]
|
||||
set_property PACKAGE_PIN K22 [get_ports {ddr4_rtl_1_cke[0]}]
|
||||
set_property PACKAGE_PIN D20 [get_ports ddr4_rtl_1_reset_n]
|
||||
|
||||
set_property -dict {PACKAGE_PIN H23 IOSTANDARD LVDS} [get_ports ddr4_ref_1_clk_p]
|
||||
set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_par]
|
||||
set_property -dict {PACKAGE_PIN D19 IOSTANDARD LVCMOS12} [get_ports ddr4_rtl_1_alert_n]
|
||||
|
||||
set_property PACKAGE_PIN N12 [get_ports ref_clk_a_p];
|
||||
set_property PACKAGE_PIN N11 [get_ports ref_clk_a_n];
|
||||
|
||||
set_property PACKAGE_PIN D2 [get_ports {rx_data_a_p[0]}]
|
||||
set_property PACKAGE_PIN D1 [get_ports {rx_data_a_n[0]}]
|
||||
set_property PACKAGE_PIN D6 [get_ports {tx_data_a_p[0]}]
|
||||
set_property PACKAGE_PIN D5 [get_ports {tx_data_a_n[0]}]
|
||||
set_property PACKAGE_PIN C4 [get_ports {rx_data_a_p[1]}]
|
||||
set_property PACKAGE_PIN C3 [get_ports {rx_data_a_n[1]}]
|
||||
set_property PACKAGE_PIN C8 [get_ports {tx_data_a_p[1]}]
|
||||
set_property PACKAGE_PIN C7 [get_ports {tx_data_a_n[1]}]
|
||||
set_property PACKAGE_PIN B2 [get_ports {rx_data_a_p[2]}]
|
||||
set_property PACKAGE_PIN B1 [get_ports {rx_data_a_n[2]}]
|
||||
set_property PACKAGE_PIN B6 [get_ports {tx_data_a_p[2]}]
|
||||
set_property PACKAGE_PIN B5 [get_ports {tx_data_a_n[2]}]
|
||||
set_property PACKAGE_PIN A4 [get_ports {rx_data_a_p[3]}]
|
||||
set_property PACKAGE_PIN A3 [get_ports {rx_data_a_n[3]}]
|
||||
set_property PACKAGE_PIN A8 [get_ports {tx_data_a_p[3]}]
|
||||
set_property PACKAGE_PIN A7 [get_ports {tx_data_a_n[3]}]
|
||||
|
||||
set_property PACKAGE_PIN R12 [get_ports ref_clk_b_p]
|
||||
set_property PACKAGE_PIN R11 [get_ports ref_clk_b_n]
|
||||
|
||||
set_property PACKAGE_PIN H2 [get_ports {rx_data_b_p[0]}]
|
||||
set_property PACKAGE_PIN H1 [get_ports {rx_data_b_n[0]}]
|
||||
set_property PACKAGE_PIN H6 [get_ports {tx_data_b_p[0]}]
|
||||
set_property PACKAGE_PIN H5 [get_ports {tx_data_b_n[0]}]
|
||||
set_property PACKAGE_PIN G4 [get_ports {rx_data_b_p[1]}]
|
||||
set_property PACKAGE_PIN G3 [get_ports {rx_data_b_n[1]}]
|
||||
set_property PACKAGE_PIN G8 [get_ports {tx_data_b_p[1]}]
|
||||
set_property PACKAGE_PIN G7 [get_ports {tx_data_b_n[1]}]
|
||||
set_property PACKAGE_PIN F2 [get_ports {rx_data_b_p[2]}]
|
||||
set_property PACKAGE_PIN F1 [get_ports {rx_data_b_n[2]}]
|
||||
set_property PACKAGE_PIN F6 [get_ports {tx_data_b_p[2]}]
|
||||
set_property PACKAGE_PIN F5 [get_ports {tx_data_b_n[2]}]
|
||||
set_property PACKAGE_PIN E4 [get_ports {rx_data_b_p[3]}]
|
||||
set_property PACKAGE_PIN E3 [get_ports {rx_data_b_n[3]}]
|
||||
set_property PACKAGE_PIN E8 [get_ports {tx_data_b_p[3]}]
|
||||
set_property PACKAGE_PIN E7 [get_ports {tx_data_b_n[3]}]
|
||||
|
||||
# Core clocks (BANK 66, can be used other clock pins from the bank)
|
||||
set_property -dict {PACKAGE_PIN AU6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_a_p]
|
||||
set_property -dict {PACKAGE_PIN AV6 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_a_n]
|
||||
set_property -dict {PACKAGE_PIN AV8 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_b_p]
|
||||
set_property -dict {PACKAGE_PIN AV7 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports core_clk_b_n]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AT2 IOSTANDARD LVDS} [get_ports rx_sync_a_n]
|
||||
set_property -dict {PACKAGE_PIN AR2 IOSTANDARD LVDS} [get_ports rx_sync_a_p]
|
||||
set_property -dict {PACKAGE_PIN AT18 IOSTANDARD LVDS} [get_ports rx_os_sync_a_n]
|
||||
set_property -dict {PACKAGE_PIN AR18 IOSTANDARD LVDS} [get_ports rx_os_sync_a_p]
|
||||
set_property -dict {PACKAGE_PIN AV3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_n]
|
||||
set_property -dict {PACKAGE_PIN AU3 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_p]
|
||||
set_property -dict {PACKAGE_PIN AW2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_1_n]
|
||||
set_property -dict {PACKAGE_PIN AV2 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_a_1_p]
|
||||
set_property -dict {PACKAGE_PIN AU1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_a_n]
|
||||
set_property -dict {PACKAGE_PIN AT1 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_a_p]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AR3 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_a]
|
||||
set_property -dict {PACKAGE_PIN AT3 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_a]
|
||||
set_property -dict {PACKAGE_PIN AP2 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_a]
|
||||
set_property -dict {PACKAGE_PIN AP1 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_a]
|
||||
set_property -dict {PACKAGE_PIN AL11 IOSTANDARD LVCMOS18} [get_ports adrv9009_test_a]
|
||||
set_property -dict {PACKAGE_PIN AV9 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_a]
|
||||
set_property -dict {PACKAGE_PIN AW9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_a]
|
||||
set_property -dict {PACKAGE_PIN AW7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_a]
|
||||
set_property -dict {PACKAGE_PIN AW6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_a]
|
||||
set_property -dict {PACKAGE_PIN AU5 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_a]
|
||||
set_property -dict {PACKAGE_PIN AU4 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_a]
|
||||
set_property -dict {PACKAGE_PIN AV4 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_a]
|
||||
set_property -dict {PACKAGE_PIN AW4 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_a]
|
||||
set_property -dict {PACKAGE_PIN AT8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_a]
|
||||
set_property -dict {PACKAGE_PIN AT7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_a]
|
||||
set_property -dict {PACKAGE_PIN AT6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15_a]
|
||||
set_property -dict {PACKAGE_PIN AT5 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_a]
|
||||
set_property -dict {PACKAGE_PIN AU9 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09_a]
|
||||
set_property -dict {PACKAGE_PIN AU8 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10_a]
|
||||
set_property -dict {PACKAGE_PIN AR5 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11_a]
|
||||
set_property -dict {PACKAGE_PIN AR4 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12_a]
|
||||
set_property -dict {PACKAGE_PIN AP7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14_a]
|
||||
set_property -dict {PACKAGE_PIN AR7 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13_a]
|
||||
set_property -dict {PACKAGE_PIN AP5 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17_a]
|
||||
set_property -dict {PACKAGE_PIN AP4 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16_a]
|
||||
set_property -dict {PACKAGE_PIN AP6 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18_a]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AJ20 IOSTANDARD LVDS} [get_ports rx_sync_b_n]
|
||||
set_property -dict {PACKAGE_PIN AJ21 IOSTANDARD LVDS} [get_ports rx_sync_b_p]
|
||||
set_property -dict {PACKAGE_PIN AT16 IOSTANDARD LVDS} [get_ports rx_os_sync_b_n]
|
||||
set_property -dict {PACKAGE_PIN AT17 IOSTANDARD LVDS} [get_ports rx_os_sync_b_p]
|
||||
set_property -dict {PACKAGE_PIN AL20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_n]
|
||||
set_property -dict {PACKAGE_PIN AK20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_p]
|
||||
set_property -dict {PACKAGE_PIN AG19 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_1_n]
|
||||
set_property -dict {PACKAGE_PIN AG20 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports tx_sync_b_1_p]
|
||||
set_property -dict {PACKAGE_PIN AP10 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_b_n]
|
||||
set_property -dict {PACKAGE_PIN AP11 IOSTANDARD LVDS DIFF_TERM_ADV TERM_100} [get_ports sysref_b_p]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AW5 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx1_enable_b]
|
||||
set_property -dict {PACKAGE_PIN AR8 IOSTANDARD LVCMOS18} [get_ports adrv9009_tx2_enable_b]
|
||||
set_property -dict {PACKAGE_PIN AT20 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx1_enable_b]
|
||||
set_property -dict {PACKAGE_PIN AM20 IOSTANDARD LVCMOS18} [get_ports adrv9009_rx2_enable_b]
|
||||
set_property -dict {PACKAGE_PIN AR17 IOSTANDARD LVCMOS18} [get_ports adrv9009_test_b]
|
||||
set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVCMOS18} [get_ports adrv9009_reset_b_b]
|
||||
set_property -dict {PACKAGE_PIN AK10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpint_b]
|
||||
set_property -dict {PACKAGE_PIN AM11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_00_b]
|
||||
set_property -dict {PACKAGE_PIN AN11 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_01_b]
|
||||
set_property -dict {PACKAGE_PIN AU18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_02_b]
|
||||
set_property -dict {PACKAGE_PIN AV18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_03_b]
|
||||
set_property -dict {PACKAGE_PIN AV21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_04_b]
|
||||
set_property -dict {PACKAGE_PIN AW21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_05_b]
|
||||
set_property -dict {PACKAGE_PIN AV17 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_06_b]
|
||||
set_property -dict {PACKAGE_PIN AW17 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_07_b]
|
||||
set_property -dict {PACKAGE_PIN AW20 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_15_b]
|
||||
set_property -dict {PACKAGE_PIN AW19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_08_b]
|
||||
set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_09_b]
|
||||
set_property -dict {PACKAGE_PIN AW16 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_10_b]
|
||||
set_property -dict {PACKAGE_PIN AU19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_11_b]
|
||||
set_property -dict {PACKAGE_PIN AV19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_12_b]
|
||||
set_property -dict {PACKAGE_PIN AM19 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_14_b]
|
||||
set_property -dict {PACKAGE_PIN AM18 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_13_b]
|
||||
set_property -dict {PACKAGE_PIN AL21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_17_b]
|
||||
set_property -dict {PACKAGE_PIN AM21 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_16_b]
|
||||
set_property -dict {PACKAGE_PIN AL10 IOSTANDARD LVCMOS18} [get_ports adrv9009_gpio_18_b]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AH19 IOSTANDARD LVCMOS18} [get_ports hmc7044_reset]
|
||||
set_property -dict {PACKAGE_PIN AJ19 IOSTANDARD LVCMOS18} [get_ports hmc7044_sync]
|
||||
set_property -dict {PACKAGE_PIN AK19 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_1]
|
||||
set_property -dict {PACKAGE_PIN AK18 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_2]
|
||||
set_property -dict {PACKAGE_PIN AG21 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_3]
|
||||
set_property -dict {PACKAGE_PIN AH21 IOSTANDARD LVCMOS18} [get_ports hmc7044_gpio_4]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AL18 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009_a]
|
||||
set_property -dict {PACKAGE_PIN AL17 IOSTANDARD LVCMOS18} [get_ports spi_csn_adrv9009_b]
|
||||
set_property -dict {PACKAGE_PIN AU20 IOSTANDARD LVCMOS18} [get_ports spi_csn_hmc7044]
|
||||
|
||||
create_clock -name tx_dev_clk -period 4.00 [get_ports core_clk_a_p]
|
||||
create_clock -name rx_dev_clk -period 4.00 [get_ports core_clk_b_p]
|
||||
create_clock -name jesd_tx_ref_clk -period 4.00 [get_ports ref_clk_a_p]
|
||||
create_clock -name jesd_rx_ref_clk -period 4.00 [get_ports ref_clk_b_p]
|
||||
|
||||
set_input_delay -clock rx_dev_clk -max 4 [get_ports sysref_b_p];
|
||||
set_input_delay -clock rx_dev_clk -min 4 [get_ports sysref_b_p];
|
||||
|
||||
set_input_delay -clock tx_dev_clk -max 4 [get_ports sysref_a_p];
|
||||
set_input_delay -clock tx_dev_clk -min 4 [get_ports sysref_a_p];
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2019 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsibilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module adrv9009_zu11eg_som_spi (
|
||||
|
||||
input [ 7:0] spi_csn,
|
||||
input spi_clk,
|
||||
input spi_mosi,
|
||||
input spi_miso_i,
|
||||
output spi_miso_o,
|
||||
|
||||
inout spi_sdio);
|
||||
|
||||
// internal registers
|
||||
|
||||
reg [ 5:0] spi_count = 'd0;
|
||||
reg spi_rd_wr_n = 'd0;
|
||||
reg spi_enable = 'd0;
|
||||
|
||||
// internal signals
|
||||
|
||||
wire spi_csn_s;
|
||||
wire spi_enable_s;
|
||||
wire spi_miso_io;
|
||||
|
||||
// check on rising edge and change on falling edge
|
||||
|
||||
assign spi_csn_s = & spi_csn;
|
||||
assign spi_enable_s = spi_enable & (~spi_csn[2] | ~spi_csn[3]);
|
||||
|
||||
always @(posedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_count <= 6'd0;
|
||||
spi_rd_wr_n <= 1'd0;
|
||||
end else begin
|
||||
spi_count <= (spi_count < 6'h3f) ? spi_count + 1'b1 : spi_count;
|
||||
if (spi_count == 6'd0) begin
|
||||
spi_rd_wr_n <= spi_mosi;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
always @(negedge spi_clk or posedge spi_csn_s) begin
|
||||
if (spi_csn_s == 1'b1) begin
|
||||
spi_enable <= 1'b0;
|
||||
end else begin
|
||||
if (spi_count == 6'd16) begin
|
||||
spi_enable <= spi_rd_wr_n;
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
// io buffer
|
||||
|
||||
IOBUF i_iobuf_sdio (
|
||||
.T (spi_enable_s),
|
||||
.I (spi_mosi),
|
||||
.O (spi_miso_io),
|
||||
.IO (spi_sdio));
|
||||
|
||||
assign spi_miso_o = spi_enable_s ? spi_miso_io : spi_miso_i;
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
|
||||
add_files -fileset constrs_1 -norecurse ./carrier_constr.xdc
|
||||
|
|
@ -0,0 +1,45 @@
|
|||
|
||||
set_property -dict {PACKAGE_PIN AT13 IOSTANDARD LVCMOS18} [get_ports fan_tach]
|
||||
set_property -dict {PACKAGE_PIN AR13 IOSTANDARD LVCMOS18} [get_ports fan_pwrm]
|
||||
set_property -dict {PACKAGE_PIN AR12 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_in]
|
||||
set_property -dict {PACKAGE_PIN AP12 IOSTANDARD LVCMOS18} [get_ports i2s_sdata_out]
|
||||
set_property -dict {PACKAGE_PIN AP15 IOSTANDARD LVCMOS18} [get_ports i2s_mclk]
|
||||
set_property -dict {PACKAGE_PIN AN16 IOSTANDARD LVCMOS18} [get_ports i2s_bclk]
|
||||
set_property -dict {PACKAGE_PIN AT10 IOSTANDARD LVCMOS18} [get_ports i2s_lrclk]
|
||||
set_property -dict {PACKAGE_PIN AW12 IOSTANDARD LVCMOS18} [get_ports pmod0_d0]
|
||||
set_property -dict {PACKAGE_PIN AV12 IOSTANDARD LVCMOS18} [get_ports pmod0_d1]
|
||||
set_property -dict {PACKAGE_PIN AU13 IOSTANDARD LVCMOS18} [get_ports pmod0_d2]
|
||||
set_property -dict {PACKAGE_PIN AU14 IOSTANDARD LVCMOS18} [get_ports pmod0_d3]
|
||||
set_property -dict {PACKAGE_PIN AM13 IOSTANDARD LVCMOS18} [get_ports pmod0_d4]
|
||||
set_property -dict {PACKAGE_PIN AL13 IOSTANDARD LVCMOS18} [get_ports pmod0_d5]
|
||||
set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVCMOS18} [get_ports pmod0_d6]
|
||||
set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVCMOS18} [get_ports pmod0_d7]
|
||||
set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVCMOS18} [get_ports led_gpio_0]
|
||||
set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVCMOS18} [get_ports led_gpio_1]
|
||||
set_property -dict {PACKAGE_PIN AJ12 IOSTANDARD LVCMOS18} [get_ports led_gpio_2]
|
||||
set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS18} [get_ports led_gpio_3]
|
||||
set_property -dict {PACKAGE_PIN AW11 IOSTANDARD LVCMOS18} [get_ports dip_gpio_0]
|
||||
set_property -dict {PACKAGE_PIN AW10 IOSTANDARD LVCMOS18} [get_ports dip_gpio_1]
|
||||
set_property -dict {PACKAGE_PIN AN13 IOSTANDARD LVCMOS18} [get_ports dip_gpio_2]
|
||||
set_property -dict {PACKAGE_PIN AN12 IOSTANDARD LVCMOS18} [get_ports dip_gpio_3]
|
||||
set_property -dict {PACKAGE_PIN AV13 IOSTANDARD LVCMOS18} [get_ports pb_gpio_0]
|
||||
set_property -dict {PACKAGE_PIN AV14 IOSTANDARD LVCMOS18} [get_ports pb_gpio_1]
|
||||
set_property -dict {PACKAGE_PIN AT11 IOSTANDARD LVCMOS18} [get_ports pb_gpio_2]
|
||||
set_property -dict {PACKAGE_PIN AT12 IOSTANDARD LVCMOS18} [get_ports pb_gpio_3]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AR19 IOSTANDARD LVCMOS18} [get_ports resetb_ad9545]
|
||||
set_property -dict {PACKAGE_PIN AP19 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_reset]
|
||||
set_property -dict {PACKAGE_PIN AP20 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_gpio_1]
|
||||
set_property -dict {PACKAGE_PIN AR20 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_gpio_2]
|
||||
set_property -dict {PACKAGE_PIN AP9 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_gpio_3]
|
||||
set_property -dict {PACKAGE_PIN AP8 IOSTANDARD LVCMOS18} [get_ports hmc7044_car_gpio_4]
|
||||
set_property -dict {PACKAGE_PIN AR10 IOSTANDARD LVCMOS18} [get_ports spi_csn_hmc7044_car]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AT21 IOSTANDARD LVCMOS18} [get_ports i2c0_scl]
|
||||
set_property -dict {PACKAGE_PIN AU21 IOSTANDARD LVCMOS18} [get_ports i2c0_sda]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN19 IOSTANDARD LVCMOS18} [get_ports i2c1_scl]
|
||||
set_property -dict {PACKAGE_PIN AN18 IOSTANDARD LVCMOS18} [get_ports i2c1_sda]
|
||||
|
||||
set_property -dict {PACKAGE_PIN AN17 IOSTANDARD LVDS} [get_ports oscout_p]
|
||||
set_property -dict {PACKAGE_PIN AP17 IOSTANDARD LVDS} [get_ports oscout_n]
|
||||
|
|
@ -0,0 +1,143 @@
|
|||
# create board design
|
||||
# default ports
|
||||
|
||||
create_bd_port -dir O -from 2 -to 0 spi0_csn
|
||||
create_bd_port -dir O spi0_sclk
|
||||
create_bd_port -dir O spi0_mosi
|
||||
create_bd_port -dir I spi0_miso
|
||||
|
||||
create_bd_port -dir I -from 94 -to 0 gpio_i
|
||||
create_bd_port -dir O -from 94 -to 0 gpio_o
|
||||
create_bd_port -dir O -from 94 -to 0 gpio_t
|
||||
|
||||
# instance: sys_ps8
|
||||
|
||||
ad_ip_instance zynq_ultra_ps_e sys_ps8
|
||||
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP0 0
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP1 0
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__M_AXI_GP2 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__MAXIGP2__DATA_WIDTH 32
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL0_ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__SRCSEL {IOPLL}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL0_REF_CTRL__FREQMHZ 100
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__FPGA_PL1_ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__SRCSEL {IOPLL}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__PL1_REF_CTRL__FREQMHZ 200
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ0 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USE__IRQ1 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO_EMIO__PERIPHERAL__ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__PERIPHERAL__IO {EMIO}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS1__ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SPI0__GRP_SS2__ENABLE 1
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__CRL_APB__SPI0_REF_CTRL__FREQMHZ 100
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__I2C0__PERIPHERAL__IO {MIO 14 .. 15}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__UART1__PERIPHERAL__IO {MIO 16 .. 17}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SD1__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__SWDT1__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC1__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC2__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__TTC3__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USB0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__USB3_0__PERIPHERAL__IO {GT Lane1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET0__PERIPHERAL__IO {GT Lane0}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {0}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {0}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__PMU__PERIPHERAL__ENABLE {0}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__MODE {Dual Parallel}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__QSPI__PERIPHERAL__DATA_MODE {x4}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DISPLAYPORT__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DPAUX__PERIPHERAL__IO {MIO 27 .. 30}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__ENET3__GRP_MDIO__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.SUBPRESET1 {DDR4_MICRON_MT40A256M16GE_083E}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BUS_WIDTH {64 Bit}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__DRAM_WIDTH {16 Bits}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__BG_ADDR_COUNT {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__PARITY_ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__DDRC__ECC {Enabled}
|
||||
set_property -dict [list CONFIG.PSU__DDRC__ROW_ADDR_COUNT {16} CONFIG.PSU__DDRC__DEVICE_CAPACITY {8192 MBits} ] [get_bd_cells sys_ps8]
|
||||
set_property -dict [list CONFIG.PSU__I2C1__PERIPHERAL__ENABLE {1} CONFIG.PSU__I2C1__PERIPHERAL__IO {MIO 32 .. 33}] [get_bd_cells sys_ps8]
|
||||
set_property -dict [list CONFIG.PSU__CRF_APB__DP_VIDEO_REF_CTRL__SRCSEL {VPLL} CONFIG.PSU__CRF_APB__DP_AUDIO_REF_CTRL__SRCSEL {DPLL} CONFIG.PSU__CRF_APB__DP_STC_REF_CTRL__SRCSEL {DPLL}] [get_bd_cells sys_ps8]
|
||||
set_property -dict [list CONFIG.PSU__CRF_APB__TOPSW_MAIN_CTRL__SRCSEL {APLL}] [get_bd_cells sys_ps8]
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO0_MIO__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO1_MIO__PERIPHERAL__ENABLE {1}
|
||||
ad_ip_parameter sys_ps8 CONFIG.PSU__GPIO2_MIO__PERIPHERAL__ENABLE {1}
|
||||
|
||||
ad_ip_instance proc_sys_reset sys_rstgen
|
||||
ad_ip_parameter sys_rstgen CONFIG.C_EXT_RST_WIDTH 1
|
||||
|
||||
# system reset/clock definitions
|
||||
|
||||
ad_connect sys_cpu_clk sys_ps8/pl_clk0
|
||||
ad_connect sys_200m_clk sys_ps8/pl_clk1
|
||||
ad_connect sys_cpu_reset sys_rstgen/peripheral_reset
|
||||
ad_connect sys_cpu_resetn sys_rstgen/peripheral_aresetn
|
||||
ad_connect sys_cpu_clk sys_rstgen/slowest_sync_clk
|
||||
ad_connect sys_ps8/pl_resetn0 sys_rstgen/ext_reset_in
|
||||
|
||||
# gpio
|
||||
|
||||
ad_connect gpio_i sys_ps8/emio_gpio_i
|
||||
ad_connect gpio_o sys_ps8/emio_gpio_o
|
||||
ad_connect gpio_t sys_ps8/emio_gpio_t
|
||||
|
||||
# add 1 bit GND signal
|
||||
ad_ip_instance xlconstant GND_1_bit
|
||||
ad_ip_parameter GND_1_bit CONFIG.CONST_VAL {0}
|
||||
|
||||
# spi
|
||||
|
||||
ad_ip_instance xlconcat spi0_csn_concat
|
||||
ad_ip_parameter spi0_csn_concat CONFIG.NUM_PORTS 3
|
||||
ad_connect sys_ps8/emio_spi0_ss_o_n spi0_csn_concat/In0
|
||||
ad_connect sys_ps8/emio_spi0_ss1_o_n spi0_csn_concat/In1
|
||||
ad_connect sys_ps8/emio_spi0_ss2_o_n spi0_csn_concat/In2
|
||||
ad_connect spi0_csn_concat/dout spi0_csn
|
||||
ad_connect sys_ps8/emio_spi0_sclk_o spi0_sclk
|
||||
ad_connect sys_ps8/emio_spi0_m_o spi0_mosi
|
||||
ad_connect sys_ps8/emio_spi0_m_i spi0_miso
|
||||
ad_connect sys_ps8/emio_spi0_ss_i_n VCC
|
||||
ad_connect sys_ps8/emio_spi0_sclk_i GND_1_bit/dout
|
||||
ad_connect sys_ps8/emio_spi0_s_i GND_1_bit/dout
|
||||
|
||||
# interrupts
|
||||
|
||||
ad_ip_instance xlconcat sys_concat_intc_0
|
||||
ad_ip_parameter sys_concat_intc_0 CONFIG.NUM_PORTS 8
|
||||
|
||||
ad_ip_instance xlconcat sys_concat_intc_1
|
||||
ad_ip_parameter sys_concat_intc_1 CONFIG.NUM_PORTS 8
|
||||
|
||||
ad_connect sys_concat_intc_0/dout sys_ps8/pl_ps_irq0
|
||||
ad_connect sys_concat_intc_1/dout sys_ps8/pl_ps_irq1
|
||||
|
||||
ad_connect sys_concat_intc_1/In7 GND
|
||||
ad_connect sys_concat_intc_1/In6 GND
|
||||
ad_connect sys_concat_intc_1/In5 GND
|
||||
ad_connect sys_concat_intc_1/In4 GND
|
||||
ad_connect sys_concat_intc_1/In3 GND
|
||||
ad_connect sys_concat_intc_1/In2 GND
|
||||
ad_connect sys_concat_intc_1/In1 GND
|
||||
ad_connect sys_concat_intc_1/In0 GND
|
||||
ad_connect sys_concat_intc_0/In7 GND
|
||||
ad_connect sys_concat_intc_0/In6 GND
|
||||
ad_connect sys_concat_intc_0/In5 GND
|
||||
ad_connect sys_concat_intc_0/In4 GND
|
||||
ad_connect sys_concat_intc_0/In3 GND
|
||||
ad_connect sys_concat_intc_0/In2 GND
|
||||
ad_connect sys_concat_intc_0/In1 GND
|
||||
ad_connect sys_concat_intc_0/In0 GND
|
||||
|
||||
connect_bd_net [get_bd_pins sys_ps8/maxihpm0_lpd_aclk] [get_bd_pins sys_ps8/pl_clk0]
|
||||
|
||||
source adrv9009_zu11eg_som_bd.tcl
|
||||
source carrier_bd.tcl
|
||||
|
|
@ -0,0 +1,4 @@
|
|||
|
||||
set_property -dict {PACKAGE_PIN AN21 IOSTANDARD LVCMOS18} [get_ports spi_clk]
|
||||
set_property -dict {PACKAGE_PIN AP21 IOSTANDARD LVCMOS18} [get_ports spi_sdio]
|
||||
set_property -dict {PACKAGE_PIN AR9 IOSTANDARD LVCMOS18} [get_ports spi_miso]
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
|
||||
source ../scripts/adi_env.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_project.tcl
|
||||
source $ad_hdl_dir/projects/scripts/adi_board.tcl
|
||||
|
||||
set p_device "xczu11eg-ffvf1517-1-e"
|
||||
set sys_zynq 2
|
||||
|
||||
adi_project_xilinx adrv9009_zu11eg_som
|
||||
adi_project_files adrv9009_zu11eg_som [list \
|
||||
"system_top.v" \
|
||||
"adrv9009_zu11eg_som_spi.v" \
|
||||
"system_constr.xdc" \
|
||||
"$ad_hdl_dir/library/xilinx/common/ad_iobuf.v" ]
|
||||
|
||||
adi_project_run adrv9009_zu11eg_som
|
||||
|
|
@ -0,0 +1,504 @@
|
|||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
// Copyright 2014 - 2017 (c) Analog Devices, Inc. All rights reserved.
|
||||
//
|
||||
// In this HDL repository, there are many different and unique modules, consisting
|
||||
// of various HDL (Verilog or VHDL) components. The individual modules are
|
||||
// developed independently, and may be accompanied by separate and unique license
|
||||
// terms.
|
||||
//
|
||||
// The user should read each of these license terms, and understand the
|
||||
// freedoms and responsabilities that he or she has by using this source/core.
|
||||
//
|
||||
// This core is distributed in the hope that it will be useful, but WITHOUT ANY
|
||||
// WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR
|
||||
// A PARTICULAR PURPOSE.
|
||||
//
|
||||
// Redistribution and use of source or resulting binaries, with or without modification
|
||||
// of this file, are permitted under one of the following two license terms:
|
||||
//
|
||||
// 1. The GNU General Public License version 2 as published by the
|
||||
// Free Software Foundation, which can be found in the top level directory
|
||||
// of this repository (LICENSE_GPL2), and also online at:
|
||||
// <https://www.gnu.org/licenses/old-licenses/gpl-2.0.html>
|
||||
//
|
||||
// OR
|
||||
//
|
||||
// 2. An ADI specific BSD license, which can be found in the top level directory
|
||||
// of this repository (LICENSE_ADIBSD), and also on-line at:
|
||||
// https://github.com/analogdevicesinc/hdl/blob/master/LICENSE_ADIBSD
|
||||
// This will allow to generate bit files and not release the source code,
|
||||
// as long as it attaches to an ADI device.
|
||||
//
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
module system_top (
|
||||
|
||||
output fan_tach,
|
||||
output fan_pwrm,
|
||||
input i2s_sdata_in,
|
||||
output i2s_sdata_out,
|
||||
output i2s_mclk,
|
||||
output i2s_bclk,
|
||||
output i2s_lrclk,
|
||||
inout pmod0_d0,
|
||||
inout pmod0_d1,
|
||||
inout pmod0_d2,
|
||||
inout pmod0_d3,
|
||||
inout pmod0_d4,
|
||||
inout pmod0_d5,
|
||||
inout pmod0_d6,
|
||||
inout pmod0_d7,
|
||||
output led_gpio_0,
|
||||
output led_gpio_1,
|
||||
output led_gpio_2,
|
||||
output led_gpio_3,
|
||||
inout dip_gpio_0,
|
||||
inout dip_gpio_1,
|
||||
inout dip_gpio_2,
|
||||
inout dip_gpio_3,
|
||||
inout pb_gpio_0,
|
||||
inout pb_gpio_1,
|
||||
inout pb_gpio_2,
|
||||
inout pb_gpio_3,
|
||||
output resetb_ad9545,
|
||||
output hmc7044_car_reset,
|
||||
inout hmc7044_car_gpio_1,
|
||||
inout hmc7044_car_gpio_2,
|
||||
inout hmc7044_car_gpio_3,
|
||||
inout hmc7044_car_gpio_4,
|
||||
output spi_csn_hmc7044_car,
|
||||
|
||||
inout i2c0_scl,
|
||||
inout i2c0_sda,
|
||||
|
||||
inout i2c1_scl,
|
||||
inout i2c1_sda,
|
||||
|
||||
input oscout_p,
|
||||
input oscout_n,
|
||||
|
||||
input ref_clk_a_p,
|
||||
input ref_clk_a_n,
|
||||
input core_clk_a_p,
|
||||
input core_clk_a_n,
|
||||
input [ 3:0] rx_data_a_p,
|
||||
input [ 3:0] rx_data_a_n,
|
||||
output [ 3:0] tx_data_a_p,
|
||||
output [ 3:0] tx_data_a_n,
|
||||
|
||||
output rx_sync_a_p,
|
||||
output rx_sync_a_n,
|
||||
output rx_os_sync_a_p,
|
||||
output rx_os_sync_a_n,
|
||||
input tx_sync_a_p,
|
||||
input tx_sync_a_n,
|
||||
input tx_sync_a_1_p,
|
||||
input tx_sync_a_1_n,
|
||||
input sysref_a_p,
|
||||
input sysref_a_n,
|
||||
|
||||
inout adrv9009_tx1_enable_a,
|
||||
inout adrv9009_tx2_enable_a,
|
||||
inout adrv9009_rx1_enable_a,
|
||||
inout adrv9009_rx2_enable_a,
|
||||
inout adrv9009_test_a,
|
||||
inout adrv9009_reset_b_a,
|
||||
inout adrv9009_gpint_a,
|
||||
|
||||
inout adrv9009_gpio_00_a,
|
||||
inout adrv9009_gpio_01_a,
|
||||
inout adrv9009_gpio_02_a,
|
||||
inout adrv9009_gpio_03_a,
|
||||
inout adrv9009_gpio_04_a,
|
||||
inout adrv9009_gpio_05_a,
|
||||
inout adrv9009_gpio_06_a,
|
||||
inout adrv9009_gpio_07_a,
|
||||
inout adrv9009_gpio_15_a,
|
||||
inout adrv9009_gpio_08_a,
|
||||
inout adrv9009_gpio_09_a,
|
||||
inout adrv9009_gpio_10_a,
|
||||
inout adrv9009_gpio_11_a,
|
||||
inout adrv9009_gpio_12_a,
|
||||
inout adrv9009_gpio_14_a,
|
||||
inout adrv9009_gpio_13_a,
|
||||
inout adrv9009_gpio_17_a,
|
||||
inout adrv9009_gpio_16_a,
|
||||
inout adrv9009_gpio_18_a,
|
||||
|
||||
input ref_clk_b_p,
|
||||
input ref_clk_b_n,
|
||||
input core_clk_b_p,
|
||||
input core_clk_b_n,
|
||||
input [ 3:0] rx_data_b_p,
|
||||
input [ 3:0] rx_data_b_n,
|
||||
output [ 3:0] tx_data_b_p,
|
||||
output [ 3:0] tx_data_b_n,
|
||||
|
||||
output rx_sync_b_p,
|
||||
output rx_sync_b_n,
|
||||
output rx_os_sync_b_p,
|
||||
output rx_os_sync_b_n,
|
||||
input tx_sync_b_p,
|
||||
input tx_sync_b_n,
|
||||
input tx_sync_b_1_p,
|
||||
input tx_sync_b_1_n,
|
||||
input sysref_b_p,
|
||||
input sysref_b_n,
|
||||
|
||||
inout adrv9009_tx1_enable_b,
|
||||
inout adrv9009_tx2_enable_b,
|
||||
inout adrv9009_rx1_enable_b,
|
||||
inout adrv9009_rx2_enable_b,
|
||||
inout adrv9009_test_b,
|
||||
inout adrv9009_reset_b_b,
|
||||
inout adrv9009_gpint_b,
|
||||
|
||||
inout adrv9009_gpio_00_b,
|
||||
inout adrv9009_gpio_01_b,
|
||||
inout adrv9009_gpio_02_b,
|
||||
inout adrv9009_gpio_03_b,
|
||||
inout adrv9009_gpio_04_b,
|
||||
inout adrv9009_gpio_05_b,
|
||||
inout adrv9009_gpio_06_b,
|
||||
inout adrv9009_gpio_07_b,
|
||||
inout adrv9009_gpio_15_b,
|
||||
inout adrv9009_gpio_08_b,
|
||||
inout adrv9009_gpio_09_b,
|
||||
inout adrv9009_gpio_10_b,
|
||||
inout adrv9009_gpio_11_b,
|
||||
inout adrv9009_gpio_12_b,
|
||||
inout adrv9009_gpio_14_b,
|
||||
inout adrv9009_gpio_13_b,
|
||||
inout adrv9009_gpio_17_b,
|
||||
inout adrv9009_gpio_16_b,
|
||||
inout adrv9009_gpio_18_b,
|
||||
|
||||
output hmc7044_reset,
|
||||
output hmc7044_sync,
|
||||
inout hmc7044_gpio_1,
|
||||
inout hmc7044_gpio_2,
|
||||
inout hmc7044_gpio_3,
|
||||
inout hmc7044_gpio_4,
|
||||
|
||||
output spi_csn_adrv9009_a,
|
||||
output spi_csn_adrv9009_b,
|
||||
output spi_csn_hmc7044,
|
||||
|
||||
input ddr4_ref_1_clk_n,
|
||||
input ddr4_ref_1_clk_p,
|
||||
|
||||
output ddr4_rtl_1_act_n,
|
||||
output [16:0] ddr4_rtl_1_adr,
|
||||
output [1:0] ddr4_rtl_1_ba,
|
||||
output [0:0] ddr4_rtl_1_bg,
|
||||
output [0:0] ddr4_rtl_1_ck_c,
|
||||
output [0:0] ddr4_rtl_1_ck_t,
|
||||
output [0:0] ddr4_rtl_1_cke,
|
||||
output [0:0] ddr4_rtl_1_cs_n,
|
||||
inout [3:0] ddr4_rtl_1_dm_n,
|
||||
inout [31:0] ddr4_rtl_1_dq,
|
||||
inout [3:0] ddr4_rtl_1_dqs_c,
|
||||
inout [3:0] ddr4_rtl_1_dqs_t,
|
||||
output [0:0] ddr4_rtl_1_odt,
|
||||
output ddr4_rtl_1_reset_n,
|
||||
output ddr4_rtl_1_par,
|
||||
input ddr4_rtl_1_alert_n,
|
||||
output spi_clk,
|
||||
inout spi_sdio,
|
||||
input spi_miso
|
||||
);
|
||||
|
||||
// internal signals
|
||||
|
||||
wire [94:0] gpio_i;
|
||||
wire [94:0] gpio_o;
|
||||
wire [94:0] gpio_t;
|
||||
|
||||
wire [2:0] spi_csn;
|
||||
|
||||
wire ref_clk_a;
|
||||
wire core_clk_a;
|
||||
wire rx_sync_rx;
|
||||
wire tx_sync_a;
|
||||
wire sysref_a;
|
||||
wire ref_clk_b;
|
||||
wire core_clk_b;
|
||||
wire rx_sync_obs;
|
||||
wire rx_os_sync_b;
|
||||
wire tx_sync_b;
|
||||
wire sysref_b;
|
||||
wire tx_sync;
|
||||
wire spi_mosi;
|
||||
wire spi0_miso;
|
||||
|
||||
reg [7:0] spi_3_to_8_csn;
|
||||
|
||||
always @(*) begin
|
||||
case (spi_csn)
|
||||
3'h0: spi_3_to_8_csn = 8'b11111110;
|
||||
3'h1: spi_3_to_8_csn = 8'b11111101;
|
||||
3'h2: spi_3_to_8_csn = 8'b11111011;
|
||||
3'h3: spi_3_to_8_csn = 8'b11110111;
|
||||
default: spi_3_to_8_csn = 8'b11111111;
|
||||
endcase
|
||||
end
|
||||
|
||||
assign spi_csn_adrv9009_a = spi_3_to_8_csn[0];
|
||||
assign spi_csn_adrv9009_b = spi_3_to_8_csn[1];
|
||||
assign spi_csn_hmc7044 = spi_3_to_8_csn[2];
|
||||
assign spi_csn_hmc7044_car = spi_3_to_8_csn[3];
|
||||
|
||||
adrv9009_zu11eg_som_spi i_spi (
|
||||
.spi_csn(spi_3_to_8_csn),
|
||||
.spi_clk(spi_clk),
|
||||
.spi_mosi(spi_mosi),
|
||||
.spi_miso_i(spi_miso),
|
||||
.spi_miso_o(spi0_miso),
|
||||
.spi_sdio(spi_sdio));
|
||||
|
||||
assign tx_sync = tx_sync_a & tx_sync_b;
|
||||
|
||||
assign gpio_i[94:90] = gpio_o[94:90];
|
||||
assign gpio_i[31:28] = gpio_o[31:28];
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(58)) i_iobuf (
|
||||
.dio_t ({gpio_t[89:32]}),
|
||||
.dio_i ({gpio_o[89:32]}),
|
||||
.dio_o ({gpio_i[89:32]}),
|
||||
.dio_p ({
|
||||
hmc7044_gpio_4, // 89
|
||||
hmc7044_gpio_3, // 88
|
||||
hmc7044_gpio_1, // 87
|
||||
hmc7044_gpio_2, // 86
|
||||
hmc7044_sync, // 85
|
||||
hmc7044_reset, // 84
|
||||
adrv9009_tx2_enable_b, // 83
|
||||
adrv9009_tx1_enable_b, // 82
|
||||
adrv9009_rx2_enable_b, // 81
|
||||
adrv9009_rx1_enable_b, // 80
|
||||
adrv9009_test_b, // 79
|
||||
adrv9009_reset_b_b, // 78
|
||||
adrv9009_gpint_b, // 77
|
||||
adrv9009_gpio_18_b, // 77
|
||||
adrv9009_gpio_17_b, // 75
|
||||
adrv9009_gpio_16_b, // 74
|
||||
adrv9009_gpio_15_b, // 73
|
||||
adrv9009_gpio_14_b, // 72
|
||||
adrv9009_gpio_13_b, // 71
|
||||
adrv9009_gpio_12_b, // 70
|
||||
adrv9009_gpio_11_b, // 69
|
||||
adrv9009_gpio_10_b, // 68
|
||||
adrv9009_gpio_09_b, // 67
|
||||
adrv9009_gpio_08_b, // 66
|
||||
adrv9009_gpio_07_b, // 65
|
||||
adrv9009_gpio_06_b, // 64
|
||||
adrv9009_gpio_05_b, // 63
|
||||
adrv9009_gpio_04_b, // 62
|
||||
adrv9009_gpio_03_b, // 61
|
||||
adrv9009_gpio_02_b, // 60
|
||||
adrv9009_gpio_01_b, // 58
|
||||
adrv9009_gpio_00_b, // 58
|
||||
adrv9009_tx2_enable_a, // 57
|
||||
adrv9009_tx1_enable_a, // 56
|
||||
adrv9009_rx2_enable_a, // 55
|
||||
adrv9009_rx1_enable_a, // 54
|
||||
adrv9009_test_a, // 53
|
||||
adrv9009_reset_b_a, // 52
|
||||
adrv9009_gpint_a, // 51
|
||||
adrv9009_gpio_18_a, // 50
|
||||
adrv9009_gpio_17_a, // 49
|
||||
adrv9009_gpio_16_a, // 48
|
||||
adrv9009_gpio_15_a, // 47
|
||||
adrv9009_gpio_14_a, // 46
|
||||
adrv9009_gpio_13_a, // 45
|
||||
adrv9009_gpio_12_a, // 44
|
||||
adrv9009_gpio_11_a, // 43
|
||||
adrv9009_gpio_10_a, // 42
|
||||
adrv9009_gpio_09_a, // 41
|
||||
adrv9009_gpio_08_a, // 40
|
||||
adrv9009_gpio_07_a, // 39
|
||||
adrv9009_gpio_06_a, // 38
|
||||
adrv9009_gpio_05_a, // 37
|
||||
adrv9009_gpio_04_a, // 36
|
||||
adrv9009_gpio_03_a, // 35
|
||||
adrv9009_gpio_02_a, // 34
|
||||
adrv9009_gpio_01_a, // 33
|
||||
adrv9009_gpio_00_a})); // 32
|
||||
|
||||
ad_iobuf #(.DATA_WIDTH(28)) i_carrier_iobuf (
|
||||
.dio_t ({gpio_t[27:0]}),
|
||||
.dio_i ({gpio_o[27:0]}),
|
||||
.dio_o ({gpio_i[27:0]}),
|
||||
.dio_p ({
|
||||
hmc7044_car_gpio_3, // 27
|
||||
hmc7044_car_gpio_2, // 26
|
||||
hmc7044_car_gpio_1, // 25
|
||||
hmc7044_car_gpio_0, // 24
|
||||
hmc7044_car_reset, // 23
|
||||
resetb_ad9545, // 22
|
||||
fan_tach, // 21
|
||||
fan_pwrm, // 20
|
||||
pmod0_d7, // 19
|
||||
pmod0_d6, // 18
|
||||
pmod0_d5, // 17
|
||||
pmod0_d4, // 16
|
||||
pmod0_d3, // 15
|
||||
pmod0_d2, // 14
|
||||
pmod0_d1, // 13
|
||||
pmod0_d0, // 12
|
||||
led_gpio_3, // 11
|
||||
led_gpio_2, // 10
|
||||
led_gpio_1, // 9
|
||||
led_gpio_0, // 8
|
||||
dip_gpio_3, // 7
|
||||
dip_gpio_2, // 6
|
||||
dip_gpio_1, // 5
|
||||
dip_gpio_0, // 4
|
||||
pb_gpio_3, // 3
|
||||
pb_gpio_2, // 2
|
||||
pb_gpio_1, // 1
|
||||
pb_gpio_0})); // 0
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk_1 (
|
||||
.CEB (1'd0),
|
||||
.I (ref_clk_a_p),
|
||||
.IB (ref_clk_a_n),
|
||||
.O (ref_clk_a),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS_GTE4 i_ibufds_ref_clk_2 (
|
||||
.CEB (1'd0),
|
||||
.I (ref_clk_b_p),
|
||||
.IB (ref_clk_b_n),
|
||||
.O (ref_clk_b),
|
||||
.ODIV2 ());
|
||||
|
||||
IBUFDS i_ibufds_sysref_1 (
|
||||
.I (sysref_a_p),
|
||||
.IB (sysref_a_n),
|
||||
.O (sysref_a));
|
||||
|
||||
IBUFDS i_ibufds_sysref_2 (
|
||||
.I (sysref_b_p),
|
||||
.IB (sysref_b_n),
|
||||
.O (sysref_b));
|
||||
|
||||
IBUFGDS i_rx_clk_ibufg_1 (
|
||||
.I (core_clk_a_p),
|
||||
.IB (core_clk_a_n),
|
||||
.O (core_clk_a));
|
||||
|
||||
IBUFGDS i_rx_clk_ibufg_2 (
|
||||
.I (core_clk_b_p),
|
||||
.IB (core_clk_b_n),
|
||||
.O (core_clk_b));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync_1 (
|
||||
.I (tx_sync_a_p),
|
||||
.IB (tx_sync_a_n),
|
||||
.O (tx_sync_a));
|
||||
|
||||
IBUFDS i_ibufds_tx_sync_2 (
|
||||
.I (tx_sync_b_p),
|
||||
.IB (tx_sync_b_n),
|
||||
.O (tx_sync_b));
|
||||
|
||||
OBUFDS i_obufds_rx_sync_1 (
|
||||
.I (rx_sync_rx),
|
||||
.O (rx_sync_a_p),
|
||||
.OB (rx_sync_a_n));
|
||||
|
||||
OBUFDS i_obufds_rx_os_sync_1 (
|
||||
.I (rx_sync_obs),
|
||||
.O (rx_os_sync_a_p),
|
||||
.OB (rx_os_sync_a_n));
|
||||
|
||||
OBUFDS i_obufds_rx_sync_2 (
|
||||
.I (rx_sync_rx),
|
||||
.O (rx_sync_b_p),
|
||||
.OB (rx_sync_b_n));
|
||||
|
||||
OBUFDS i_obufds_rx_os_sync_2 (
|
||||
.I (rx_sync_obs),
|
||||
.O (rx_os_sync_b_p),
|
||||
.OB (rx_os_sync_b_n));
|
||||
|
||||
system_wrapper i_system_wrapper (
|
||||
.gpio_i (gpio_i),
|
||||
.gpio_o (gpio_o),
|
||||
.gpio_t (gpio_t),
|
||||
|
||||
.ddr4_rtl_1_act_n(ddr4_rtl_1_act_n),
|
||||
.ddr4_rtl_1_adr(ddr4_rtl_1_adr),
|
||||
.ddr4_rtl_1_ba(ddr4_rtl_1_ba),
|
||||
.ddr4_rtl_1_bg(ddr4_rtl_1_bg),
|
||||
.ddr4_rtl_1_ck_c(ddr4_rtl_1_ck_c),
|
||||
.ddr4_rtl_1_ck_t(ddr4_rtl_1_ck_t),
|
||||
.ddr4_rtl_1_cke(ddr4_rtl_1_cke),
|
||||
.ddr4_rtl_1_cs_n(ddr4_rtl_1_cs_n),
|
||||
.ddr4_rtl_1_dm_n(ddr4_rtl_1_dm_n),
|
||||
.ddr4_rtl_1_dq(ddr4_rtl_1_dq),
|
||||
.ddr4_rtl_1_dqs_c(ddr4_rtl_1_dqs_c),
|
||||
.ddr4_rtl_1_dqs_t(ddr4_rtl_1_dqs_t),
|
||||
.ddr4_rtl_1_odt(ddr4_rtl_1_odt),
|
||||
.ddr4_rtl_1_reset_n(ddr4_rtl_1_reset_n),
|
||||
.sys_reset(1'b0),
|
||||
.ddr4_ref_1_clk_n(ddr4_ref_1_clk_n),
|
||||
.ddr4_ref_1_clk_p(ddr4_ref_1_clk_p),
|
||||
.core_clk_a(core_clk_a),
|
||||
.core_clk_b(core_clk_b),
|
||||
.ref_clk_a(ref_clk_a),
|
||||
.ref_clk_b(ref_clk_b),
|
||||
.rx_data_0_n (rx_data_a_n[0]),
|
||||
.rx_data_0_p (rx_data_a_p[0]),
|
||||
.rx_data_1_n (rx_data_a_n[1]),
|
||||
.rx_data_1_p (rx_data_a_p[1]),
|
||||
.rx_data_2_n (rx_data_a_n[2]),
|
||||
.rx_data_2_p (rx_data_a_p[2]),
|
||||
.rx_data_3_n (rx_data_a_n[3]),
|
||||
.rx_data_3_p (rx_data_a_p[3]),
|
||||
.rx_data_4_n (rx_data_b_n[0]),
|
||||
.rx_data_4_p (rx_data_b_p[0]),
|
||||
.rx_data_5_n (rx_data_b_n[1]),
|
||||
.rx_data_5_p (rx_data_b_p[1]),
|
||||
.rx_data_6_n (rx_data_b_n[2]),
|
||||
.rx_data_6_p (rx_data_b_p[2]),
|
||||
.rx_data_7_n (rx_data_b_n[3]),
|
||||
.rx_data_7_p (rx_data_b_p[3]),
|
||||
.rx_sync_0 (rx_sync_rx),
|
||||
.rx_sync_4 (rx_sync_obs),
|
||||
.rx_sysref_0 (sysref_b),
|
||||
.rx_sysref_4 (sysref_a),
|
||||
.tx_data_0_n (tx_data_a_n[0]),
|
||||
.tx_data_0_p (tx_data_a_p[0]),
|
||||
.tx_data_1_n (tx_data_a_n[1]),
|
||||
.tx_data_1_p (tx_data_a_p[1]),
|
||||
.tx_data_2_n (tx_data_a_n[2]),
|
||||
.tx_data_2_p (tx_data_a_p[2]),
|
||||
.tx_data_3_n (tx_data_a_n[3]),
|
||||
.tx_data_3_p (tx_data_a_p[3]),
|
||||
.tx_data_4_n (tx_data_b_n[0]),
|
||||
.tx_data_4_p (tx_data_b_p[0]),
|
||||
.tx_data_5_n (tx_data_b_n[1]),
|
||||
.tx_data_5_p (tx_data_b_p[1]),
|
||||
.tx_data_6_n (tx_data_b_n[2]),
|
||||
.tx_data_6_p (tx_data_b_p[2]),
|
||||
.tx_data_7_n (tx_data_b_n[3]),
|
||||
.tx_data_7_p (tx_data_b_p[3]),
|
||||
.tx_sync_0 (tx_sync),
|
||||
.tx_sysref_0 (sysref_a),
|
||||
.dac_fifo_bypass(gpio_o[90]),
|
||||
.spi0_csn(spi_csn),
|
||||
.spi0_miso(spi0_miso),
|
||||
.spi0_mosi(spi_mosi),
|
||||
.spi0_sclk(spi_clk)
|
||||
);
|
||||
|
||||
endmodule
|
||||
|
||||
// ***************************************************************************
|
||||
// ***************************************************************************
|
||||
Loading…
Reference in New Issue