From 95701fbd0e2b8864f6e9f1816e1c603424a85e39 Mon Sep 17 00:00:00 2001 From: Istvan Csomortani Date: Thu, 10 Jul 2014 10:41:48 +0300 Subject: [PATCH] fmcomms2_pr : PR initial check in --- projects/fmcomms2_pr/common/prcfg_setup.tcl | 87 +++++ .../fmcomms2_pr/common/prcfg_system_top.v | 134 +++++++ projects/fmcomms2_pr/mitx045/prcfg_constr.xdc | 81 ++++ projects/fmcomms2_pr/mitx045/system_bd.tcl | 5 + .../fmcomms2_pr/mitx045/system_project.tcl | 96 +++++ projects/fmcomms2_pr/mitx045/system_top.v | 361 ++++++++++++++++++ projects/fmcomms2_pr/zc706/prcfg_constr.xdc | 81 ++++ projects/fmcomms2_pr/zc706/system_bd.tcl | 5 + projects/fmcomms2_pr/zc706/system_project.tcl | 96 +++++ projects/fmcomms2_pr/zc706/system_top.v | 346 +++++++++++++++++ 10 files changed, 1292 insertions(+) create mode 100644 projects/fmcomms2_pr/common/prcfg_setup.tcl create mode 100644 projects/fmcomms2_pr/common/prcfg_system_top.v create mode 100644 projects/fmcomms2_pr/mitx045/prcfg_constr.xdc create mode 100644 projects/fmcomms2_pr/mitx045/system_bd.tcl create mode 100644 projects/fmcomms2_pr/mitx045/system_project.tcl create mode 100644 projects/fmcomms2_pr/mitx045/system_top.v create mode 100644 projects/fmcomms2_pr/zc706/prcfg_constr.xdc create mode 100644 projects/fmcomms2_pr/zc706/system_bd.tcl create mode 100644 projects/fmcomms2_pr/zc706/system_project.tcl create mode 100644 projects/fmcomms2_pr/zc706/system_top.v diff --git a/projects/fmcomms2_pr/common/prcfg_setup.tcl b/projects/fmcomms2_pr/common/prcfg_setup.tcl new file mode 100644 index 000000000..827e78bc4 --- /dev/null +++ b/projects/fmcomms2_pr/common/prcfg_setup.tcl @@ -0,0 +1,87 @@ +set data_width 63 + +# +# Port definitions +# + +set clk [create_bd_port -dir O clk] + +# define ports for tx +set dma_dac_dunf [create_bd_port -dir O dma_dac_dunf] +set core_dac_dunf [create_bd_port -dir I core_dac_dunf] +set dma_dac_ddata [create_bd_port -dir O -from $data_width -to 0 dma_dac_ddata] +set core_dac_ddata [create_bd_port -dir I -from $data_width -to 0 core_dac_ddata] +set dma_dac_drd [create_bd_port -dir I dma_dac_drd] +set core_dac_drd [create_bd_port -dir O core_dac_drd] + +# define ports for rx +set dma_adc_ovf [create_bd_port -dir O dma_adc_ovf] +set core_adc_ovf [create_bd_port -dir I core_adc_ovf] +set dma_adc_ddata [create_bd_port -dir I -from $data_width -to 0 dma_adc_ddata] +set core_adc_ddata [create_bd_port -dir O -from $data_width -to 0 core_adc_ddata] +set dma_adc_dwr [create_bd_port -dir I dma_adc_dwr] +set core_adc_dwr [create_bd_port -dir O core_adc_dwr] +set dma_adc_dsync [create_bd_port -dir I dma_adc_dsync] +set core_adc_dsync [create_bd_port -dir O core_adc_dsync] + +# define gpio input/outpu ports +set up_dac_gpio_in [create_bd_port -dir I -from 31 -to 0 up_dac_gpio_in] +set up_adc_gpio_in [create_bd_port -dir I -from 31 -to 0 up_adc_gpio_in] +set up_dac_gpio_out [create_bd_port -dir O -from 31 -to 0 up_dac_gpio_out] +set up_adc_gpio_out [create_bd_port -dir O -from 31 -to 0 up_adc_gpio_out] + +# define additional ila probes +set_property -dict [list CONFIG.C_NUM_OF_PROBES {9}] $ila_adc +set_property -dict [list CONFIG.C_PROBE5_WIDTH {64}] $ila_adc +set_property -dict [list CONFIG.C_PROBE6_WIDTH {64}] $ila_adc +set_property -dict [list CONFIG.C_PROBE7_WIDTH {64}] $ila_adc +set_property -dict [list CONFIG.C_PROBE8_WIDTH {64}] $ila_adc + +# +# Net definitions +# + +# connect clock signal +connect_bd_net [get_bd_pins axi_ad9361/clk] [get_bd_ports clk] + +# connections for tx path + +# clear the existing datapath +delete_bd_objs [get_bd_nets axi_ad9361_dac_dunf] [get_bd_nets fifo_data] [get_bd_nets axi_ad9361_dac_drd] + +# connect pins to port +connect_bd_net -net rp_dma_unf_tx [get_bd_pins axi_ad9361_dac_dma/fifo_rd_underflow] [get_bd_ports dma_dac_dunf] +connect_bd_net -net rp_dma_data_tx [get_bd_pins axi_ad9361_dac_dma/fifo_rd_dout] [get_bd_ports dma_dac_ddata] +connect_bd_net -net rp_dma_rdy_tx [get_bd_pins axi_ad9361_dac_dma/fifo_rd_en] [get_bd_ports dma_dac_drd] + +connect_bd_net -net rp_core_unf_tx [get_bd_pins axi_ad9361/dac_dunf] [get_bd_ports core_dac_dunf] +connect_bd_net -net rp_core_data_tx [get_bd_pins util_dac_unpack/dma_data] [get_bd_ports core_dac_ddata] +connect_bd_net -net rp_core_rdy_tx [get_bd_pins util_dac_unpack/dma_rd] [get_bd_ports core_dac_drd] + +# connections for rx path + +# clear the existing datapath +delete_bd_objs [get_bd_nets axi_ad9361_adc_dovf] [get_bd_nets util_adc_pack_ddata] [get_bd_nets util_adc_pack_dvalid] [get_bd_nets util_adc_pack_dsync] + +# connect pins to port +connect_bd_net -net rp_dma_ovf_rx [get_bd_pins axi_ad9361_adc_dma/fifo_wr_overflow] [get_bd_ports dma_adc_ovf] +connect_bd_net -net rp_dma_data_rx [get_bd_pins axi_ad9361_adc_dma/fifo_wr_din] [get_bd_ports dma_adc_ddata] +connect_bd_net -net rp_dma_rdy_rx [get_bd_pins axi_ad9361_adc_dma/fifo_wr_en] [get_bd_ports dma_adc_dwr] +connect_bd_net -net rp_dma_sync_rx [get_bd_pins axi_ad9361_adc_dma/fifo_wr_sync] [get_bd_ports dma_adc_dsync] + +connect_bd_net -net rp_core_ovf_rx [get_bd_pins axi_ad9361/adc_dovf] [get_bd_ports core_adc_ovf] +connect_bd_net -net rp_core_data_rx [get_bd_pins util_adc_pack/ddata] [get_bd_ports core_adc_ddata] +connect_bd_net -net rp_core_rdy_rx [get_bd_pins util_adc_pack/dvalid] [get_bd_ports core_adc_dwr] +connect_bd_net -net rp_core_sync_rx [get_bd_pins util_adc_pack/dsync] [get_bd_ports core_adc_dsync] + +connect_bd_net -net dac_gpio_in [get_bd_pins axi_ad9361/up_dac_gpio_in] [get_bd_ports up_dac_gpio_in] +connect_bd_net -net adc_gpio_in [get_bd_pins axi_ad9361/up_adc_gpio_in] [get_bd_ports up_adc_gpio_in] +connect_bd_net -net dac_gpio_out [get_bd_pins axi_ad9361/up_dac_gpio_out] [get_bd_ports up_dac_gpio_out] +connect_bd_net -net adc_gpio_out [get_bd_pins axi_ad9361/up_adc_gpio_out] [get_bd_ports up_adc_gpio_out] + +# connect ila probes +connect_bd_net -net rp_core_data_tx [get_bd_pins ila_adc/probe5] +connect_bd_net -net rp_core_data_rx [get_bd_pins ila_adc/probe6] +connect_bd_net -net rp_dma_data_tx [get_bd_pins ila_adc/probe7] +connect_bd_net -net rp_dma_data_rx [get_bd_pins ila_adc/probe8] + diff --git a/projects/fmcomms2_pr/common/prcfg_system_top.v b/projects/fmcomms2_pr/common/prcfg_system_top.v new file mode 100644 index 000000000..c8d683ae0 --- /dev/null +++ b/projects/fmcomms2_pr/common/prcfg_system_top.v @@ -0,0 +1,134 @@ + +// *************************************************************************** +// *************************************************************************** +// Copyright 2013(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/1ns + +module prcfg_system_top ( + clk, + + // gpio + adc_gpio_input, + adc_gpio_output, + dac_gpio_input, + dac_gpio_output, + + // TX side + dma_dac_drd, + dma_dac_dunf, + dma_dac_ddata, + + core_dac_drd, + core_dac_dunf, + core_dac_ddata, + + // RX side + core_adc_dwr, + core_adc_dsync, + core_adc_ddata, + core_adc_ovf, + + dma_adc_dwr, + dma_adc_dsync, + dma_adc_ddata, + dma_adc_ovf +); + + input clk; + + input [31:0] adc_gpio_input; + output [31:0] adc_gpio_output; + input [31:0] dac_gpio_input; + output [31:0] dac_gpio_output; + + output dma_dac_drd; + input dma_dac_dunf; + input [63:0] dma_dac_ddata; + + input core_dac_drd; + output core_dac_dunf; + output [63:0] core_dac_ddata; + + input core_adc_dwr; + input core_adc_dsync; + input [63:0] core_adc_ddata; + output core_adc_ovf; + + output dma_adc_dwr; + output dma_adc_dsync; + output [63:0] dma_adc_ddata; + input dma_adc_ovf; + + + localparam NUM_CHANNEL = 2; + localparam ENABLE = 1; + localparam DISABLE = 0; + + // setup values for PR fmcomms2 + // number of channels : 2 + // ADC : enabled + // DAC : enabled + + prcfg_top #( + .NUM_CHANNEL(NUM_CHANNEL), + .ADC_EN(ENABLE), + .DAC_EN(ENABLE) + )i_prcfg_top ( + .clk(clk), + .adc_gpio_input(adc_gpio_input), + .adc_gpio_output(adc_gpio_output), + .dac_gpio_input(dac_gpio_input), + .dac_gpio_output(dac_gpio_output), + .dma_dac_drd(dma_dac_drd), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .core_dac_drd(core_dac_drd), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf) +); + +endmodule diff --git a/projects/fmcomms2_pr/mitx045/prcfg_constr.xdc b/projects/fmcomms2_pr/mitx045/prcfg_constr.xdc new file mode 100644 index 000000000..835081e55 --- /dev/null +++ b/projects/fmcomms2_pr/mitx045/prcfg_constr.xdc @@ -0,0 +1,81 @@ + +#------------------------------------------------- +# pblock_switch +# for pr instance switch +#------------------------------------------------- +create_pblock pblock_adi +add_cells_to_pblock [get_pblocks pblock_adi] [get_cells -quiet [list i_prcfg_system_top]] +resize_pblock [get_pblocks pblock_adi] -add {SLICE_X90Y0:SLICE_X161Y149} +resize_pblock [get_pblocks pblock_adi] -add {RAMB18_X4Y0:RAMB18_X7Y59} +resize_pblock [get_pblocks pblock_adi] -add {RAMB36_X4Y0:RAMB36_X7Y29} +resize_pblock [get_pblocks pblock_adi] -add {DSP48_X4Y0:DSP48_X6Y59} +set_property RESET_AFTER_RECONFIG 1 [get_pblocks pblock_adi] + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AB16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AH18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N + +set_property -dict {PACKAGE_PIN AK13 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AK12 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN T29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN U29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN R28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN T28 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN W29 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN W25 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN W26 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN V27 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN W28 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] +create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {ad9361_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + diff --git a/projects/fmcomms2_pr/mitx045/system_bd.tcl b/projects/fmcomms2_pr/mitx045/system_bd.tcl new file mode 100644 index 000000000..45e306ad9 --- /dev/null +++ b/projects/fmcomms2_pr/mitx045/system_bd.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/mitx045/mitx045_system_bd.tcl +source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl +source $ad_phdl_dir/projects/fmcomms2_rp/common/prcfg_setup.tcl + diff --git a/projects/fmcomms2_pr/mitx045/system_project.tcl b/projects/fmcomms2_pr/mitx045/system_project.tcl new file mode 100644 index 000000000..30cc47263 --- /dev/null +++ b/projects/fmcomms2_pr/mitx045/system_project.tcl @@ -0,0 +1,96 @@ +# Script for non-project mode + +# activate/deactivate different flow stages +set runInit 1 +set runSynth 1 +set runImpl 1 +set runPrv 1 +set runBit 1 + +# supported carrier ZC706/MITX045 +set part "xc7z045ffg900-2" + +# Load scripts for env. variables and RP design flow +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_prcfg_project.tcl + +############################################################################### +#### INIT WORKSPACE #### +############################################################################### +if { $runInit == 1 } { + prcfg_init_workspace [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### SYNTHESIS #### +############################################################################### +if { $runSynth == 1 } { + + ########### Static part + + prcfg_synth_static [list "./system_top.v" \ + "${ad_hdl_dir}/library/common/ad_iobuf.v"] \ + "${ad_hdl_dir}/projects/common/mitx045/mitx045_system_constr.xdc" + + ########### Reconfigurable part + # Default + set prcfg_name "default" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v"] + # Bist + set prcfg_name "bist" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v"] + + # Qpsk + set prcfg_name "qpsk" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Tx_Filter.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Rx_Filter.v"] +} + +############################################################################### +#### IMPLEMENTATION #### +############################################################################### +if { $runImpl == 1 } { + + prcfg_impl "prcfg_constr.xdc" [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### PR Verify #### +############################################################################### +if { $runPrv == 1 } { + + prcfg_verify [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### BITSTREAM GENERATION #### +############################################################################### +if { $runBit == 1} { + + prcfg_gen_bit [list "default" \ + "bist" \ + "qpsk"] +} + diff --git a/projects/fmcomms2_pr/mitx045/system_top.v b/projects/fmcomms2_pr/mitx045/system_top.v new file mode 100644 index 000000000..7f0fe407b --- /dev/null +++ b/projects/fmcomms2_pr/mitx045/system_top.v @@ -0,0 +1,361 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + i2s_mclk, + i2s_bclk, + i2s_lrclk, + i2s_sdata_out, + i2s_sdata_in, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [11:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [15:0] hdmi_data; + + output spdif; + + output i2s_mclk; + output i2s_bclk; + output i2s_lrclk; + output i2s_sdata_out; + input i2s_sdata_in; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + inout gpio_txnrx; + inout gpio_enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [48:0] gpio_i; + wire [48:0] gpio_o; + wire [48:0] gpio_t; + wire [19:0] gpio_wire; + + wire clk; + wire dma_dac_dunf; + wire core_dac_dunf; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; + wire dma_dac_drd; + wire core_dac_drd; + + wire dma_adc_ovf; + wire core_adc_ovf; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; + wire dma_adc_dwr; + wire core_adc_dwr; + wire dma_adc_dsync; + wire core_adc_dsync; + + // PR GPIOs + wire [31:0] adc_gpio_input; + wire [31:0] adc_gpio_output; + wire [31:0] dac_gpio_input; + wire [31:0] dac_gpio_output; + + ad_iobuf #(.DATA_WIDTH(49)) i_iobuf ( + .dt (gpio_t[48:0]), + .di (gpio_o[48:0]), + .do (gpio_i[48:0]), + .dio ({ gpio_txnrx, // 48 + gpio_enable, // 47 + gpio_resetb, // 46 + gpio_sync, // 45 + gpio_en_agc, // 44 + gpio_ctl, // 40 + gpio_status, // 32 + gpio_wire, // 15 + gpio_bd})); // 0 + + prcfg_system_top i_prcfg_system_top ( + .clk(clk), + .adc_gpio_input(adc_gpio_input), + .adc_gpio_output(adc_gpio_output), + .dac_gpio_input(dac_gpio_input), + .dac_gpio_output(dac_gpio_output), + .dma_dac_drd(dma_dac_drd), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .core_dac_drd(core_dac_drd), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf)); + + system_wrapper i_system_wrapper ( + + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + .i2s_bclk (i2s_bclk), + .i2s_lrclk (i2s_lrclk), + .i2s_mclk (i2s_mclk), + .i2s_sdata_in (i2s_sdata_in), + .i2s_sdata_out (i2s_sdata_out), + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + + .spdif (spdif), + + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_miso_i (spi_miso), + .spi_mosi_i (1'b0), + .spi_mosi_o (spi_mosi), + .spi_sclk_i (1'b0), + .spi_sclk_o (spi_clk), + + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + // pr related ports + .clk(clk), + + .dma_dac_drd(dma_dac_drd), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .core_dac_drd(core_dac_drd), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf), + + .up_dac_gpio_in(dac_gpio_output), + .up_adc_gpio_in(adc_gpio_output), + .up_dac_gpio_out(dac_gpio_input), + .up_adc_gpio_out(adc_gpio_input)); + +endmodule + +// black box definition for PR module +(* black_box *) module prcfg_system_top ( + input clk, + input [31:0] adc_gpio_input, + output [31:0] adc_gpio_output, + input [31:0] dac_gpio_input, + output [31:0] dac_gpio_output, + output dma_dac_drd, + input dma_dac_dunf, + input [63:0] dma_dac_ddata, + input core_dac_drd, + output core_dac_dunf, + output [63:0] core_dac_ddata, + input core_adc_dwr, + input core_adc_dsync, + input [63:0] core_adc_ddata, + output core_adc_ovf, + output dma_adc_dwr, + output dma_adc_dsync, + output [63:0] dma_adc_ddata, + input dma_adc_ovf); + +endmodule + +// *************************************************************************** +// *************************************************************************** diff --git a/projects/fmcomms2_pr/zc706/prcfg_constr.xdc b/projects/fmcomms2_pr/zc706/prcfg_constr.xdc new file mode 100644 index 000000000..98070e363 --- /dev/null +++ b/projects/fmcomms2_pr/zc706/prcfg_constr.xdc @@ -0,0 +1,81 @@ + +#------------------------------------------------- +# pblock_switch +# for pr instance switch +#------------------------------------------------- +create_pblock pblock_adi +add_cells_to_pblock [get_pblocks pblock_adi] [get_cells -quiet [list i_prcfg_system_top]] +resize_pblock [get_pblocks pblock_adi] -add {SLICE_X90Y0:SLICE_X161Y149} +resize_pblock [get_pblocks pblock_adi] -add {RAMB18_X4Y0:RAMB18_X7Y59} +resize_pblock [get_pblocks pblock_adi] -add {RAMB36_X4Y0:RAMB36_X7Y29} +resize_pblock [get_pblocks pblock_adi] -add {DSP48_X4Y0:DSP48_X6Y59} +set_property RESET_AFTER_RECONFIG 1 [get_pblocks pblock_adi] + +# constraints +# ad9361 + +set_property -dict {PACKAGE_PIN AE13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P +set_property -dict {PACKAGE_PIN AF13 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N +set_property -dict {PACKAGE_PIN AF15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P +set_property -dict {PACKAGE_PIN AG15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N +set_property -dict {PACKAGE_PIN AE12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P +set_property -dict {PACKAGE_PIN AF12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N +set_property -dict {PACKAGE_PIN AG12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P +set_property -dict {PACKAGE_PIN AH12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N +set_property -dict {PACKAGE_PIN AJ15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P +set_property -dict {PACKAGE_PIN AK15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N +set_property -dict {PACKAGE_PIN AE16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P +set_property -dict {PACKAGE_PIN AE15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N +set_property -dict {PACKAGE_PIN AB12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P +set_property -dict {PACKAGE_PIN AC12 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N +set_property -dict {PACKAGE_PIN AA15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P +set_property -dict {PACKAGE_PIN AA14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N +set_property -dict {PACKAGE_PIN AD14 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P +set_property -dict {PACKAGE_PIN AD13 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N +set_property -dict {PACKAGE_PIN AH14 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P +set_property -dict {PACKAGE_PIN AH13 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N +set_property -dict {PACKAGE_PIN AJ16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P +set_property -dict {PACKAGE_PIN AK16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N +set_property -dict {PACKAGE_PIN AD16 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P +set_property -dict {PACKAGE_PIN AD15 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N +set_property -dict {PACKAGE_PIN AH17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P +set_property -dict {PACKAGE_PIN AH16 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N +set_property -dict {PACKAGE_PIN AC14 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P +set_property -dict {PACKAGE_PIN AC13 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N +set_property -dict {PACKAGE_PIN AF18 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P +set_property -dict {PACKAGE_PIN AF17 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N +set_property -dict {PACKAGE_PIN AB15 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P +set_property -dict {PACKAGE_PIN AB14 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N + +set_property -dict {PACKAGE_PIN AG26 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P +set_property -dict {PACKAGE_PIN AG27 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N +set_property -dict {PACKAGE_PIN AH28 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P +set_property -dict {PACKAGE_PIN AH29 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N +set_property -dict {PACKAGE_PIN AK27 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P +set_property -dict {PACKAGE_PIN AK28 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N +set_property -dict {PACKAGE_PIN AJ26 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P +set_property -dict {PACKAGE_PIN AK26 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N +set_property -dict {PACKAGE_PIN AF30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P +set_property -dict {PACKAGE_PIN AG30 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N +set_property -dict {PACKAGE_PIN AF29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P +set_property -dict {PACKAGE_PIN AG29 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N +set_property -dict {PACKAGE_PIN AH26 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P +set_property -dict {PACKAGE_PIN AH27 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N +set_property -dict {PACKAGE_PIN AD25 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P +set_property -dict {PACKAGE_PIN AE18 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P +set_property -dict {PACKAGE_PIN AE17 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N + +set_property -dict {PACKAGE_PIN AJ30 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P +set_property -dict {PACKAGE_PIN AK30 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N +set_property -dict {PACKAGE_PIN AJ28 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P +set_property -dict {PACKAGE_PIN AJ29 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N + +# clocks + +create_clock -name rx_clk -period 4.00 [get_ports rx_clk_in_p] +create_clock -name ad9361_clk -period 4.00 [get_pins i_system_wrapper/system_i/axi_ad9361/clk] +create_clock -name fmc_dma_clk -period 10.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] + +set_clock_groups -asynchronous -group {ad9361_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} + diff --git a/projects/fmcomms2_pr/zc706/system_bd.tcl b/projects/fmcomms2_pr/zc706/system_bd.tcl new file mode 100644 index 000000000..edee8c684 --- /dev/null +++ b/projects/fmcomms2_pr/zc706/system_bd.tcl @@ -0,0 +1,5 @@ + +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source $ad_hdl_dir/projects/fmcomms2/common/fmcomms2_bd.tcl +source $ad_phdl_dir/projects/fmcomms2_rp/common/prcfg_setup.tcl + diff --git a/projects/fmcomms2_pr/zc706/system_project.tcl b/projects/fmcomms2_pr/zc706/system_project.tcl new file mode 100644 index 000000000..ac35a4284 --- /dev/null +++ b/projects/fmcomms2_pr/zc706/system_project.tcl @@ -0,0 +1,96 @@ +# Script for non-project mode + +# activate/deactivate different flow stages +set runInit 1 +set runSynth 1 +set runImpl 1 +set runPrv 1 +set runBit 1 + +# supported carrier ZC706 +set part "xc7z045ffg900-2" + +# Load scripts for env. variables and RP design flow +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_prcfg_project.tcl + +############################################################################### +#### INIT WORKSPACE #### +############################################################################### +if { $runInit == 1 } { + prcfg_init_workspace [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### SYNTHESIS #### +############################################################################### +if { $runSynth == 1 } { + + ########### Static part + + prcfg_synth_static [list "./system_top.v" \ + "${ad_hdl_dir}/library/common/ad_iobuf.v"] \ + "${ad_hdl_dir}/projects/common/zc706/zc706_system_constr.xdc" + + ########### Reconfigurable part + # Default + set prcfg_name "default" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v"] + # Bist + set prcfg_name "bist" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v"] + + # Qpsk + set prcfg_name "qpsk" + prcfg_synth_reconf $prcfg_name [list "../common/prcfg_system_top.v" \ + "${ad_hdl_dir}/library/prcfg/common/prcfg_top.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_dac.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/prcfg_adc.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_mod.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/qpsk_demod.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Modulator.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/QPSK_Demodulator_Baseband.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Interpolation.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/FIR_Decimation.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Tx_Filter.v" \ + "${ad_hdl_dir}/library/prcfg/${prcfg_name}/Raised_Cosine_Rx_Filter.v"] +} + +############################################################################### +#### IMPLEMENTATION #### +############################################################################### +if { $runImpl == 1 } { + + prcfg_impl "prcfg_constr.xdc" [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### PR Verify #### +############################################################################### +if { $runPrv == 1 } { + + prcfg_verify [list "default" \ + "bist" \ + "qpsk"] +} + +############################################################################### +#### BITSTREAM GENERATION #### +############################################################################### +if { $runBit == 1} { + + prcfg_gen_bit [list "default" \ + "bist" \ + "qpsk"] +} + diff --git a/projects/fmcomms2_pr/zc706/system_top.v b/projects/fmcomms2_pr/zc706/system_top.v new file mode 100644 index 000000000..82321a913 --- /dev/null +++ b/projects/fmcomms2_pr/zc706/system_top.v @@ -0,0 +1,346 @@ +// *************************************************************************** +// *************************************************************************** +// Copyright 2011(c) Analog Devices, Inc. +// +// All rights reserved. +// +// Redistribution and use in source and binary forms, with or without modification, +// are permitted provided that the following conditions are met: +// - Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// - Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in +// the documentation and/or other materials provided with the +// distribution. +// - Neither the name of Analog Devices, Inc. nor the names of its +// contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// - The use of this software may or may not infringe the patent rights +// of one or more patent holders. This license does not release you +// from the requirement that you obtain separate licenses from these +// patent holders to use this software. +// - Use of the software either in source or binary form, must be run +// on or directly connected to an Analog Devices Inc. component. +// +// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, +// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A +// PARTICULAR PURPOSE ARE DISCLAIMED. +// +// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, +// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY +// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR +// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, +// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF +// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** +// *************************************************************************** + +`timescale 1ns/100ps + +module system_top ( + + DDR_addr, + DDR_ba, + DDR_cas_n, + DDR_ck_n, + DDR_ck_p, + DDR_cke, + DDR_cs_n, + DDR_dm, + DDR_dq, + DDR_dqs_n, + DDR_dqs_p, + DDR_odt, + DDR_ras_n, + DDR_reset_n, + DDR_we_n, + + FIXED_IO_ddr_vrn, + FIXED_IO_ddr_vrp, + FIXED_IO_mio, + FIXED_IO_ps_clk, + FIXED_IO_ps_porb, + FIXED_IO_ps_srstb, + + gpio_bd, + + hdmi_out_clk, + hdmi_vsync, + hdmi_hsync, + hdmi_data_e, + hdmi_data, + + spdif, + + iic_scl, + iic_sda, + + rx_clk_in_p, + rx_clk_in_n, + rx_frame_in_p, + rx_frame_in_n, + rx_data_in_p, + rx_data_in_n, + tx_clk_out_p, + tx_clk_out_n, + tx_frame_out_p, + tx_frame_out_n, + tx_data_out_p, + tx_data_out_n, + + gpio_txnrx, + gpio_enable, + gpio_resetb, + gpio_sync, + gpio_en_agc, + gpio_ctl, + gpio_status, + + spi_csn, + spi_clk, + spi_mosi, + spi_miso); + + inout [14:0] DDR_addr; + inout [ 2:0] DDR_ba; + inout DDR_cas_n; + inout DDR_ck_n; + inout DDR_ck_p; + inout DDR_cke; + inout DDR_cs_n; + inout [ 3:0] DDR_dm; + inout [31:0] DDR_dq; + inout [ 3:0] DDR_dqs_n; + inout [ 3:0] DDR_dqs_p; + inout DDR_odt; + inout DDR_ras_n; + inout DDR_reset_n; + inout DDR_we_n; + + inout FIXED_IO_ddr_vrn; + inout FIXED_IO_ddr_vrp; + inout [53:0] FIXED_IO_mio; + inout FIXED_IO_ps_clk; + inout FIXED_IO_ps_porb; + inout FIXED_IO_ps_srstb; + + inout [14:0] gpio_bd; + + output hdmi_out_clk; + output hdmi_vsync; + output hdmi_hsync; + output hdmi_data_e; + output [23:0] hdmi_data; + + output spdif; + + inout iic_scl; + inout iic_sda; + + input rx_clk_in_p; + input rx_clk_in_n; + input rx_frame_in_p; + input rx_frame_in_n; + input [ 5:0] rx_data_in_p; + input [ 5:0] rx_data_in_n; + output tx_clk_out_p; + output tx_clk_out_n; + output tx_frame_out_p; + output tx_frame_out_n; + output [ 5:0] tx_data_out_p; + output [ 5:0] tx_data_out_n; + + inout gpio_txnrx; + inout gpio_enable; + inout gpio_resetb; + inout gpio_sync; + inout gpio_en_agc; + inout [ 3:0] gpio_ctl; + inout [ 7:0] gpio_status; + + output spi_csn; + output spi_clk; + output spi_mosi; + input spi_miso; + + // internal signals + + wire [48:0] gpio_i; + wire [48:0] gpio_o; + wire [48:0] gpio_t; + wire [16:0] gpio_wire; + + wire clk; + wire dma_dac_dunf; + wire core_dac_dunf; + wire [63:0] dma_dac_ddata; + wire [63:0] core_dac_ddata; + wire dma_dac_drd; + wire core_dac_drd; + + wire dma_adc_ovf; + wire core_adc_ovf; + wire [63:0] dma_adc_ddata; + wire [63:0] core_adc_ddata; + wire dma_adc_dwr; + wire core_adc_dwr; + wire dma_adc_dsync; + wire core_adc_dsync; + + // PR GPIOs + wire [31:0] adc_gpio_input; + wire [31:0] adc_gpio_output; + wire [31:0] dac_gpio_input; + wire [31:0] dac_gpio_output; + + // instantiations + ad_iobuf #(.DATA_WIDTH(49)) i_iobuf_gpio_ps7 ( + .dt (gpio_t[48:0]), + .di (gpio_o[48:0]), + .do (gpio_i[48:0]), + .dio ({ gpio_txnrx, // 48 + gpio_enable, // 47 + gpio_resetb, // 46 + gpio_sync, // 45 + gpio_en_agc, // 44 + gpio_ctl, // 40 + gpio_status, // 32 + gpio_wire, // 15 + gpio_bd})); // 0 + + prcfg_system_top i_prcfg_system_top ( + .clk(clk), + .adc_gpio_input(adc_gpio_input), + .adc_gpio_output(adc_gpio_output), + .dac_gpio_input(dac_gpio_input), + .dac_gpio_output(dac_gpio_output), + .dma_dac_drd(dma_dac_drd), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .core_dac_drd(core_dac_drd), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf)); + + system_wrapper i_system_wrapper ( + + .DDR_addr (DDR_addr), + .DDR_ba (DDR_ba), + .DDR_cas_n (DDR_cas_n), + .DDR_ck_n (DDR_ck_n), + .DDR_ck_p (DDR_ck_p), + .DDR_cke (DDR_cke), + .DDR_cs_n (DDR_cs_n), + .DDR_dm (DDR_dm), + .DDR_dq (DDR_dq), + .DDR_dqs_n (DDR_dqs_n), + .DDR_dqs_p (DDR_dqs_p), + .DDR_odt (DDR_odt), + .DDR_ras_n (DDR_ras_n), + .DDR_reset_n (DDR_reset_n), + .DDR_we_n (DDR_we_n), + + .FIXED_IO_ddr_vrn (FIXED_IO_ddr_vrn), + .FIXED_IO_ddr_vrp (FIXED_IO_ddr_vrp), + .FIXED_IO_mio (FIXED_IO_mio), + .FIXED_IO_ps_clk (FIXED_IO_ps_clk), + .FIXED_IO_ps_porb (FIXED_IO_ps_porb), + .FIXED_IO_ps_srstb (FIXED_IO_ps_srstb), + + .GPIO_I (gpio_i), + .GPIO_O (gpio_o), + .GPIO_T (gpio_t), + + .hdmi_data (hdmi_data), + .hdmi_data_e (hdmi_data_e), + .hdmi_hsync (hdmi_hsync), + .hdmi_out_clk (hdmi_out_clk), + .hdmi_vsync (hdmi_vsync), + + .iic_main_scl_io (iic_scl), + .iic_main_sda_io (iic_sda), + + .rx_clk_in_n (rx_clk_in_n), + .rx_clk_in_p (rx_clk_in_p), + .rx_data_in_n (rx_data_in_n), + .rx_data_in_p (rx_data_in_p), + .rx_frame_in_n (rx_frame_in_n), + .rx_frame_in_p (rx_frame_in_p), + + .spdif (spdif), + + .spi_csn_i (1'b1), + .spi_csn_o (spi_csn), + .spi_miso_i (spi_miso), + .spi_mosi_i (1'b0), + .spi_mosi_o (spi_mosi), + .spi_sclk_i (1'b0), + .spi_sclk_o (spi_clk), + + .tx_clk_out_n (tx_clk_out_n), + .tx_clk_out_p (tx_clk_out_p), + .tx_data_out_n (tx_data_out_n), + .tx_data_out_p (tx_data_out_p), + .tx_frame_out_n (tx_frame_out_n), + .tx_frame_out_p (tx_frame_out_p), + // pr related ports + .clk(clk), + + .dma_dac_drd(dma_dac_drd), + .dma_dac_dunf(dma_dac_dunf), + .dma_dac_ddata(dma_dac_ddata), + .core_dac_drd(core_dac_drd), + .core_dac_dunf(core_dac_dunf), + .core_dac_ddata(core_dac_ddata), + + .core_adc_dwr(core_adc_dwr), + .core_adc_dsync(core_adc_dsync), + .core_adc_ddata(core_adc_ddata), + .core_adc_ovf(core_adc_ovf), + .dma_adc_dwr(dma_adc_dwr), + .dma_adc_dsync(dma_adc_dsync), + .dma_adc_ddata(dma_adc_ddata), + .dma_adc_ovf(dma_adc_ovf), + + .up_dac_gpio_in(dac_gpio_output), + .up_adc_gpio_in(adc_gpio_output), + .up_dac_gpio_out(dac_gpio_input), + .up_adc_gpio_out(adc_gpio_input)); + +endmodule + +// black box definition for PR module +(* black_box *) module prcfg_system_top ( + input clk, + input [31:0] adc_gpio_input, + output [31:0] adc_gpio_output, + input [31:0] dac_gpio_input, + output [31:0] dac_gpio_output, + output dma_dac_drd, + input dma_dac_dunf, + input [63:0] dma_dac_ddata, + input core_dac_drd, + output core_dac_dunf, + output [63:0] core_dac_ddata, + input core_adc_dwr, + input core_adc_dsync, + input [63:0] core_adc_ddata, + output core_adc_ovf, + output dma_adc_dwr, + output dma_adc_dsync, + output [63:0] dma_adc_ddata, + input dma_adc_ovf); + +endmodule + +// *************************************************************************** +// ***************************************************************************