diff --git a/library/xilinx/axi_dacfifo/axi_dacfifo.v b/library/xilinx/axi_dacfifo/axi_dacfifo.v
index 496360775..88077d018 100644
--- a/library/xilinx/axi_dacfifo/axi_dacfifo.v
+++ b/library/xilinx/axi_dacfifo/axi_dacfifo.v
@@ -118,7 +118,6 @@ module axi_dacfifo (
   parameter   AXI_ADDRESS = 32'h00000000;
   parameter   AXI_ADDRESS_LIMIT = 32'hffffffff;
   parameter   AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
-  parameter   BYPASS_EN = 1;
 
   // dma interface
 
@@ -311,34 +310,23 @@ module axi_dacfifo (
 
   // bypass logic
 
-  generate if (BYPASS_EN == 1) begin
+  util_axis_resize #(
+    .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
+    .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
+  ) i_util_axis_resize (
+    .clk (axi_clk),
+    .resetn (axi_resetn),
+    .s_valid (dma_valid),
+    .s_ready (dma_ready_bp_s),
+    .s_data (dma_data),
+    .m_valid (dma_valid_bp_s),
+    .m_ready (axi_rd_ready_s),
+    .m_data (dma_data_bp_s)
+  );
 
-    util_axis_resize #(
-      .MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
-      .SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
-    ) i_util_axis_resize (
-      .clk (axi_clk),
-      .resetn (axi_resetn),
-      .s_valid (dma_valid),
-      .s_ready (dma_ready_bp_s),
-      .s_data (dma_data),
-      .m_valid (dma_valid_bp_s),
-      .m_ready (axi_rd_ready_s),
-      .m_data (dma_data_bp_s)
-    );
-
-    assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
-    assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
-    assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
-
-  end else begin
-
-    assign  dac_rd_valid_s = axi_rd_valid_s;
-    assign  dac_rd_data_s = axi_rd_data_s;
-    assign  dma_ready = dma_ready_s;
-
-  end
-  endgenerate
+  assign  dac_rd_valid_s = (dac_fifo_bypass) ? dma_valid_bp_s : axi_rd_valid_s;
+  assign  dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
+  assign  dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
 
 endmodule
 
diff --git a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
index 13cc3cb3f..735870609 100644
--- a/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
+++ b/projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
@@ -50,7 +50,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
   set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
   set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
-  set_property -dict [list CONFIG.BYPASS_EN {1}] $axi_dacfifo
 
   ## clock and reset