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axi_dacfifo: Delete redundant parameter BYPASS_EN

main
Istvan Csomortani 2017-02-16 19:53:44 +02:00
parent 8453d758c2
commit 95a4ea20c8
2 changed files with 16 additions and 29 deletions
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12
library/xilinx/axi_dacfifo/axi_dacfifo.v
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@ -118,7 +118,6 @@ module axi_dacfifo (
parameter AXI_ADDRESS = 32'h00000000;
parameter AXI_ADDRESS_LIMIT = 32'hffffffff;
parameter AXI_BYTE_WIDTH = AXI_DATA_WIDTH/8;
parameter BYPASS_EN = 1;
// dma interface
@ -311,8 +310,6 @@ module axi_dacfifo (
// bypass logic
generate if (BYPASS_EN == 1) begin
util_axis_resize #(
.MASTER_DATA_WIDTH (AXI_DATA_WIDTH),
.SLAVE_DATA_WIDTH (DMA_DATA_WIDTH)
@ -331,14 +328,5 @@ module axi_dacfifo (
assign dac_rd_data_s = (dac_fifo_bypass) ? dma_data_bp_s : axi_rd_data_s;
assign dma_ready = (dac_fifo_bypass) ? dma_ready_bp_s : dma_ready_s;
end else begin
assign dac_rd_valid_s = axi_rd_valid_s;
assign dac_rd_data_s = axi_rd_data_s;
assign dma_ready = dma_ready_s;
end
endgenerate
endmodule

1
projects/common/zc706/zc706_system_plddr3_dacfifo.tcl
View File

@ -50,7 +50,6 @@ proc p_plddr3_dacfifo {p_name m_name dma_data_width dac_data_width} {
set_property -dict [list CONFIG.AXI_LENGTH {15}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS {0x80000000}] $axi_dacfifo
set_property -dict [list CONFIG.AXI_ADDRESS_LIMIT {0xa0000000}] $axi_dacfifo
set_property -dict [list CONFIG.BYPASS_EN {1}] $axi_dacfifo
## clock and reset