From 95c143412db439c0f6bd1fa39364cde5e3a60359 Mon Sep 17 00:00:00 2001 From: Adrian Costina Date: Fri, 29 Aug 2014 13:53:59 +0300 Subject: [PATCH] fmcomms2: Modified design to work with 4 channel util_adc_pack --- projects/fmcomms2/common/fmcomms2_bd.tcl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/projects/fmcomms2/common/fmcomms2_bd.tcl b/projects/fmcomms2/common/fmcomms2_bd.tcl index c2e8b15c2..c7104e9e2 100755 --- a/projects/fmcomms2/common/fmcomms2_bd.tcl +++ b/projects/fmcomms2/common/fmcomms2_bd.tcl @@ -49,6 +49,7 @@ # channel packing for the ADC set util_adc_pack [create_bd_cell -type ip -vlnv analog.com:user:util_adc_pack:1.0 util_adc_pack] + set_property -dict [list CONFIG.CHANNELS {4}] $util_adc_pack set util_dac_unpack [create_bd_cell -type ip -vlnv analog.com:user:util_dac_unpack:1.0 util_dac_unpack] @@ -72,7 +73,7 @@ if {$sys_zynq == 1} { set_property -dict [list CONFIG.C_CLKS_ASYNC_SRC_DEST {1}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_CLKS_ASYNC_REQ_SRC {1}] $axi_ad9361_adc_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_ad9361_adc_dma - set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {128}] $axi_ad9361_adc_dma + set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {64}] $axi_ad9361_adc_dma if {$sys_zynq == 1} { set axi_ad9361_adc_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_ad9361_adc_dma_interconnect]