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projects: Update .v files according to guideline 

Deleted lines after endmodule and consecutive empty lines.
Modified parentheses, extra spaces.
Fixed indentation.
Fixed parameters list to be each parameter on its line.

Signed-off-by: Iulia Moldovan <iulia.moldovan@analog.com>
main
Iulia Moldovan 2022-04-14 16:13:22 +03:00 committed by imoldovan
parent 0c0617d49e
commit 961ebe0cc2
145 changed files with 1401 additions and 1450 deletions
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7
projects/ad40xx_fmc/zed/system_top_ad40xx.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -91,7 +90,8 @@ module system_top (
output ad40xx_spi_sclk,
output ad40xx_spi_cs,
inout ad40xx_amp_pd);
inout ad40xx_amp_pd
);
// internal signals
@ -211,6 +211,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad40xx_fmc/zed/system_top_adaq400x.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -89,7 +88,8 @@ module system_top (
input adaq400x_spi_sdi,
output adaq400x_spi_sdo,
output adaq400x_spi_sclk,
output adaq400x_spi_cs);
output adaq400x_spi_cs
);
// internal signals
@ -201,6 +201,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

21
projects/ad4630_fmc/zed/system_top.v
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@ -37,8 +37,7 @@
module system_top #(
parameter NUM_OF_SDI = 2
)(
) (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
@ -97,7 +96,6 @@ module system_top #(
output ad463x_cnv,
input ad463x_busy,
inout ad463x_resetn
);
// internal signals
@ -119,24 +117,22 @@ module system_top #(
assign gpio_i[63:33] = 31'b0;
ad_data_clk #(
.SINGLE_ENDED (1))
i_ext_clk (
.SINGLE_ENDED (1)
) i_ext_clk (
.rst (1'b0),
.locked (),
.clk_in_p (ad463x_ext_clk),
.clk_in_n (1'b0),
.clk (ext_clk_s)
);
.clk (ext_clk_s));
ad_data_clk #(
.SINGLE_ENDED (1))
i_echo_sclk (
.SINGLE_ENDED (1)
) i_echo_sclk (
.rst (1'b0),
.locked (),
.clk_in_p (ad463x_echo_sclk),
.clk_in_n (1'b0),
.clk (ad463x_echo_sclk_s)
);
.clk (ad463x_echo_sclk_s));
ad_iobuf #(
.DATA_WIDTH(1)
@ -243,6 +239,3 @@ module system_top #(
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

8
projects/ad469x_fmc/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -91,9 +90,10 @@ module system_top (
output ad469x_spi_sclk,
output ad469x_spi_cs,
output ad469x_spi_cnv,
input ad469x_busy_alt_gp0,
inout ad469x_resetn);
inout ad469x_resetn
);
// internal signals
@ -215,5 +215,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************

7
projects/ad5758_sdz/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -91,7 +90,8 @@ module system_top (
input spi_sdi,
output spi_sdo,
output spi_sclk,
output spi_sync_n);
output spi_sync_n
);
// internal signals
@ -202,6 +202,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad5766_sdz/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -89,7 +88,8 @@ module system_top (
output spi_sclk,
output spi_cs,
inout reset);
inout reset
);
// internal signals
@ -191,6 +191,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

16
projects/ad6676evb/vc707/system_top.v
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@ -110,7 +110,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -150,7 +151,9 @@ module system_top (
.O (rx_sync_p),
.OB (rx_sync_n));
ad_iobuf #(.DATA_WIDTH(10)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(10)
) i_iobuf (
.dio_t (gpio_t[41:32]),
.dio_i (gpio_o[41:32]),
.dio_o (gpio_i[41:32]),
@ -165,7 +168,9 @@ module system_top (
adc_agc3,
adc_agc4}));
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(21)
) i_iobuf_bd (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
@ -236,9 +241,6 @@ module system_top (
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout));
.uart_sout (uart_sout));
endmodule
// ***************************************************************************
// ***************************************************************************

16
projects/ad6676evb/zc706/system_top.v
View File

@ -96,7 +96,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -114,7 +115,7 @@ module system_top (
wire rx_ref_clk;
wire rx_sync;
wire rx_sysref;
wire rx_clk;
wire rx_clk;
assign gpio_i[63:42]= gpio_o[63:42];
assign gpio_i[31:15]= gpio_o[31:15];
@ -143,7 +144,9 @@ module system_top (
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
ad_iobuf #(.DATA_WIDTH(10)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(10)
) i_iobuf (
.dio_t (gpio_t[41:32]),
.dio_i (gpio_o[41:32]),
.dio_o (gpio_i[41:32]),
@ -158,7 +161,9 @@ module system_top (
adc_agc3,
adc_agc4}));
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -230,6 +235,3 @@ module system_top (
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad7134_fmc/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -109,7 +108,8 @@ module system_top (
// ad713x reference clock (not used by default)
output ad713x_sdpclk);
output ad713x_sdpclk
);
// internal signals
@ -226,6 +226,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad738x_fmc/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -88,7 +87,8 @@ module system_top (
input spi_sdib,
output spi_sdo,
output spi_sclk,
output spi_cs);
output spi_cs
);
// internal signals
@ -181,6 +181,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad7405_fmc/zed/system_top_differential.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -87,7 +86,8 @@ module system_top (
output adc_clk_p,
output adc_clk_n,
input adc_data_p,
input adc_data_n);
input adc_data_n
);
// internal signals
@ -228,6 +228,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

8
projects/ad7405_fmc/zed/system_top_singlended.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -85,7 +84,8 @@ module system_top (
input otg_vbusoc,
output adc_clk,
input adc_data);
input adc_data
);
// internal signals
@ -105,7 +105,6 @@ module system_top (
assign gpio_i[63:49] = 15'b0;
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
@ -215,6 +214,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

13
projects/ad7616_sdz/zc706/system_top_pi.v
View File

@ -83,7 +83,8 @@ module system_top (
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel);
output [ 2:0] adc_chsel
);
// internal signals
@ -99,7 +100,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
ad_iobuf #(
.DATA_WIDTH(7)
) i_iobuf_adc_cntrl (
.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
@ -166,10 +169,6 @@ module system_top (
.rx_db_i (adc_db_i),
.rx_db_t (adc_db_t),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n)
);
.rx_wr_n (adc_wr_n));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/ad7616_sdz/zc706/system_top_si.v
View File

@ -86,7 +86,8 @@ module system_top (
output [ 2:0] adc_chsel,
output adc_crcen,
output adc_burst,
output [ 2:0] adc_os);
output [ 2:0] adc_os
);
// internal signals
@ -96,7 +97,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -157,6 +160,3 @@ module system_top (
.rx_busy (adc_busy));
endmodule
// ***************************************************************************
// ***************************************************************************

13
projects/ad7616_sdz/zed/system_top_pi.v
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@ -93,7 +93,8 @@ module system_top (
input adc_busy,
output adc_seq_en,
output [ 1:0] adc_hw_rngsel,
output [ 2:0] adc_chsel);
output [ 2:0] adc_chsel
);
// internal signals
@ -115,7 +116,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(7)) i_iobuf_adc_cntrl (
ad_iobuf #(
.DATA_WIDTH(7)
) i_iobuf_adc_cntrl (
.dio_t ({gpio_t[43:41], gpio_t[37], gpio_t[35:33]}),
.dio_i ({gpio_o[43:41], gpio_o[37], gpio_o[35:33]}),
.dio_o ({gpio_i[43:41], gpio_i[37], gpio_i[35:33]}),
@ -214,10 +217,6 @@ module system_top (
.rx_db_i (adc_db_i),
.rx_db_t (adc_db_t),
.rx_rd_n (adc_rd_n),
.rx_wr_n (adc_wr_n)
);
.rx_wr_n (adc_wr_n));
endmodule
// ***************************************************************************
// ***************************************************************************

13
projects/ad7616_sdz/zed/system_top_si.v
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@ -96,7 +96,8 @@ module system_top (
output [ 2:0] adc_chsel,
output adc_crcen,
output adc_burst,
output [ 2:0] adc_os);
output [ 2:0] adc_os
);
// internal signals
@ -112,7 +113,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf_adc_cntrl (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf_adc_cntrl (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -200,10 +203,6 @@ module system_top (
.rx_sdo (spi_sdo),
.rx_sdi (spi_sdi),
.rx_cs_n (spi_cs_n),
.rx_busy (adc_busy)
);
.rx_busy (adc_busy));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad77681evb/zed/system_top.v
View File

@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -93,7 +92,8 @@ module system_top (
output ad7768_spi_mosi,
output ad7768_spi_sclk,
output ad7768_spi_cs,
input ad7768_drdy);
input ad7768_drdy
);
// internal signals
@ -219,6 +219,3 @@ module system_top (
.adc_data_ready (ad7768_drdy));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/ad7768evb/common/ad7768_if.v
View File

@ -74,7 +74,8 @@ module ad7768_if (
input up_crc_enable,
input up_crc_4_or_16_n,
input [ 35:0] up_status_clr,
output [ 35:0] up_status);
output [ 35:0] up_status
);
// internal registers
@ -495,7 +496,6 @@ module ad7768_if (
end
end
// data (common)
assign adc_cnt_enable_1_s = (adc_cnt_p <= 9'h01f) ? 1'b1 : 1'b0;
@ -569,6 +569,3 @@ module ad7768_if (
end
endmodule
// ***************************************************************************
// ***************************************************************************

22
projects/ad7768evb/zed/system_top.v
View File

@ -101,7 +101,8 @@ module system_top (
inout start_n,
inout sync_n,
inout sync_in_n,
output mclk);
output mclk
);
// internal signals
@ -145,7 +146,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(9)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(9)
) i_iobuf (
.dio_t ({gpio_t[52:48], gpio_t[43:40]}),
.dio_i ({gpio_o[52:48], gpio_o[43:40]}),
.dio_o ({gpio_i[52:48], gpio_i[43:40]}),
@ -159,7 +162,9 @@ module system_top (
start_n, // 41
reset_n})); // 40
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_bd (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
@ -170,13 +175,17 @@ module system_top (
assign gpio_i[47:44] = gpio_o[47:44];
assign gpio_i[63:53] = gpio_o[63:53];
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t ({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iic_mux_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t ({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
@ -290,6 +299,3 @@ module system_top (
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************

15
projects/ad9081_fmca_ebz/a10soc/system_top.v
View File

@ -159,8 +159,7 @@ module system_top #(
output rstb,
output [1:0] rxen,
output [1:0] txen
);
);
// internal signals
@ -180,7 +179,9 @@ module system_top #(
assign spi0_mosi = spi_mosi;
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_hmc (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi_hmc (
.spi_csn (spi_csn_s[1]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
@ -215,7 +216,6 @@ module system_top #(
assign txen[0] = gpio_o[58];
assign txen[1] = gpio_o[59];
// board stuff (max-v-u21)
assign gpio_i[31:14] = gpio_o[31:14];
@ -327,11 +327,6 @@ module system_top #(
.rx_ref_clk_clk (fpga_refclk_in),
.rx_sync_export (fpga_syncout_0),
.rx_sysref_export (sysref2),
.rx_device_clk_clk (clkin6)
);
.rx_device_clk_clk (clkin6));
endmodule
// ***************************************************************************
// ***************************************************************************

42
projects/ad9081_fmca_ebz/vck190/system_top.v
View File

@ -36,12 +36,12 @@
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 4,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 4,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
parameter TX_JESD_L = 4,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 4,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
input sys_clk_n,
input sys_clk_p,
output ddr4_act_n,
@ -102,7 +102,6 @@ module system_top #(
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
@ -166,19 +165,20 @@ module system_top #(
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
.O (tx_device_clk));
BUFG i_rx_device_clk (
.I (clkin10),
.O (rx_device_clk)
);
.O (rx_device_clk));
// spi
assign spi0_csb = spi0_csn[0];
assign spi1_csb = spi1_csn[0];
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi (
.spi_csn (spi1_csn[0]),
.spi_clk (spi1_sclk),
.spi_mosi (spi1_mosi),
@ -188,7 +188,9 @@ module system_top #(
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -217,7 +219,9 @@ module system_top #(
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
assign tx_syncin[1] = fpga_syncin_1_p;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncin_iobuf (
.dio_t (gpio_t[61:60]),
.dio_i (gpio_o[61:60]),
.dio_o (gpio_i[61:60]),
@ -229,7 +233,9 @@ module system_top #(
assign fpga_syncout_1_p = rx_syncout[1];
assign fpga_syncout_1_n = 0;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncout_iobuf (
.dio_t (gpio_t[63:62]),
.dio_i (gpio_o[63:62]),
.dio_o (gpio_i[63:62]),
@ -298,8 +304,7 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
.tx_sysref_0 (sysref));
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
@ -308,6 +313,3 @@ module system_top #(
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

39
projects/ad9081_fmca_ebz/vcu118/system_top.v
View File

@ -35,14 +35,12 @@
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1
) (
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1
) (
input sys_rst,
input sys_clk_p,
input sys_clk_n,
@ -120,7 +118,6 @@ module system_top #(
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
@ -200,13 +197,12 @@ module system_top #(
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
.O (tx_device_clk));
BUFG_GT i_rx_device_clk (
.I (clkin8),
.O (rx_device_clk)
);
.O (rx_device_clk));
// spi
assign spi0_csb = spi_csn[0];
@ -219,7 +215,9 @@ module system_top #(
assign spi_miso = ~spi_csn[0] ? spi0_miso :
~spi_csn[1] ? spi1_miso : 1'b0;
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi (
.spi_csn (spi_csn[1]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
@ -229,7 +227,9 @@ module system_top #(
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -254,8 +254,9 @@ module system_top #(
assign txen[0] = gpio_o[58];
assign txen[1] = gpio_o[59];
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(17)
) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
@ -349,13 +350,9 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
.tx_sysref_0 (sysref));
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

50
projects/ad9081_fmca_ebz/vcu128/system_top.v
View File

@ -35,16 +35,13 @@
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
input sys_rst,
input sys_clk_p,
input sys_clk_n,
@ -123,7 +120,6 @@ module system_top #(
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
@ -149,7 +145,6 @@ module system_top #(
wire tx_device_clk;
wire rx_device_clk;
// instantiations
IBUFDS_GTE4 i_ibufds_ref_clk (
@ -187,13 +182,12 @@ module system_top #(
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
.O (tx_device_clk));
BUFG_GT i_rx_device_clk (
.I (clkin8),
.O (rx_device_clk)
);
.O (rx_device_clk));
// spi
assign spi0_csb = spi_csn[0];
@ -206,7 +200,9 @@ module system_top #(
assign spi_miso = ~spi_csn[0] ? spi0_miso :
~spi_csn[1] ? spi1_miso : 1'b0;
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi (
.spi_csn (spi_csn[1]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi),
@ -216,7 +212,9 @@ module system_top #(
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -245,7 +243,9 @@ module system_top #(
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
assign tx_syncin[1] = fpga_syncin_1_p;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncin_iobuf (
.dio_t (gpio_t[61:60]),
.dio_i (gpio_o[61:60]),
.dio_o (gpio_i[61:60]),
@ -257,7 +257,9 @@ module system_top #(
assign fpga_syncout_1_p = rx_syncout[1];
assign fpga_syncout_1_n = 0;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncout_iobuf (
.dio_t (gpio_t[63:62]),
.dio_i (gpio_o[63:62]),
.dio_o (gpio_i[63:62]),
@ -266,7 +268,9 @@ module system_top #(
end
endgenerate
ad_iobuf #(.DATA_WIDTH(8)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(8)
) i_iobuf_bd (
.dio_t (gpio_t[7:0]),
.dio_i (gpio_o[7:0]),
.dio_o (gpio_i[7:0]),
@ -360,13 +364,9 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
.tx_sysref_0 (sysref));
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

46
projects/ad9081_fmca_ebz/zc706/system_top.v
View File

@ -36,13 +36,12 @@
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter JESD_MODE = "8B10B"
) (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
@ -118,7 +117,6 @@ module system_top #(
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
@ -185,19 +183,20 @@ module system_top #(
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
.O (tx_device_clk));
BUFG i_rx_device_clk (
.I (clkin10),
.O (rx_device_clk)
);
.O (rx_device_clk));
// spi
assign spi0_csb = spi0_csn[0];
assign spi1_csb = spi1_csn[0];
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi (
.spi_csn (spi1_csn[0]),
.spi_clk (spi1_sclk),
.spi_mosi (spi1_mosi),
@ -207,7 +206,9 @@ module system_top #(
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -236,7 +237,9 @@ module system_top #(
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
assign tx_syncin[1] = fpga_syncin_1_p;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncin_iobuf (
.dio_t (gpio_t[61:60]),
.dio_i (gpio_o[61:60]),
.dio_o (gpio_i[61:60]),
@ -248,7 +251,9 @@ module system_top #(
assign fpga_syncout_1_p = rx_syncout[1];
assign fpga_syncout_1_n = 0;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncout_iobuf (
.dio_t (gpio_t[63:62]),
.dio_i (gpio_o[63:62]),
.dio_o (gpio_i[63:62]),
@ -264,8 +269,7 @@ module system_top #(
.dio_t (gpio_t[0+:15]),
.dio_i (gpio_o[0+:15]),
.dio_o (gpio_i[0+:15]),
.dio_p (gpio_bd)
);
.dio_p (gpio_bd));
// Unused GPIOs
assign gpio_i[59:54] = gpio_o[59:54];
@ -362,8 +366,7 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
.tx_sysref_0 (sysref));
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
@ -372,6 +375,3 @@ module system_top #(
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

68
projects/ad9081_fmca_ebz/zcu102/system_top.v
View File

@ -35,20 +35,17 @@
`timescale 1ns/100ps
module system_top #(
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter SHARED_DEVCLK = 0,
parameter JESD_MODE = "8B10B"
) (
parameter TX_JESD_L = 8,
parameter TX_NUM_LINKS = 1,
parameter RX_JESD_L = 8,
parameter RX_NUM_LINKS = 1,
parameter SHARED_DEVCLK = 0,
parameter JESD_MODE = "8B10B"
) (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
// FMC HPC IOs
input [1:0] agc0,
input [1:0] agc1,
@ -88,7 +85,6 @@ module system_top #(
input sysref2_n,
input sysref2_p,
output [1:0] txen
);
// internal signals
@ -156,23 +152,22 @@ module system_top #(
BUFG i_tx_device_clk (
.I (clkin6),
.O (tx_device_clk)
);
.O (tx_device_clk));
BUFG i_rx_device_clk (
.I (clkin10),
.O (rx_device_clk_internal)
);
.O (rx_device_clk_internal));
assign rx_device_clk = SHARED_DEVCLK ? tx_device_clk : rx_device_clk_internal;
// spi
assign spi0_csb = spi0_csn[0];
assign spi1_csb = spi1_csn[0];
assign spi0_csb = spi0_csn[0];
assign spi1_csb = spi1_csn[0];
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi (
.spi_csn (spi1_csn[0]),
.spi_clk (spi1_sclk),
.spi_mosi (spi1_mosi),
@ -182,7 +177,9 @@ module system_top #(
// gpios
ad_iobuf #(.DATA_WIDTH(12)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(12)
) i_iobuf (
.dio_t (gpio_t[43:32]),
.dio_i (gpio_o[43:32]),
.dio_o (gpio_i[43:32]),
@ -200,18 +197,20 @@ module system_top #(
assign gpio_i[52] = irqb[0];
assign gpio_i[53] = irqb[1];
assign hmc_sync = gpio_o[54];
assign rstb = gpio_o[55];
assign rxen[0] = gpio_o[56];
assign rxen[1] = gpio_o[57];
assign txen[0] = gpio_o[58];
assign txen[1] = gpio_o[59];
assign hmc_sync = gpio_o[54];
assign rstb = gpio_o[55];
assign rxen[0] = gpio_o[56];
assign rxen[1] = gpio_o[57];
assign txen[0] = gpio_o[58];
assign txen[1] = gpio_o[59];
generate
generate
if (TX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
assign tx_syncin[1] = fpga_syncin_1_p;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncin_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncin_iobuf (
.dio_t (gpio_t[61:60]),
.dio_i (gpio_o[61:60]),
.dio_o (gpio_i[61:60]),
@ -221,9 +220,11 @@ module system_top #(
if (RX_NUM_LINKS > 1 & JESD_MODE == "8B10B") begin
assign fpga_syncout_1_p = rx_syncout[1];
assign fpga_syncout_1_n = 0;
assign fpga_syncout_1_n = 0;
end else begin
ad_iobuf #(.DATA_WIDTH(2)) i_syncout_iobuf (
ad_iobuf #(
.DATA_WIDTH(2)
) i_syncout_iobuf (
.dio_t (gpio_t[63:62]),
.dio_i (gpio_o[63:62]),
.dio_o (gpio_i[63:62]),
@ -293,8 +294,7 @@ module system_top #(
.rx_sync_0 (rx_syncout),
.tx_sync_0 (tx_syncin),
.rx_sysref_0 (sysref),
.tx_sysref_0 (sysref)
);
.tx_sysref_0 (sysref));
assign rx_data_p_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_p[RX_JESD_L*RX_NUM_LINKS-1:0];
assign rx_data_n_loc[RX_JESD_L*RX_NUM_LINKS-1:0] = rx_data_n[RX_JESD_L*RX_NUM_LINKS-1:0];
@ -302,8 +302,4 @@ module system_top #(
assign tx_data_p[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_p_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
assign tx_data_n[TX_JESD_L*TX_NUM_LINKS-1:0] = tx_data_n_loc[TX_JESD_L*TX_NUM_LINKS-1:0];
endmodule
// ***************************************************************************
// ***************************************************************************

13
projects/ad9083_evb/a10soc/system_top.v
View File

@ -126,7 +126,8 @@ module system_top (
output spi_csn_clk,
output spi_csn_adc,
output spi_clk,
inout spi_sdio);
inout spi_sdio
);
// internal signals
@ -144,15 +145,14 @@ module system_top (
assign spi_csn_clk = spi_csn_s[1];
ad_3w_spi #(
.NUM_OF_SLAVES(2))
i_spi (
.NUM_OF_SLAVES(2)
) i_spi (
.spi_csn (spi_csn_s[1:0]),
.spi_clk (spi_clk),
.spi_mosi (spi_mosi_s),
.spi_miso (spi_miso_s),
.spi_sdio (spi_sdio),
.spi_dir ()
);
.spi_dir ());
// gpio in & out are separate cores
@ -259,6 +259,3 @@ module system_top (
.sys_spi_SS_n (spi_csn_s));
endmodule
// ***************************************************************************
// ***************************************************************************

23
projects/ad9083_evb/zcu102/system_top.v
View File

@ -102,12 +102,11 @@ module system_top (
IBUFDS IBUFDS_inst (
.O(rx_ref_core_clk0_s),
.I(glblclk_p),
.IB(glblclk_n)
);
.IB(glblclk_n));
BUFG BUFG_inst (
.O(rx_ref_core_clk0),
.I(rx_ref_core_clk0_s)
);
.I(rx_ref_core_clk0_s));
IBUFDS_GTE4 i_ibufds_ref_clk0 (
.CEB (1'd0),
@ -117,17 +116,18 @@ module system_top (
.ODIV2 ());
ad_3w_spi #(
.NUM_OF_SLAVES(2))
i_spi (
.NUM_OF_SLAVES(2)
) i_spi (
.spi_csn(spi0_csn[1:0]),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio),
.spi_dir(spidbg_dir)
);
.spi_dir(spidbg_dir));
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf (
.dio_t ({gpio_t[34:32]}),
.dio_i ({gpio_o[34:32]}),
.dio_o ({gpio_i[34:32]}),
@ -172,9 +172,6 @@ module system_top (
.spi1_csn (),
.spi1_miso (),
.spi1_mosi (),
.spi1_sclk ()
);
.spi1_sclk ());
endmodule
// ***************************************************************************

22
projects/ad9208_dual_ebz/vcu118/system_top.v
View File

@ -101,7 +101,6 @@
// DUTB_PDWN_TO_FPGA LA09_P D14 AJ33 adc1_pdwn IO_L19P_T3L_N0_DBC_AD9P_43
// HMC7044_SYNC_REQ_TO_FPGA LA13_N D18 AJ36 hmc_sync_req IO_L20N_T3L_N3_AD1N_43
module system_top (
input sys_rst,
@ -184,7 +183,6 @@ module system_top (
inout adc1_pdwn,
inout hmc_sync_req
);
// internal signals
@ -228,7 +226,6 @@ module system_top (
.O (rx_ref_clk_1),
.ODIV2 ());
IBUFDS i_ibufds_rx_sysref_0 (
.I (rx_sysref_0_p),
.IB (rx_sysref_0_n),
@ -258,9 +255,7 @@ module system_top (
BUFG_GT i_bufg(
.I (glbl_clk_0),
.O (glbl_clk_buf)
);
.O (glbl_clk_buf));
daq3_spi i_spi (
.spi_csn (spi_csn[2:0]),
@ -270,7 +265,9 @@ module system_top (
.spi_sdio (spi_sdio),
.spi_dir ());
ad_iobuf #(.DATA_WIDTH(11)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(11)
) i_iobuf (
.dio_t (gpio_t[42:32]),
.dio_i (gpio_o[42:32]),
.dio_o (gpio_i[42:32]),
@ -286,7 +283,9 @@ module system_top (
adc1_pdwn, // 33
hmc_sync_req})); // 32
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(17)
) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
@ -380,11 +379,6 @@ module system_top (
.rx_sync_0 (rx_sync_0),
.rx_sync_1_0 (rx_sync_1),
.rx_sysref_0 (rx_sysref_0),
.rx_sysref_1_0 (rx_sysref_0)
);
.rx_sysref_1_0 (rx_sysref_0));
endmodule
// ***************************************************************************
// ***************************************************************************

68
projects/ad9213_dual_ebz/s10soc/system_top.v
View File

@ -157,7 +157,6 @@ module system_top (
output adf4377_sclk,
inout adf4377_sdio,
output [ 1:0] adf4377_csn
);
// internal signals
@ -211,8 +210,8 @@ module system_top (
// instantiations
ad_3w_spi #(
.NUM_OF_SLAVES(2))
i_ad_3w_spi_ad9213_dual (
.NUM_OF_SLAVES(2)
) i_ad_3w_spi_ad9213_dual (
.spi_csn (ad9213_dual_csn),
.spi_clk (ad9213_dual_sclk),
.spi_mosi (spi_mosi_s),
@ -221,8 +220,8 @@ module system_top (
.spi_dir ());
ad_3w_spi #(
.NUM_OF_SLAVES(2))
i_ad_3w_spi_adf4377 (
.NUM_OF_SLAVES(2)
) i_ad_3w_spi_adf4377 (
.spi_csn (adf4377_csn),
.spi_clk (adf4377_sclk),
.spi_mosi (adf4377_sdi_s),
@ -238,39 +237,39 @@ module system_top (
// done reset
assign sys_resetn_s = fpga_resetn & ~h2f_reset_s & ~ninit_done_s;
genvar i;
for (i = 0; i < 512; i = i + 16) begin
genvar i;
for (i = 0; i < 512; i = i + 16) begin
assign adc_data[(2*i)+31:(2*i)] ={adc_data_1_swap[i+15:i],adc_data_0_swap[i+15:i]};
end
end
always @(posedge rx_device_clk_0) begin
adc_swap_d1 <= adc_swap;
adc_swap_d2 <= adc_swap_d1;
always @(posedge rx_device_clk_0) begin
adc_swap_d1 <= adc_swap;
adc_swap_d2 <= adc_swap_d1;
if (adc_swap_d2 == 1'b0) begin
adc_data_0_swap <= adc_data_0;
adc_data_1_swap <= adc_data_1;
end else begin
adc_data_0_swap <= adc_data_1;
adc_data_1_swap <= adc_data_0;
end
if (adc_swap_d2 == 1'b0) begin
adc_data_0_swap <= adc_data_0;
adc_data_1_swap <= adc_data_1;
end else begin
adc_data_0_swap <= adc_data_1;
adc_data_1_swap <= adc_data_0;
end
adc_data_0_d1 <= adc_data_0;
adc_data_1_d1 <= adc_data_1;
adc_data_0_d1 <= adc_data_0;
adc_data_1_d1 <= adc_data_1;
case ({adc_enable_1,adc_enable_0})
2'b01: adc_data_d1 <= {adc_data_0,adc_data_0_d1};
2'b10: adc_data_d1 <= {adc_data_1,adc_data_1_d1};
2'b11: adc_data_d1 <= adc_data;
default: adc_data_d1 <= adc_data_d1;
endcase
case ({adc_enable_1,adc_enable_0})
2'b01: adc_valid_d1 <= ~adc_valid_d1;
2'b10: adc_valid_d1 <= ~adc_valid_d1;
2'b11: adc_valid_d1<= adc_valid;
default: adc_valid_d1 <= adc_valid;
endcase
end
case ({adc_enable_1,adc_enable_0})
2'b01: adc_data_d1 <= {adc_data_0,adc_data_0_d1};
2'b10: adc_data_d1 <= {adc_data_1,adc_data_1_d1};
2'b11: adc_data_d1 <= adc_data;
default: adc_data_d1 <= adc_data_d1;
endcase
case ({adc_enable_1,adc_enable_0})
2'b01: adc_valid_d1 <= ~adc_valid_d1;
2'b10: adc_valid_d1 <= ~adc_valid_d1;
2'b11: adc_valid_d1<= adc_valid;
default: adc_valid_d1 <= adc_valid;
endcase
end
system_bd i_system_bd (
.sys_clk_clk ( sys_clk ),
@ -394,6 +393,3 @@ module system_top (
.ad9213_dual_pio_export ( {ad9213_b_gpio, ad9213_a_gpio} ));
endmodule
// ***************************************************************************
// ***************************************************************************

4
projects/ad9265_fmc/common/ad9265_spi.v
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@ -42,7 +42,8 @@ module ad9265_spi (
input spi_mosi,
output spi_miso,
inout spi_sdio);
inout spi_sdio
);
// internal registers
@ -88,4 +89,3 @@ module ad9265_spi (
assign spi_miso = spi_sdio;
endmodule

69
projects/ad9265_fmc/zc706/system_top.v
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@ -81,49 +81,51 @@ module system_top (
output spi_clk,
output spi_csn_adc,
output spi_csn_clk,
inout spi_sdio);
inout spi_sdio
);
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
// instantiations
// instantiations
assign spi_csn_adc = spi0_csn[0];
assign spi_csn_clk = spi0_csn[1];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
assign spi_csn_adc = spi0_csn[0];
assign spi_csn_clk = spi0_csn[1];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
assign spi0_miso = spi_miso;
ad_iobuf #(.DATA_WIDTH(15)) iobuf_gpio_bd (
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
.dio_p (gpio_bd));
ad_iobuf #(
.DATA_WIDTH(15)
) iobuf_gpio_bd (
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
.dio_p (gpio_bd));
assign gpio_i[63:15] = gpio_o[63:15];
assign gpio_i[63:15] = gpio_o[63:15];
ad9265_spi i_spi (
ad9265_spi i_spi (
.spi_csn(spi0_csn[1:0]),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
.spi_sdio(spi_sdio));
system_wrapper i_system_wrapper (
system_wrapper i_system_wrapper (
.ddr_addr(ddr_addr),
.ddr_ba(ddr_ba),
.ddr_cas_n(ddr_cas_n),
@ -182,6 +184,3 @@ system_wrapper i_system_wrapper (
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

9
projects/ad9434_fmc/common/ad9434_spi.v
View File

@ -42,7 +42,8 @@ module ad9434_spi (
input spi_mosi,
output spi_miso,
inout spi_sdio);
inout spi_sdio
);
// internal registers
@ -83,8 +84,10 @@ module ad9434_spi (
end
// io buffer
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_sdio (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_sdio (
.dio_t (spi_enable_s),
.dio_i (spi_mosi),
.dio_o (spi_miso),

12
projects/ad9434_fmc/zc706/system_top.v
View File

@ -83,7 +83,8 @@ module system_top (
output spi_csn_clk,
output spi_csn_adc,
output spi_sclk,
inout spi_dio);
inout spi_dio
);
// internal signals
@ -103,7 +104,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_gpio (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_gpio (
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
@ -114,8 +117,7 @@ module system_top (
.spi_clk(spi_sclk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_dio)
);
.spi_sdio(spi_dio));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
@ -175,6 +177,4 @@ module system_top (
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi));
endmodule

8
projects/ad9467_fmc/common/ad9467_spi.v
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@ -42,7 +42,8 @@ module ad9467_spi (
input spi_mosi,
output spi_miso,
inout spi_sdio);
inout spi_sdio
);
// internal registers
@ -84,11 +85,12 @@ module ad9467_spi (
// io buffer
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_sdio (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_sdio (
.dio_t (spi_enable_s),
.dio_i (spi_mosi),
.dio_o (spi_miso),
.dio_p (spi_sdio));
endmodule

149
projects/ad9467_fmc/kc705/system_top.v
View File

@ -100,7 +100,8 @@ module system_top (
output spi_clk,
output spi_csn_adc,
output spi_csn_clk,
inout spi_sdio);
inout spi_sdio
);
// internal signals
wire [ 7:0] spi_csn;
@ -120,85 +121,83 @@ module system_top (
assign spi_csn_clk = spi_csn[1];
ad9467_spi i_spi (
.spi_csn(spi_csn[1:0]),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
.spi_csn(spi_csn[1:0]),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio));
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_sw_led (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
ad_iobuf #(
.DATA_WIDTH(17)
) i_iobuf_sw_led (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
.dio_p (gpio_bd));
assign gpio_i[63:32] = gpio_o[63:32];
assign gpio_i[31:17] = gpio_o[31:17];
system_wrapper i_system_wrapper (
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_or_n (adc_data_or_n),
.adc_data_or_p (adc_data_or_p),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
.ddr3_addr (ddr3_addr),
.ddr3_ba (ddr3_ba),
.ddr3_cas_n (ddr3_cas_n),
.ddr3_ck_n (ddr3_ck_n),
.ddr3_ck_p (ddr3_ck_p),
.ddr3_cke (ddr3_cke),
.ddr3_cs_n (ddr3_cs_n),
.ddr3_dm (ddr3_dm),
.ddr3_dq (ddr3_dq),
.ddr3_dqs_n (ddr3_dqs_n),
.ddr3_dqs_p (ddr3_dqs_p),
.ddr3_odt (ddr3_odt),
.ddr3_ras_n (ddr3_ras_n),
.ddr3_reset_n (ddr3_reset_n),
.ddr3_we_n (ddr3_we_n),
.gpio_lcd_tri_io (gpio_lcd),
.gpio0_o (gpio_o[31:0]),
.gpio0_t (gpio_t[31:0]),
.gpio0_i (gpio_i[31:0]),
.gpio1_o (gpio_o[63:32]),
.gpio1_t (gpio_t[63:32]),
.gpio1_i (gpio_i[63:32]),
.iic_main_scl_io (iic_scl),
.iic_main_sda_io (iic_sda),
.mdio_mdc (mdio_mdc),
.mdio_mdio_io (mdio_mdio),
.mii_col (mii_col),
.mii_crs (mii_crs),
.mii_rst_n (mii_rst_n),
.mii_rx_clk (mii_rx_clk),
.mii_rx_dv (mii_rx_dv),
.mii_rx_er (mii_rx_er),
.mii_rxd (mii_rxd),
.mii_tx_clk (mii_tx_clk),
.mii_tx_en (mii_tx_en),
.mii_txd (mii_txd),
.linear_flash_addr (linear_flash_addr),
.linear_flash_adv_ldn (linear_flash_adv_ldn),
.linear_flash_ce_n (linear_flash_ce_n),
.linear_flash_dq_io (linear_flash_dq_io),
.linear_flash_oen (linear_flash_oen),
.linear_flash_wen (linear_flash_wen),
.sys_clk_n (sys_clk_n),
.sys_clk_p (sys_clk_p),
.sys_rst (sys_rst),
.uart_sin (uart_sin),
.uart_sout (uart_sout),
.adc_clk_in_n (adc_clk_in_n),
.adc_clk_in_p (adc_clk_in_p),
.adc_data_in_n (adc_data_in_n),
.adc_data_in_p (adc_data_in_p),
.adc_data_or_n (adc_data_or_n),
.adc_data_or_p (adc_data_or_p),
.spi_clk_i (1'b0),
.spi_clk_o (spi_clk),
.spi_csn_i (1'b1),
.spi_csn_o (spi_csn),
.spi_sdi_i (spi_miso),
.spi_sdo_i (1'b0),
.spi_sdo_o (spi_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

57
projects/ad9467_fmc/zed/system_top.v
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@ -91,25 +91,28 @@ module system_top (
output spi_clk,
output spi_csn_adc,
output spi_csn_clk,
inout spi_sdio);
inout spi_sdio
);
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// internal signals
wire [ 1:0] spi_csn;
wire spi_miso;
wire spi_mosi;
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
// instantiations
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_gpio (
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_gpio (
.dio_t ({gpio_t[31:0]}),
.dio_i ({gpio_o[31:0]}),
.dio_o ({gpio_i[31:0]}),
@ -117,30 +120,33 @@ wire iic_mux_sda_t_s;
assign gpio_i[63:32] = gpio_o[63:32];
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_scl (
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_sda (
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
.dio_p (iic_mux_sda));
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
assign spi_csn_adc = spi_csn[0];
assign spi_csn_clk = spi_csn[1];
ad9467_spi i_spi (
ad9467_spi i_spi (
.spi_csn(spi_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso),
.spi_sdio(spi_sdio)
);
.spi_sdio(spi_sdio));
system_wrapper i_system_wrapper (
system_wrapper i_system_wrapper (
.ddr_addr(ddr_addr),
.ddr_ba(ddr_ba),
.ddr_cas_n(ddr_cas_n),
@ -211,6 +217,3 @@ system_wrapper i_system_wrapper (
.spi1_sdo_o());
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/ad9656_fmc/zcu102/system_top.v
View File

@ -59,7 +59,8 @@ module system_top (
output spi_csn_ad9656,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -107,7 +108,7 @@ module system_top (
.I (sysref_out),
.O (sysref_out_p),
.OB (sysref_out_n));
IBUFDS i_ibufds_sysref (
.I (sysref_p),
.IB (sysref_n),
@ -129,7 +130,7 @@ module system_top (
.rx_data_2_p (rx_data_p[2]),
.rx_data_3_n (rx_data_n[3]),
.rx_data_3_p (rx_data_p[3]),
.rx_ref_clk_0 (ref_clk0),
.rx_ref_clk_0 (ref_clk0),
.rx_sync_0 (rx_sync),
.rx_sysref_0 (sysref),
.spi0_sclk (spi_clk),
@ -142,6 +143,3 @@ module system_top (
.spi1_mosi ());
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/ad9695_fmc/zcu102/system_top.v
View File

@ -93,7 +93,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf (
.dio_t ({gpio_t[34:32]}),
.dio_i ({gpio_o[34:32]}),
.dio_o ({gpio_i[34:32]}),
@ -161,10 +163,6 @@ module system_top (
.spi1_csn (spi1_csn),
.spi1_miso (pmod_spi_miso),
.spi1_mosi (pmod_spi_mosi),
.spi1_sclk (pmod_spi_clk)
);
.spi1_sclk (pmod_spi_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/ad9739a_fmc/zc706/system_top.v
View File

@ -86,7 +86,8 @@ module system_top (
output spi_csn_dac,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -112,7 +113,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -181,6 +184,3 @@ module system_top (
.spi1_sdo_o (spi1_mosi));
endmodule
// ***************************************************************************
// ***************************************************************************

17
projects/ad9783_ebz/zcu102/system_top.v
View File

@ -39,22 +39,23 @@ module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
// dci_p&n enter the chip
output dci_p,
output dci_n,
// dco_p&n leave the chip
input dco1_p,
input dco1_n,
output [15:0] data_p,
output [15:0] data_n,
output spi_clk,
output spi_dio,
input spi_do,
output spi_en);
output spi_en
);
// internal signals
@ -67,9 +68,8 @@ module system_top (
assign gpio_bd_o = gpio_o[20:13];
assign gpio_i[94:13] = gpio_o[94:13];
assign gpio_i[12: 0] = gpio_bd_i;
assign spi_en = spi_csb[0];
assign spi_en = spi_csb[0];
// instantiations
@ -93,6 +93,3 @@ module system_top (
.data_p (data_p));
endmodule
// ***************************************************************************
// ***************************************************************************

31
projects/ad_fmclidar1_ebz/a10soc/system_top.v
View File

@ -168,7 +168,6 @@ module system_top (
// Vref selects for AFE board
output [ 7:0] tia_chsel
);
// internal signals
@ -212,20 +211,19 @@ module system_top (
wire [31:0] adc_data_tia_chsel_s;
util_tia_chsel #(
.DATA_WIDTH (32))
i_util_tia_chsel (
.DATA_WIDTH (32)
) i_util_tia_chsel (
.clk (rx_device_clk),
.adc_tia_chsel_en (laser_driver),
.adc_data_tia_chsel (adc_data_tia_chsel_s),
.tia_chsel (tia_chsel)
);
.tia_chsel (tia_chsel));
wire dma_sync_s;
wire fifo_wr_en_s;
util_axis_syncgen #(
.ASYNC_SYNC (1))
i_util_axis_syncgen (
.ASYNC_SYNC (1)
) i_util_axis_syncgen (
.s_axis_aclk (rx_device_clk),
.s_axis_aresetn (1'b1),
.s_axis_ready (1'b1),
@ -240,8 +238,17 @@ module system_top (
wire i2c_0_sda_in;
wire i2c_0_sda_oe;
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c_0_scl_out), .o(i2c_0_scl_in), .io(afe_dac_scl));
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c_0_sda_oe), .o(i2c_0_sda_in), .io(afe_dac_sda));
ALT_IOBUF scl_iobuf (
.i(1'b0),
.oe(i2c_0_scl_out),
.o(i2c_0_scl_in),
.io(afe_dac_scl));
ALT_IOBUF sda_iobuf (
.i(1'b0),
.oe(i2c_0_sda_oe),
.o(i2c_0_sda_in),
.io(afe_dac_sda));
// Block design instance
@ -362,10 +369,6 @@ module system_top (
// DMA synchronization
.fifo_wr_en_out_valid (fifo_wr_en_s),
.fifo_wr_en_in_valid (fifo_wr_en_s),
.fifo_wr_sync_sync (dma_sync_s)
);
.fifo_wr_sync_sync (dma_sync_s));
endmodule
// ***************************************************************************
// ***************************************************************************

11
projects/ad_fmclidar1_ebz/common/util_axis_syncgen.v
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@ -37,15 +37,16 @@
module util_axis_syncgen #(
parameter ASYNC_SYNC = 1) (
parameter ASYNC_SYNC = 1
) (
input s_axis_aclk,
input s_axis_aresetn,
input s_axis_ready,
input s_axis_valid,
input ext_sync,
output s_axis_sync);
output s_axis_sync
);
wire sync_int_s;
wire sync_ack_s;
@ -58,8 +59,8 @@ module util_axis_syncgen #(
sync_bits #(
.NUM_OF_BITS (1),
.ASYNC_CLK (ASYNC_SYNC))
i_axis_ext_sync (
.ASYNC_CLK (ASYNC_SYNC)
) i_axis_ext_sync (
.in_bits (ext_sync),
.out_clk (s_axis_aclk),
.out_resetn (s_axis_aresetn),

7
projects/ad_fmclidar1_ebz/common/util_tia_chsel.v
View File

@ -37,14 +37,15 @@
module util_tia_chsel #(
parameter DATA_WIDTH = 32) (
parameter DATA_WIDTH = 32
) (
input clk,
input adc_tia_chsel_en,
output [DATA_WIDTH-1:0] adc_data_tia_chsel,
input [ 7:0] tia_chsel);
input [ 7:0] tia_chsel
);
(* keep = "TRUE" *)reg [DATA_WIDTH-1:0] adc_data_tia_chsel_int;

9
projects/ad_fmclidar1_ebz/zc706/system_top.v
View File

@ -139,7 +139,6 @@ module system_top (
// Vref selects for AFE board
output [ 7:0] tia_chsel
);
// internal signals
@ -191,7 +190,9 @@ module system_top (
// GPIO connections to the FMC connector
ad_iobuf #(.DATA_WIDTH(20)) i_fmc_iobuf (
ad_iobuf #(
.DATA_WIDTH(20)
) i_fmc_iobuf (
.dio_t ({gpio_t[51:38], 3'b0, gpio_t[34:32]}),
.dio_i ({gpio_o[51:32]}),
.dio_o ({gpio_i[51:32]}),
@ -210,7 +211,9 @@ module system_top (
// GPIO connections for the carrier
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),

8
projects/ad_fmclidar1_ebz/zcu102/system_top.v
View File

@ -37,7 +37,6 @@
module system_top (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
@ -107,7 +106,6 @@ module system_top (
// Vref selects for AFE board
output [ 7:0] tia_chsel
);
// internal signals
@ -145,7 +143,7 @@ module system_top (
.I (rx_device_clk_p),
.IB (rx_device_clk_n),
.O (rx_device_clk_ds));
BUFG i_rx_device_clk (
.I (rx_device_clk_ds),
.O (rx_device_clk));
@ -164,7 +162,9 @@ module system_top (
// GPIO connections to the FMC connector
ad_iobuf #(.DATA_WIDTH(20)) i_fmc_iobuf (
ad_iobuf #(
.DATA_WIDTH(20)
) i_fmc_iobuf (
.dio_t ({gpio_t[51:38], 3'b0, gpio_t[34:32]}),
.dio_i ({gpio_o[51:32]}),
.dio_o ({gpio_i[51:32]}),

348
projects/ad_quadmxfe1_ebz/common/quad_mxfe_gpio_mux.v
View File

@ -35,7 +35,7 @@
`timescale 1ns/100ps
module quad_mxfe_gpio_mux #() (
module quad_mxfe_gpio_mux (
inout mxfe0_gpio0,
inout mxfe0_gpio1,
@ -96,12 +96,13 @@ module quad_mxfe_gpio_mux #() (
input [127:64] gpio_t,
output [127:64] gpio_i,
input [127:64] gpio_o
);
wire gpio0_mode;
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_mxfe_0 (
ad_iobuf #(
.DATA_WIDTH(13)
) i_iobuf_mxfe_0 (
.dio_t ( {mxfe0_gpio0_t,
mxfe0_gpio1_t,
mxfe0_gpio2_t,
@ -153,10 +154,11 @@ module quad_mxfe_gpio_mux #() (
mxfe0_syncin_1_n,
mxfe0_syncin_1_p,
mxfe0_syncout_1_n,
mxfe0_syncout_1_p})
);
mxfe0_syncout_1_p}));
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_mxfe_1 (
ad_iobuf #(
.DATA_WIDTH(13)
) i_iobuf_mxfe_1 (
.dio_t ( {mxfe1_gpio0_t,
mxfe1_gpio1_t,
mxfe1_gpio2_t,
@ -208,10 +210,11 @@ module quad_mxfe_gpio_mux #() (
mxfe1_syncin_1_n,
mxfe1_syncin_1_p,
mxfe1_syncout_1_n,
mxfe1_syncout_1_p})
);
mxfe1_syncout_1_p}));
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_mxfe_2 (
ad_iobuf #(
.DATA_WIDTH(13)
) i_iobuf_mxfe_2 (
.dio_t ( {mxfe2_gpio0_t,
mxfe2_gpio1_t,
mxfe2_gpio2_t,
@ -265,7 +268,9 @@ module quad_mxfe_gpio_mux #() (
mxfe2_syncout_1_n,
mxfe2_syncout_1_p}));
ad_iobuf #(.DATA_WIDTH(13)) i_iobuf_mxfe_3 (
ad_iobuf #(
.DATA_WIDTH(13)
) i_iobuf_mxfe_3 (
.dio_t ( {mxfe3_gpio0_t,
mxfe3_gpio1_t,
mxfe3_gpio2_t,
@ -317,209 +322,206 @@ module quad_mxfe_gpio_mux #() (
mxfe3_syncin_1_n,
mxfe3_syncin_1_p,
mxfe3_syncout_1_n,
mxfe3_syncout_1_p})
);
mxfe3_syncout_1_p}));
// Bidirectional buffer output enables
assign {mxfe0_gpio0_t,
mxfe1_gpio0_t,
mxfe2_gpio0_t,
mxfe3_gpio0_t} = gpio0_mode ? 4'b0001 : {4{gpio_t[64]}};
// Bidirectional buffer output enables
assign {mxfe0_gpio0_t,
mxfe1_gpio0_t,
mxfe2_gpio0_t,
mxfe3_gpio0_t} = gpio0_mode ? 4'b0001 : {4{gpio_t[64]}};
assign {mxfe0_gpio1_t,
mxfe1_gpio1_t,
mxfe2_gpio1_t,
mxfe3_gpio1_t} = {4{gpio_t[65]}};
assign {mxfe0_gpio1_t,
mxfe1_gpio1_t,
mxfe2_gpio1_t,
mxfe3_gpio1_t} = {4{gpio_t[65]}};
assign {mxfe0_gpio2_t,
mxfe1_gpio2_t,
mxfe2_gpio2_t,
mxfe3_gpio2_t} = {4{gpio_t[66]}};
assign {mxfe0_gpio2_t,
mxfe1_gpio2_t,
mxfe2_gpio2_t,
mxfe3_gpio2_t} = {4{gpio_t[66]}};
assign {mxfe0_gpio5_t,
mxfe1_gpio5_t,
mxfe2_gpio5_t,
mxfe3_gpio5_t} = {4{gpio_t[69]}};
assign {mxfe0_gpio5_t,
mxfe1_gpio5_t,
mxfe2_gpio5_t,
mxfe3_gpio5_t} = {4{gpio_t[69]}};
assign {mxfe0_gpio6_t,
mxfe1_gpio6_t,
mxfe2_gpio6_t,
mxfe3_gpio6_t} = {4{gpio_t[70]}};
assign {mxfe0_gpio6_t,
mxfe1_gpio6_t,
mxfe2_gpio6_t,
mxfe3_gpio6_t} = {4{gpio_t[70]}};
assign {mxfe0_gpio7_t,
mxfe1_gpio7_t,
mxfe2_gpio7_t,
mxfe3_gpio7_t} = {4{gpio_t[71]}};
assign {mxfe0_gpio7_t,
mxfe1_gpio7_t,
mxfe2_gpio7_t,
mxfe3_gpio7_t} = {4{gpio_t[71]}};
assign {mxfe0_gpio8_t,
mxfe1_gpio8_t,
mxfe2_gpio8_t,
mxfe3_gpio8_t} = {4{gpio_t[72]}};
assign {mxfe0_gpio8_t,
mxfe1_gpio8_t,
mxfe2_gpio8_t,
mxfe3_gpio8_t} = {4{gpio_t[72]}};
assign {mxfe0_gpio9_t,
mxfe1_gpio9_t,
mxfe2_gpio9_t,
mxfe3_gpio9_t} = {4{gpio_t[73]}};
assign {mxfe0_gpio9_t,
mxfe1_gpio9_t,
mxfe2_gpio9_t,
mxfe3_gpio9_t} = {4{gpio_t[73]}};
assign {mxfe0_gpio10_t,
mxfe1_gpio10_t,
mxfe2_gpio10_t,
mxfe3_gpio10_t} = {4{gpio_t[74]}};
assign {mxfe0_gpio10_t,
mxfe1_gpio10_t,
mxfe2_gpio10_t,
mxfe3_gpio10_t} = {4{gpio_t[74]}};
assign {mxfe0_syncin_1_n_t,
mxfe1_syncin_1_n_t,
mxfe2_syncin_1_n_t,
mxfe3_syncin_1_n_t} = {4{gpio_t[75]}};
assign {mxfe0_syncin_1_n_t,
mxfe1_syncin_1_n_t,
mxfe2_syncin_1_n_t,
mxfe3_syncin_1_n_t} = {4{gpio_t[75]}};
assign {mxfe0_syncin_1_p_t,
mxfe1_syncin_1_p_t,
mxfe2_syncin_1_p_t,
mxfe3_syncin_1_p_t} = {4{gpio_t[76]}};
assign {mxfe0_syncin_1_p_t,
mxfe1_syncin_1_p_t,
mxfe2_syncin_1_p_t,
mxfe3_syncin_1_p_t} = {4{gpio_t[76]}};
assign {mxfe0_syncout_1_n_t,
mxfe1_syncout_1_n_t,
mxfe2_syncout_1_n_t,
mxfe3_syncout_1_n_t} = {4{gpio_t[77]}};
assign {mxfe0_syncout_1_n_t,
mxfe1_syncout_1_n_t,
mxfe2_syncout_1_n_t,
mxfe3_syncout_1_n_t} = {4{gpio_t[77]}};
assign {mxfe0_syncout_1_p_t,
mxfe1_syncout_1_p_t,
mxfe2_syncout_1_p_t,
mxfe3_syncout_1_p_t} = {4{gpio_t[78]}};
assign {mxfe0_syncout_1_p_t,
mxfe1_syncout_1_p_t,
mxfe2_syncout_1_p_t,
mxfe3_syncout_1_p_t} = {4{gpio_t[78]}};
// Bidirectional buffer output values
assign {mxfe0_gpio0_o,
mxfe1_gpio0_o,
mxfe2_gpio0_o,
mxfe3_gpio0_o} = gpio0_mode ? {4{mxfe3_gpio0_i}} : {4{gpio_o[64]}};
// Bidirectional buffer output values
assign {mxfe0_gpio0_o,
mxfe1_gpio0_o,
mxfe2_gpio0_o,
mxfe3_gpio0_o} = gpio0_mode ? {4{mxfe3_gpio0_i}} : {4{gpio_o[64]}};
assign {mxfe0_gpio1_o,
mxfe1_gpio1_o,
mxfe2_gpio1_o,
mxfe3_gpio1_o} = {4{gpio_o[65]}};
assign {mxfe0_gpio1_o,
mxfe1_gpio1_o,
mxfe2_gpio1_o,
mxfe3_gpio1_o} = {4{gpio_o[65]}};
assign {mxfe0_gpio2_o,
mxfe1_gpio2_o,
mxfe2_gpio2_o,
mxfe3_gpio2_o} = {4{gpio_o[66]}};
assign {mxfe0_gpio2_o,
mxfe1_gpio2_o,
mxfe2_gpio2_o,
mxfe3_gpio2_o} = {4{gpio_o[66]}};
assign {mxfe0_gpio5_o,
mxfe1_gpio5_o,
mxfe2_gpio5_o,
mxfe3_gpio5_o} = {4{gpio_o[69]}};
assign {mxfe0_gpio5_o,
mxfe1_gpio5_o,
mxfe2_gpio5_o,
mxfe3_gpio5_o} = {4{gpio_o[69]}};
assign {mxfe0_gpio6_o,
mxfe1_gpio6_o,
mxfe2_gpio6_o,
mxfe3_gpio6_o} = {4{gpio_o[70]}};
assign {mxfe0_gpio6_o,
mxfe1_gpio6_o,
mxfe2_gpio6_o,
mxfe3_gpio6_o} = {4{gpio_o[70]}};
assign {mxfe0_gpio7_o,
mxfe1_gpio7_o,
mxfe2_gpio7_o,
mxfe3_gpio7_o} = {4{gpio_o[71]}};
assign {mxfe0_gpio7_o,
mxfe1_gpio7_o,
mxfe2_gpio7_o,
mxfe3_gpio7_o} = {4{gpio_o[71]}};
assign {mxfe0_gpio8_o,
mxfe1_gpio8_o,
mxfe2_gpio8_o,
mxfe3_gpio8_o} = {4{gpio_o[72]}};
assign {mxfe0_gpio8_o,
mxfe1_gpio8_o,
mxfe2_gpio8_o,
mxfe3_gpio8_o} = {4{gpio_o[72]}};
assign {mxfe0_gpio9_o,
mxfe1_gpio9_o,
mxfe2_gpio9_o,
mxfe3_gpio9_o} = {4{gpio_o[73]}};
assign {mxfe0_gpio9_o,
mxfe1_gpio9_o,
mxfe2_gpio9_o,
mxfe3_gpio9_o} = {4{gpio_o[73]}};
assign {mxfe0_gpio10_o,
mxfe1_gpio10_o,
mxfe2_gpio10_o,
mxfe3_gpio10_o} = {4{gpio_o[74]}};
assign {mxfe0_gpio10_o,
mxfe1_gpio10_o,
mxfe2_gpio10_o,
mxfe3_gpio10_o} = {4{gpio_o[74]}};
assign {mxfe0_syncin_1_n_o,
mxfe1_syncin_1_n_o,
mxfe2_syncin_1_n_o,
mxfe3_syncin_1_n_o} = {4{gpio_o[75]}};
assign {mxfe0_syncin_1_n_o,
mxfe1_syncin_1_n_o,
mxfe2_syncin_1_n_o,
mxfe3_syncin_1_n_o} = {4{gpio_o[75]}};
assign {mxfe0_syncin_1_p_o,
mxfe1_syncin_1_p_o,
mxfe2_syncin_1_p_o,
mxfe3_syncin_1_p_o} = {4{gpio_o[76]}};
assign {mxfe0_syncin_1_p_o,
mxfe1_syncin_1_p_o,
mxfe2_syncin_1_p_o,
mxfe3_syncin_1_p_o} = {4{gpio_o[76]}};
assign {mxfe0_syncout_1_n_o,
mxfe1_syncout_1_n_o,
mxfe2_syncout_1_n_o,
mxfe3_syncout_1_n_o} = {4{gpio_o[77]}};
assign {mxfe0_syncout_1_n_o,
mxfe1_syncout_1_n_o,
mxfe2_syncout_1_n_o,
mxfe3_syncout_1_n_o} = {4{gpio_o[77]}};
assign {mxfe0_syncout_1_p_o,
mxfe1_syncout_1_p_o,
mxfe2_syncout_1_p_o,
mxfe3_syncout_1_p_o} = {4{gpio_o[78]}};
assign {mxfe0_syncout_1_p_o,
mxfe1_syncout_1_p_o,
mxfe2_syncout_1_p_o,
mxfe3_syncout_1_p_o} = {4{gpio_o[78]}};
// GPIO inputs
assign gpio_i[64] = gpio0_mode ? gpio_o[64] : |{mxfe0_gpio0_i,
mxfe1_gpio0_i,
mxfe2_gpio0_i,
mxfe3_gpio0_i};
// GPIO inputs
assign gpio_i[65] = |{mxfe0_gpio1_i,
mxfe1_gpio1_i,
mxfe2_gpio1_i,
mxfe3_gpio1_i};
assign gpio_i[64] = gpio0_mode ? gpio_o[64] : |{mxfe0_gpio0_i,
mxfe1_gpio0_i,
mxfe2_gpio0_i,
mxfe3_gpio0_i};
assign gpio_i[66] = |{mxfe0_gpio2_i,
mxfe1_gpio2_i,
mxfe2_gpio2_i,
mxfe3_gpio2_i};
assign gpio_i[65] = |{mxfe0_gpio1_i,
mxfe1_gpio1_i,
mxfe2_gpio1_i,
mxfe3_gpio1_i};
assign gpio_i[69] = |{mxfe0_gpio5_i,
mxfe1_gpio5_i,
mxfe2_gpio5_i,
mxfe3_gpio5_i};
assign gpio_i[66] = |{mxfe0_gpio2_i,
mxfe1_gpio2_i,
mxfe2_gpio2_i,
mxfe3_gpio2_i};
assign gpio_i[70] = |{mxfe0_gpio6_i,
mxfe1_gpio6_i,
mxfe2_gpio6_i,
mxfe3_gpio6_i};
assign gpio_i[69] = |{mxfe0_gpio5_i,
mxfe1_gpio5_i,
mxfe2_gpio5_i,
mxfe3_gpio5_i};
assign gpio_i[71] = |{mxfe0_gpio7_i,
mxfe1_gpio7_i,
mxfe2_gpio7_i,
mxfe3_gpio7_i};
assign gpio_i[70] = |{mxfe0_gpio6_i,
mxfe1_gpio6_i,
mxfe2_gpio6_i,
mxfe3_gpio6_i};
assign gpio_i[72] = |{mxfe0_gpio8_i,
mxfe1_gpio8_i,
mxfe2_gpio8_i,
mxfe3_gpio8_i};
assign gpio_i[71] = |{mxfe0_gpio7_i,
mxfe1_gpio7_i,
mxfe2_gpio7_i,
mxfe3_gpio7_i};
assign gpio_i[73] = |{mxfe0_gpio9_i,
mxfe1_gpio9_i,
mxfe2_gpio9_i,
mxfe3_gpio9_i};
assign gpio_i[72] = |{mxfe0_gpio8_i,
mxfe1_gpio8_i,
mxfe2_gpio8_i,
mxfe3_gpio8_i};
assign gpio_i[74] = |{mxfe0_gpio10_i,
mxfe1_gpio10_i,
mxfe2_gpio10_i,
mxfe3_gpio10_i};
assign gpio_i[73] = |{mxfe0_gpio9_i,
mxfe1_gpio9_i,
mxfe2_gpio9_i,
mxfe3_gpio9_i};
assign gpio_i[75] = |{mxfe0_syncin_1_n_i,
mxfe1_syncin_1_n_i,
mxfe2_syncin_1_n_i,
mxfe3_syncin_1_n_i};
assign gpio_i[74] = |{mxfe0_gpio10_i,
mxfe1_gpio10_i,
mxfe2_gpio10_i,
mxfe3_gpio10_i};
assign gpio_i[76] = |{mxfe0_syncin_1_p_i,
mxfe1_syncin_1_p_i,
mxfe2_syncin_1_p_i,
mxfe3_syncin_1_p_i};
assign gpio_i[75] = |{mxfe0_syncin_1_n_i,
mxfe1_syncin_1_n_i,
mxfe2_syncin_1_n_i,
mxfe3_syncin_1_n_i};
assign gpio_i[77] = |{mxfe0_syncout_1_n_i,
mxfe1_syncout_1_n_i,
mxfe2_syncout_1_n_i,
mxfe3_syncout_1_n_i};
assign gpio_i[76] = |{mxfe0_syncin_1_p_i,
mxfe1_syncin_1_p_i,
mxfe2_syncin_1_p_i,
mxfe3_syncin_1_p_i};
assign gpio_i[77] = |{mxfe0_syncout_1_n_i,
mxfe1_syncout_1_n_i,
mxfe2_syncout_1_n_i,
mxfe3_syncout_1_n_i};
assign gpio_i[78] = |{mxfe0_syncout_1_p_i,
mxfe1_syncout_1_p_i,
mxfe2_syncout_1_p_i,
mxfe3_syncout_1_p_i};
assign gpio_i[78] = |{mxfe0_syncout_1_p_i,
mxfe1_syncout_1_p_i,
mxfe2_syncout_1_p_i,
mxfe3_syncout_1_p_i};
//loopback unused gpios
assign gpio_i[68:67] = gpio_o[68:67];

38
projects/ad_quadmxfe1_ebz/vcu118/system_top.v
View File

@ -78,7 +78,7 @@ module system_top (
input vadj_1v8_pgood,
// FMCp IOs
//
output [3:0] adf4371_cs,
output adf4371_sclk,
inout adf4371_sdio,
@ -154,7 +154,6 @@ module system_top (
output [3:0] mxfe_tx_en0,
output [3:0] mxfe_tx_en1,
// PMOD1 for calibration board
output pmod1_adc_sync_n,
output pmod1_adc_sdi,
@ -165,7 +164,6 @@ module system_top (
output pmod1_5045_v1,
output pmod1_ctrl_ind,
output pmod1_ctrl_rx_combined
);
// internal signals
@ -251,8 +249,7 @@ module system_top (
BUFG i_rx_device_clk (
.I (fpga_clk_m2c_1),
.O (rx_device_clk)
);
.O (rx_device_clk));
IBUFDS i_ibufds_tx_device_clk (
.I (fpga_clk_m2c_p[2]),
@ -261,8 +258,7 @@ module system_top (
BUFG i_tx_device_clk (
.I (fpga_clk_m2c_2),
.O (tx_device_clk)
);
.O (tx_device_clk));
// spi
@ -292,7 +288,9 @@ module system_top (
assign spi_3_miso = ~pmod1_adc_sync_n ? pmod1_adc_sdo : 1'b0;
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_hmc (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi_hmc (
.spi_csn (spi_2_csn[4]),
.spi_clk (spi_2_clk),
.spi_mosi (spi_2_mosi),
@ -300,7 +298,9 @@ module system_top (
.spi_sdio (hmc7043_sdata),
.spi_dir ());
ad_3w_spi #(.NUM_OF_SLAVES(1)) i_spi_4371 (
ad_3w_spi #(
.NUM_OF_SLAVES(1)
) i_spi_4371 (
.spi_csn (&spi_2_csn[3:0]),
.spi_clk (spi_2_clk),
.spi_mosi (spi_2_mosi),
@ -310,12 +310,13 @@ module system_top (
// gpios
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf (
.dio_t (gpio_t[32:32]),
.dio_i (gpio_o[32:32]),
.dio_o (gpio_i[32:32]),
.dio_p ({hmc7043_gpio // 32
}));
.dio_p ({hmc7043_gpio})); // 32
assign hmc7043_reset = gpio_o[33];
assign adrf5020_ctrl = gpio_o[34];
@ -328,7 +329,9 @@ module system_top (
assign dac_fifo_bypass = gpio_o[61];
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(17)
) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
@ -396,8 +399,7 @@ module system_top (
.gpio_t(gpio_t[127:64]),
.gpio_i(gpio_i[127:64]),
.gpio_o(gpio_o[127:64])
);
.gpio_o(gpio_o[127:64]));
assign pmod1_5045_v2 = gpio_o[120];
assign pmod1_5045_v1 = gpio_o[121];
@ -556,12 +558,8 @@ module system_top (
.gpio3_i (gpio_i[127:96]),
.gpio3_o (gpio_o[127:96]),
.gpio3_t (gpio_t[127:96]),
.ext_sync (sysref)
);
.ext_sync (sysref));
assign link1_rx_syncout = 4'b1111;
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/adaq7980_sdz/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -90,7 +89,8 @@ module system_top (
inout [ 7:0] adaq7980_gpio,
inout adaq7980_rbuf_pd,
inout adaq7980_ref_pd);
inout adaq7980_ref_pd
);
// internal signals
@ -198,6 +198,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

27
projects/adaq8092_fmc/zed/system_top.v
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@ -83,7 +83,7 @@ module system_top (
input otg_vbusoc,
// adc interface
// adc interface
input adc_clk_in_n,
input adc_clk_in_p,
@ -97,39 +97,40 @@ module system_top (
output adc_pd1,
output adc_pd2,
output en_1p8,
// spi interface
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 2:0] spi0_csn;
wire spi0_clk;
wire spi0_mosi;
wire spi0_miso;
wire [ 2:0] spi1_csn;
wire spi1_clk;
wire spi1_mosi;
wire spi1_miso;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
assign spi_csn = spi0_csn[0];
assign spi_clk = spi0_clk;
assign spi_mosi = spi0_mosi;
@ -139,7 +140,7 @@ module system_top (
assign adc_pd1 = gpio_o[33];
assign adc_pd2 = gpio_o[34];
assign en_1p8 = gpio_o[35];
ad_iobuf #(
.DATA_WIDTH(15)
) iobuf_gpio_bd (
@ -147,10 +148,10 @@ module system_top (
.dio_o (gpio_i[14:0]),
.dio_t (gpio_t[14:0]),
.dio_p (gpio_bd[14:0]));
assign gpio_i[63:33] = gpio_o[63:33];
assign gpio_i[31:15] = gpio_o[31:15];
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
@ -158,7 +159,7 @@ module system_top (
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
@ -238,5 +239,5 @@ module system_top (
.spi1_sdo_i (spi1_mosi),
.spi1_sdo_o (spi1_mosi),
.spdif (spdif));
endmodule

6
projects/adrv9001/a10soc/system_top.v
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@ -365,10 +365,6 @@ module system_top (
dgpio_3,
dgpio_2,
dgpio_1,
dgpio_0})
);
dgpio_0}));
endmodule
// ***************************************************************************
// ***************************************************************************

31
projects/adrv9001/zc706/system_top.v
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@ -176,7 +176,9 @@ module system_top (
assign platform_status = vadj_err;
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t (vadj_err ? {16{1'b1}} : gpio_t[47:32]),
.dio_i ({gpio_o[47:32]}),
.dio_o ({gpio_i[47:32]}),
@ -202,7 +204,9 @@ module system_top (
assign gpio_tx1_enable_in = gpio_o[50];
assign gpio_tx2_enable_in = gpio_o[51];
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -215,7 +219,7 @@ module system_top (
assign tdd_sync_loc = gpio_o[56];
// tdd_sync_loc - local sync signal from a GPIO or other source
// tdd_sync - external sync
// tdd_sync - external sync
assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
@ -327,20 +331,15 @@ module system_top (
.gpio_tx2_enable_in (gpio_tx2_enable_in),
.tdd_sync (tdd_sync_i),
.tdd_sync_cntr (tdd_sync_cntr)
.tdd_sync_cntr (tdd_sync_cntr));
);
assign spi_clk = vadj_err ? 1'bz : spi_clk_s;
assign spi_en = vadj_err ? 1'bz : spi_en_s;
assign spi_dio = vadj_err ? 1'bz : spi_dio_s;
assign spi_clk = vadj_err ? 1'bz : spi_clk_s;
assign spi_en = vadj_err ? 1'bz : spi_en_s;
assign spi_dio = vadj_err ? 1'bz : spi_dio_s;
assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s;
assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s;
assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s;
assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s;
assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s;
assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s;
assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s;
assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s;
endmodule
// ***************************************************************************
// ***************************************************************************

15
projects/adrv9001/zcu102/system_top.v
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@ -128,8 +128,8 @@ module system_top (
//debug hdr
output [9:0] proto_hdr
);
// internal registers
reg [ 2:0] mcs_sync_m = 'd0;
reg dev_mcs_fpga_in = 1'b0;
@ -180,7 +180,9 @@ module system_top (
assign platform_status = vadj_err;
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t ({gpio_t[47:32]}),
.dio_i ({gpio_o[47:32]}),
.dio_o ({gpio_i[47:32]}),
@ -220,7 +222,7 @@ module system_top (
assign tdd_sync_loc = gpio_o[56];
// tdd_sync_loc - local sync signal from a GPIO or other source
// tdd_sync - external sync
// tdd_sync - external sync
assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
@ -300,13 +302,8 @@ module system_top (
.adc1_div_clk (proto_hdr[0]),
.adc2_div_clk (proto_hdr[1]),
.dac1_div_clk (proto_hdr[2]),
.dac2_div_clk (proto_hdr[3])
);
.dac2_div_clk (proto_hdr[3]));
assign proto_hdr[9:4] = {'b0};
endmodule
// ***************************************************************************
// ***************************************************************************

36
projects/adrv9001/zed/system_top.v
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@ -191,7 +191,7 @@ module system_top (
// instantiations
// multi-ssi synchronization
//
assign mssi_sync = gpio_o[54];
assign platform_status = vadj_err;
@ -204,7 +204,9 @@ module system_top (
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t (vadj_err ? {16{1'b1}} : gpio_t[47:32]),
.dio_i ({gpio_o[47:32]}),
.dio_o ({gpio_i[47:32]}),
@ -237,17 +239,21 @@ module system_top (
assign tdd_sync_loc = gpio_o[56];
// tdd_sync_loc - local sync signal from a GPIO or other source
// tdd_sync - external sync
// tdd_sync - external sync
assign tdd_sync_i = tdd_sync_cntr ? tdd_sync_loc : tdd_sync;
assign tdd_sync = tdd_sync_cntr ? tdd_sync_loc : 1'bz;
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_scl (
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_sda (
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
@ -374,19 +380,15 @@ module system_top (
.spi1_csn_i (1'b1),
.spi1_sdi_i (1'b0),
.spi1_sdo_i (1'b0),
.spi1_sdo_o ()
);
.spi1_sdo_o ());
assign spi_clk = vadj_err ? 1'bz : spi_clk_s;
assign spi_en = vadj_err ? 1'bz : spi_en_s;
assign spi_dio = vadj_err ? 1'bz : spi_dio_s;
assign spi_clk = vadj_err ? 1'bz : spi_clk_s;
assign spi_en = vadj_err ? 1'bz : spi_en_s;
assign spi_dio = vadj_err ? 1'bz : spi_dio_s;
assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s;
assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s;
assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s;
assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s;
assign rx1_enable = vadj_err ? 1'bz : rx1_enable_s;
assign rx2_enable = vadj_err ? 1'bz : rx2_enable_s;
assign tx1_enable = vadj_err ? 1'bz : tx1_enable_s;
assign tx2_enable = vadj_err ? 1'bz : tx2_enable_s;
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adrv9009/a10gx/system_top.v
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@ -116,7 +116,8 @@ module system_top (
output spi_csn_adrv9009,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -240,6 +241,3 @@ module system_top (
.sys_flash_tcm_chipselect_n_out (flash_cen[0]));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adrv9009/a10soc/system_top.v
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@ -156,7 +156,8 @@ module system_top (
output spi_csn_adrv9009,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -324,6 +325,3 @@ module system_top (
.rx_sysref_export (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************

13
projects/adrv9009/s10soc/system_top.v
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@ -148,7 +148,6 @@ module system_top (
output spi_clk,
output spi_mosi,
input spi_miso
);
// internal signals
@ -198,9 +197,9 @@ module system_top (
system_bd i_system_bd (
.sys_clk_clk ( sys_clk ),
.sys_rst_reset_n ( sys_resetn_s ),
.h2f_reset_reset ( h2f_reset_s ),
.rst_ninit_done_ninit_done ( ninit_done_s ),
.sys_rst_reset_n ( sys_resetn_s ),
.h2f_reset_reset ( h2f_reset_s ),
.rst_ninit_done_ninit_done ( ninit_done_s ),
.sys_gpio_bd_in_port ( gpio_i[31: 0] ),
.sys_gpio_bd_out_port ( gpio_o[31: 0] ),
.sys_gpio_in_export ( gpio_i[63:32] ),
@ -288,10 +287,6 @@ module system_top (
.rx_os_sysref_export ( sysref ),
.rx_ref_clk_clk ( ref_clk1 ),
.rx_sync_export ( rx_sync ),
.rx_sysref_export ( sysref )
);
.rx_sysref_export ( sysref ));
endmodule
// ***************************************************************************
// ***************************************************************************

14
projects/adrv9009/zc706/system_top.v
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@ -225,7 +225,8 @@ module system_top (
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n);
output ddr3_we_n
);
// internal signals
@ -295,7 +296,9 @@ module system_top (
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(28)
) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
@ -328,7 +331,9 @@ module system_top (
adrv9009_gpio_16, // 33
adrv9009_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -434,6 +439,3 @@ module system_top (
.ref_clk (ref_clk1_bufg));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/adrv9009/zcu102/system_top.v
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@ -99,7 +99,8 @@ module system_top (
inout adrv9009_gpio_13,
inout adrv9009_gpio_17,
inout adrv9009_gpio_16,
inout adrv9009_gpio_18);
inout adrv9009_gpio_18
);
// internal signals
@ -170,7 +171,9 @@ module system_top (
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(28)
) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
@ -253,6 +256,3 @@ module system_top (
.ref_clk (ref_clk1_bufg));
endmodule
// ***************************************************************************
// ***************************************************************************

38
projects/adrv9009zu11eg/adrv2crr_fmc/system_top.v
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@ -272,12 +272,12 @@ module system_top (
assign gpio_2_exp_n = spi_3_to_8_csn[5];
adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
assign tx_sync = tx_sync_a & tx_sync_b;
@ -285,7 +285,9 @@ module system_top (
assign gpio_i[31:28] = gpio_o[31:28];
assign gpio_i[21:20] = gpio_o[21:20];
ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(61)
) i_iobuf (
.dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[92:32]}),
@ -352,7 +354,9 @@ module system_top (
adrv9009_gpio_01_a, // 33
adrv9009_gpio_00_a})); // 32
ad_iobuf #(.DATA_WIDTH(6)) i_carrier_iobuf_0 (
ad_iobuf #(
.DATA_WIDTH(6)
) i_carrier_iobuf_0 (
.dio_t ({gpio_t[27:22]}),
.dio_i ({gpio_o[27:22]}),
.dio_o ({gpio_i[27:22]}),
@ -364,7 +368,9 @@ module system_top (
hmc7044_car_reset, // 23
resetb_ad9545})); // 22
ad_iobuf #(.DATA_WIDTH(20)) i_carrier_iobuf_1 (
ad_iobuf #(
.DATA_WIDTH(20)
) i_carrier_iobuf_1 (
.dio_t ({gpio_t[19:0]}),
.dio_i ({gpio_o[19:0]}),
.dio_o ({gpio_i[19:0]}),
@ -420,8 +426,8 @@ module system_top (
.O (core_clk_a_ds));
BUFG i_clk_bufg_1 (
.I (core_clk_a_ds),
.O (core_clk_a));
.I (core_clk_a_ds),
.O (core_clk_a));
IBUFDS i_rx_clk_ibuf_2 (
.I (core_clk_b_p),
@ -429,8 +435,8 @@ module system_top (
.O (core_clk_b_ds));
BUFG i_clk_bufg_2 (
.I (core_clk_b_ds),
.O (core_clk_b));
.I (core_clk_b_ds),
.O (core_clk_b));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_a_p),
@ -536,10 +542,6 @@ module system_top (
.spi0_csn(spi_csn),
.spi0_miso(spi0_miso),
.spi0_mosi(spi_mosi),
.spi0_sclk(spi_clk)
);
.spi0_sclk(spi_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

58
projects/adrv9009zu11eg/adrv2crr_fmcomms8/system_top.v
View File

@ -388,20 +388,20 @@ module system_top (
assign spi_csn_fmc_hmc7044 = spi_fmcomms8_3_to_8_csn[2];
adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
adrv9009zu11eg_spi fmcomms8_spi (
.spi_csn(spi_fmcomms8_3_to_8_csn),
.spi_clk(spi_fmc_clk),
.spi_mosi(fmcomms8_spi_mosi),
.spi_miso_i(spi_fmc_miso),
.spi_miso_o(fmcomms8_spi1_miso),
.spi_sdio(spi_fmc_sdio));
.spi_csn(spi_fmcomms8_3_to_8_csn),
.spi_clk(spi_fmc_clk),
.spi_mosi(fmcomms8_spi_mosi),
.spi_miso_i(spi_fmc_miso),
.spi_miso_o(fmcomms8_spi1_miso),
.spi_sdio(spi_fmc_sdio));
assign tx_sync = tx_sync_a & tx_sync_b & tx_sync_c & tx_sync_d;
@ -411,7 +411,9 @@ module system_top (
assign fmcomms8_gpio_i[63:36] = fmcomms8_gpio_o[63:36];
ad_iobuf #(.DATA_WIDTH(36)) i_fmcomms8_iobuf (
ad_iobuf #(
.DATA_WIDTH(36)
) i_fmcomms8_iobuf (
.dio_t ({fmcomms8_gpio_t[35:0]}),
.dio_i ({fmcomms8_gpio_o[35:0]}),
.dio_o ({fmcomms8_gpio_i[35:0]}),
@ -453,7 +455,9 @@ module system_top (
adrv9009_gpio_01_c, // 01
adrv9009_gpio_00_c})); // 00
ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(61)
) i_iobuf (
.dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[92:32]}),
@ -520,7 +524,9 @@ module system_top (
adrv9009_gpio_01_a, // 33
adrv9009_gpio_00_a})); // 32
ad_iobuf #(.DATA_WIDTH(6)) i_carrier_iobuf_0 (
ad_iobuf #(
.DATA_WIDTH(6)
) i_carrier_iobuf_0 (
.dio_t ({gpio_t[27:22]}),
.dio_i ({gpio_o[27:22]}),
.dio_o ({gpio_i[27:22]}),
@ -532,7 +538,9 @@ module system_top (
hmc7044_car_reset, // 23
resetb_ad9545})); // 22
ad_iobuf #(.DATA_WIDTH(20)) i_carrier_iobuf_1 (
ad_iobuf #(
.DATA_WIDTH(20)
) i_carrier_iobuf_1 (
.dio_t ({gpio_t[19:0]}),
.dio_i ({gpio_o[19:0]}),
.dio_o ({gpio_i[19:0]}),
@ -613,8 +621,7 @@ module system_top (
BUFG i_clk_bufg_1 (
.I (core_clk_a_ds),
.O (core_clk_a)
);
.O (core_clk_a));
IBUFDS i_rx_clk_ibuf_2 (
.I (core_clk_b_p),
@ -623,8 +630,7 @@ module system_top (
BUFG i_clk_bufg_2 (
.I (core_clk_b_ds),
.O (core_clk_b)
);
.O (core_clk_b));
IBUFDS i_rx_clk_ibuf_3 (
.I (core_clk_c_p),
@ -633,8 +639,7 @@ module system_top (
BUFG i_clk_bufg_3 (
.I (core_clk_c_ds),
.O (core_clk_c)
);
.O (core_clk_c));
IBUFDS i_rx_clk_ibufg_4 (
.I (core_clk_d_p),
@ -643,8 +648,7 @@ module system_top (
BUFG i_clk_bufg_4 (
.I (core_clk_d_ds),
.O (core_clk_d)
);
.O (core_clk_d));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_a_p),
@ -829,10 +833,6 @@ module system_top (
.spi1_csn (fmcomms8_spi_csn),
.spi1_miso(fmcomms8_spi1_miso),
.spi1_mosi(fmcomms8_spi_mosi),
.spi1_sclk(spi_fmc_clk)
);
.spi1_sclk(spi_fmc_clk));
endmodule
// ***************************************************************************
// ***************************************************************************

42
projects/adrv9009zu11eg/adrv2crr_fmcxmwbr1/system_top.v
View File

@ -337,12 +337,12 @@ module system_top (
assign spi2_cs0 = spi2_csn[0];
adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
assign tx_sync = tx_sync_a & tx_sync_b;
@ -352,7 +352,9 @@ module system_top (
assign fmcxmwbr1_gpio_i[63:30] = fmcxmwbr1_gpio_o[63:30];
ad_iobuf #(.DATA_WIDTH(30)) i_fmcxmwbr1_iobuf (
ad_iobuf #(
.DATA_WIDTH(30)
) i_fmcxmwbr1_iobuf (
.dio_t ({fmcxmwbr1_gpio_t[29:0]}),
.dio_i ({fmcxmwbr1_gpio_o[29:0]}),
.dio_o ({fmcxmwbr1_gpio_i[29:0]}),
@ -388,7 +390,9 @@ module system_top (
gpio1, // 01
gpio0})); // 00
ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(61)
) i_iobuf (
.dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[92:32]}),
@ -455,7 +459,9 @@ module system_top (
adrv9009_gpio_01_a, // 33
adrv9009_gpio_00_a})); // 32
ad_iobuf #(.DATA_WIDTH(6)) i_carrier_iobuf_0 (
ad_iobuf #(
.DATA_WIDTH(6)
) i_carrier_iobuf_0 (
.dio_t ({gpio_t[27:22]}),
.dio_i ({gpio_o[27:22]}),
.dio_o ({gpio_i[27:22]}),
@ -467,7 +473,9 @@ module system_top (
hmc7044_car_reset, // 23
resetb_ad9545})); // 22
ad_iobuf #(.DATA_WIDTH(20)) i_carrier_iobuf_1 (
ad_iobuf #(
.DATA_WIDTH(20)
) i_carrier_iobuf_1 (
.dio_t ({gpio_t[19:0]}),
.dio_i ({gpio_o[19:0]}),
.dio_o ({gpio_i[19:0]}),
@ -523,8 +531,8 @@ module system_top (
.O (core_clk_a_ds));
BUFG i_rx_clk_ibufg_1 (
.I (core_clk_a_ds),
.O (core_clk_a));
.I (core_clk_a_ds),
.O (core_clk_a));
IBUFDS i_rx_clk_ibuf_2 (
.I (core_clk_b_p),
@ -532,8 +540,8 @@ module system_top (
.O (core_clk_b_ds));
BUFG i_rx_clk_ibufg_2 (
.I (core_clk_b_ds),
.O (core_clk_b));
.I (core_clk_b_ds),
.O (core_clk_b));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_a_p),
@ -663,10 +671,6 @@ module system_top (
.fmcxmwbr1_gpio0_i(fmcxmwbr1_gpio_i[31:0]),
.fmcxmwbr1_gpio1_o(fmcxmwbr1_gpio_o[63:32]),
.fmcxmwbr1_gpio1_t(fmcxmwbr1_gpio_t[63:32]),
.fmcxmwbr1_gpio1_i(fmcxmwbr1_gpio_i[63:32])
);
.fmcxmwbr1_gpio1_i(fmcxmwbr1_gpio_i[63:32]));
endmodule
// ***************************************************************************
// ***************************************************************************

42
projects/adrv9009zu11eg/adrv2crr_xmicrowave/system_top.v
View File

@ -352,12 +352,12 @@ module system_top (
assign spi2_cs7 = spi2_csn[7];
adrv9009zu11eg_spi i_spi (
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
.spi_csn(spi_3_to_8_csn),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso_i(spi_miso_s),
.spi_miso_o(spi0_miso),
.spi_sdio(spi_sdio));
assign tx_sync = tx_sync_a & tx_sync_b;
@ -367,7 +367,9 @@ module system_top (
assign xmicrowave_gpio_i[63:16] = xmicrowave_gpio_o[63:16];
ad_iobuf #(.DATA_WIDTH(16)) i_xmicrowave_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_xmicrowave_iobuf (
.dio_t ({xmicrowave_gpio_t[15:0]}),
.dio_i ({xmicrowave_gpio_o[15:0]}),
.dio_o ({xmicrowave_gpio_i[15:0]}),
@ -389,7 +391,9 @@ module system_top (
gpio1, // 01
gpio0})); // 00
ad_iobuf #(.DATA_WIDTH(61)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(61)
) i_iobuf (
.dio_t ({gpio_t[92:32]}),
.dio_i ({gpio_o[92:32]}),
.dio_o ({gpio_i[92:32]}),
@ -456,7 +460,9 @@ module system_top (
adrv9009_gpio_01_a, // 33
adrv9009_gpio_00_a})); // 32
ad_iobuf #(.DATA_WIDTH(6)) i_carrier_iobuf_0 (
ad_iobuf #(
.DATA_WIDTH(6)
) i_carrier_iobuf_0 (
.dio_t ({gpio_t[27:22]}),
.dio_i ({gpio_o[27:22]}),
.dio_o ({gpio_i[27:22]}),
@ -468,7 +474,9 @@ module system_top (
hmc7044_car_reset, // 23
resetb_ad9545})); // 22
ad_iobuf #(.DATA_WIDTH(20)) i_carrier_iobuf_1 (
ad_iobuf #(
.DATA_WIDTH(20)
) i_carrier_iobuf_1 (
.dio_t ({gpio_t[19:0]}),
.dio_i ({gpio_o[19:0]}),
.dio_o ({gpio_i[19:0]}),
@ -524,8 +532,8 @@ module system_top (
.O (core_clk_a_ds));
BUFG i_rx_clk_ibufg_1 (
.I (core_clk_a_ds),
.O (core_clk_a));
.I (core_clk_a_ds),
.O (core_clk_a));
IBUFDS i_rx_clk_ibuf_2 (
.I (core_clk_b_p),
@ -533,8 +541,8 @@ module system_top (
.O (core_clk_b_ds));
BUFG i_rx_clk_ibufg_2 (
.I (core_clk_b_ds),
.O (core_clk_b));
.I (core_clk_b_ds),
.O (core_clk_b));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_a_p),
@ -664,10 +672,6 @@ module system_top (
.xmicrowave_gpio0_i(xmicrowave_gpio_i[31:0]),
.xmicrowave_gpio1_o(xmicrowave_gpio_o[63:32]),
.xmicrowave_gpio1_t(xmicrowave_gpio_t[63:32]),
.xmicrowave_gpio1_i(xmicrowave_gpio_i[63:32])
);
.xmicrowave_gpio1_i(xmicrowave_gpio_i[63:32]));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/adrv9009zu11eg/common/adrv9009zu11eg_spi.v
View File

@ -43,7 +43,8 @@ module adrv9009zu11eg_spi (
input spi_miso_i,
output spi_miso_o,
inout spi_sdio);
inout spi_sdio
);
// internal registers
@ -86,7 +87,9 @@ module adrv9009zu11eg_spi (
// io buffer
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_sdio (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_sdio (
.dio_t (spi_enable_s),
.dio_i (spi_mosi),
.dio_o (spi_miso_io),
@ -95,6 +98,3 @@ module adrv9009zu11eg_spi (
assign spi_miso_o = spi_enable_s ? spi_miso_io : spi_miso_i;
endmodule
// ***************************************************************************
// ***************************************************************************

14
projects/adrv9361z7035/ccbob_cmos/system_top.v
View File

@ -98,7 +98,8 @@ module system_top (
output [ 3:0] gt_tx_p,
output [ 3:0] gt_tx_n,
input [ 3:0] gt_rx_p,
input [ 3:0] gt_rx_n);
input [ 3:0] gt_rx_n
);
// internal signals
@ -130,7 +131,9 @@ module system_top (
assign gpio_i[31:20] = gpio_o[31:20];
ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(20)
) i_iobuf_bd (
.dio_t (gpio_t[19:0]),
.dio_i (gpio_o[19:0]),
.dio_o (gpio_i[19:0]),
@ -141,7 +144,9 @@ module system_top (
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
@ -229,6 +234,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

14
projects/adrv9361z7035/ccbob_lvds/system_top.v
View File

@ -103,7 +103,8 @@ module system_top (
output [ 3:0] gt_tx_p,
output [ 3:0] gt_tx_n,
input [ 3:0] gt_rx_p,
input [ 3:0] gt_rx_n);
input [ 3:0] gt_rx_n
);
// internal signals
@ -134,7 +135,9 @@ module system_top (
assign gpio_i[31:20] = gpio_o[31:20];
ad_iobuf #(.DATA_WIDTH(20)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(20)
) i_iobuf_bd (
.dio_t (gpio_t[19:0]),
.dio_i (gpio_o[19:0]),
.dio_o (gpio_i[19:0]),
@ -145,7 +148,9 @@ module system_top (
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
@ -239,6 +244,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

26
projects/adrv9361z7035/ccfmc_lvds/system_top.v
View File

@ -153,7 +153,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -219,7 +220,9 @@ module system_top (
.O (gt_ref_clk_1),
.ODIV2 ());
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_tdd_sync (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_tdd_sync (
.dio_t (tdd_sync_t),
.dio_i (tdd_sync_o),
.dio_o (tdd_sync_i),
@ -229,7 +232,9 @@ module system_top (
assign gpio_i[31:21] = gpio_o[31:21];
ad_iobuf #(.DATA_WIDTH(21)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(21)
) i_iobuf_bd (
.dio_t (gpio_t[20:0]),
.dio_i (gpio_o[20:0]),
.dio_o (gpio_i[20:0]),
@ -241,7 +246,9 @@ module system_top (
// rf & ad9517 gpio - 60:56
ad_iobuf #(.DATA_WIDTH(5)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(5)
) i_iobuf (
.dio_t (gpio_t[60:56]),
.dio_i (gpio_o[60:56]),
.dio_o (gpio_i[60:56]),
@ -257,7 +264,9 @@ module system_top (
// rf & clock-select gpio - 52:51
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_rf_1 (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_rf_1 (
.dio_t (gpio_t[52:51]),
.dio_i (gpio_o[52:51]),
.dio_o (gpio_i[52:51]),
@ -270,7 +279,9 @@ module system_top (
// ad9361 gpio - 46:32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_ad9361 (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_ad9361 (
.dio_t (gpio_t[46:32]),
.dio_i (gpio_o[46:32]),
.dio_o (gpio_i[46:32]),
@ -395,6 +406,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

46
projects/adrv9361z7035/ccpackrf_lvds/system_top.v
View File

@ -144,7 +144,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -165,7 +166,9 @@ module system_top (
// rtc int gpio - 26
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_rtc (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_rtc (
.dio_t (gpio_t[26]),
.dio_i (gpio_o[26]),
.dio_o (gpio_i[26]),
@ -173,7 +176,9 @@ module system_top (
// misc gpio part 2 - 25:24
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_misc_2 (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_misc_2 (
.dio_t (gpio_t[25:24]),
.dio_i (gpio_o[25:24]),
.dio_o (gpio_i[25:24]),
@ -182,7 +187,9 @@ module system_top (
// misc gpio - 23:20
ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc (
ad_iobuf #(
.DATA_WIDTH(4)
) i_iobuf_misc (
.dio_t (gpio_t[23:20]),
.dio_i (gpio_o[23:20]),
.dio_o (gpio_i[23:20]),
@ -195,7 +202,9 @@ module system_top (
assign gpio_i[19] = gpio_o[19];
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf_adp5061 (
.dio_t (gpio_t[18:16]),
.dio_i (gpio_o[18:16]),
.dio_o (gpio_i[18:16]),
@ -212,7 +221,9 @@ module system_top (
assign imu_rstn = gpio_o[9];
assign gpio_i[11:9] = gpio_o[11:9];
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_imu_sync (
.dio_t (gpio_t[8]),
.dio_i (gpio_o[8]),
.dio_o (gpio_i[8]),
@ -241,7 +252,9 @@ module system_top (
// tsw-part-2 gpio - 59:57
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_tsw_2 (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf_tsw_2 (
.dio_t (gpio_t[59:57]),
.dio_i (gpio_o[59:57]),
.dio_o (gpio_i[59:57]),
@ -251,7 +264,9 @@ module system_top (
// rf gpio - 56
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_rf_2 (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_rf_2 (
.dio_t (gpio_t[56]),
.dio_i (gpio_o[56]),
.dio_o (gpio_i[56]),
@ -263,7 +278,9 @@ module system_top (
// rf & clock-select gpio - 52:51
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_rf_1 (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_rf_1 (
.dio_t (gpio_t[52:51]),
.dio_i (gpio_o[52:51]),
.dio_o (gpio_i[52:51]),
@ -272,7 +289,9 @@ module system_top (
// tact-scroll-wheel gpio - 50:47
ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_tsw_1 (
ad_iobuf #(
.DATA_WIDTH(4)
) i_iobuf_tsw_1 (
.dio_t (gpio_t[50:47]),
.dio_i (gpio_o[50:47]),
.dio_o (gpio_i[50:47]),
@ -283,7 +302,9 @@ module system_top (
// ad9361 gpio - 46:32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_ad9361 (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_ad9361 (
.dio_t (gpio_t[46:32]),
.dio_i (gpio_o[46:32]),
.dio_o (gpio_i[46:32]),
@ -381,6 +402,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

15
projects/adrv9364z7020/ccbob_cmos/system_top.v
View File

@ -91,8 +91,8 @@ module system_top (
input spi_miso,
output [27:0] gp_out,
input [27:0] gp_in);
input [27:0] gp_in
);
// internal signals
@ -114,7 +114,9 @@ module system_top (
assign gpio_i[31:11] = gpio_o[31:11];
ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(11)
) i_iobuf_bd (
.dio_t (gpio_t[10:0]),
.dio_i (gpio_o[10:0]),
.dio_o (gpio_i[10:0]),
@ -125,7 +127,9 @@ module system_top (
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
@ -202,6 +206,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

15
projects/adrv9364z7020/ccbob_lvds/system_top.v
View File

@ -96,8 +96,8 @@ module system_top (
input spi_miso,
output [27:0] gp_out,
input [27:0] gp_in);
input [27:0] gp_in
);
// internal signals
@ -118,7 +118,9 @@ module system_top (
assign gpio_i[31:11] = gpio_o[31:11];
ad_iobuf #(.DATA_WIDTH(11)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(11)
) i_iobuf_bd (
.dio_t (gpio_t[10:0]),
.dio_i (gpio_o[10:0]),
.dio_o (gpio_i[10:0]),
@ -129,7 +131,9 @@ module system_top (
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[50:47] = gpio_o[50:47];
ad_iobuf #(.DATA_WIDTH(16)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(16)
) i_iobuf (
.dio_t ({gpio_t[51], gpio_t[46:32]}),
.dio_i ({gpio_o[51], gpio_o[46:32]}),
.dio_o ({gpio_i[51], gpio_i[46:32]}),
@ -212,6 +216,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

42
projects/adrv9364z7020/ccpackrf_lvds/system_top.v
View File

@ -142,7 +142,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -163,7 +164,9 @@ module system_top (
// rtc int gpio - 26
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_rtc (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_rtc (
.dio_t (gpio_t[26]),
.dio_i (gpio_o[26]),
.dio_o (gpio_i[26]),
@ -175,7 +178,9 @@ module system_top (
// misc gpio - 23:20
ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_misc (
ad_iobuf #(
.DATA_WIDTH(4)
) i_iobuf_misc (
.dio_t (gpio_t[23:20]),
.dio_i (gpio_o[23:20]),
.dio_o (gpio_i[23:20]),
@ -188,7 +193,9 @@ module system_top (
assign gpio_i[19] = gpio_o[19];
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_adp5061 (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf_adp5061 (
.dio_t (gpio_t[18:16]),
.dio_i (gpio_o[18:16]),
.dio_o (gpio_i[18:16]),
@ -205,7 +212,9 @@ module system_top (
assign imu_rstn = gpio_o[9];
assign gpio_i[11:9] = gpio_o[11:9];
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_imu_sync (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_imu_sync (
.dio_t (gpio_t[8]),
.dio_i (gpio_o[8]),
.dio_o (gpio_i[8]),
@ -234,7 +243,9 @@ module system_top (
// tsw-part-2 gpio - 59:57
ad_iobuf #(.DATA_WIDTH(3)) i_iobuf_tsw_2 (
ad_iobuf #(
.DATA_WIDTH(3)
) i_iobuf_tsw_2 (
.dio_t (gpio_t[59:57]),
.dio_i (gpio_o[59:57]),
.dio_o (gpio_i[59:57]),
@ -244,7 +255,9 @@ module system_top (
// rf gpio - 56
ad_iobuf #(.DATA_WIDTH(1)) i_iobuf_rf_2 (
ad_iobuf #(
.DATA_WIDTH(1)
) i_iobuf_rf_2 (
.dio_t (gpio_t[56]),
.dio_i (gpio_o[56]),
.dio_o (gpio_i[56]),
@ -256,7 +269,9 @@ module system_top (
// rf & clock-select gpio - 52:51
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_rf_1 (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_rf_1 (
.dio_t (gpio_t[52:51]),
.dio_i (gpio_o[52:51]),
.dio_o (gpio_i[52:51]),
@ -265,7 +280,9 @@ module system_top (
// tact-scroll-wheel gpio - 50:47
ad_iobuf #(.DATA_WIDTH(4)) i_iobuf_tsw_1 (
ad_iobuf #(
.DATA_WIDTH(4)
) i_iobuf_tsw_1 (
.dio_t (gpio_t[50:47]),
.dio_i (gpio_o[50:47]),
.dio_o (gpio_i[50:47]),
@ -276,7 +293,9 @@ module system_top (
// ad9361 gpio - 46:32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_ad9361 (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_ad9361 (
.dio_t (gpio_t[46:32]),
.dio_i (gpio_o[46:32]),
.dio_o (gpio_i[46:32]),
@ -374,6 +393,3 @@ module system_top (
.up_txnrx (gpio_o[48]));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adrv9371x/a10gx/system_top.v
View File

@ -115,7 +115,8 @@ module system_top (
output spi_csn_ad9371,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -239,6 +240,3 @@ module system_top (
.sys_flash_tcm_chipselect_n_out (flash_cen[0]));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adrv9371x/a10soc/system_top.v
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@ -155,7 +155,8 @@ module system_top (
output spi_csn_ad9371,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -323,6 +324,3 @@ module system_top (
.rx_sysref_export (sysref));
endmodule
// ***************************************************************************
// ***************************************************************************

14
projects/adrv9371x/kcu105/system_top.v
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@ -127,7 +127,8 @@ module system_top (
inout ad9371_gpio_13,
inout ad9371_gpio_17,
inout ad9371_gpio_16,
inout ad9371_gpio_18);
inout ad9371_gpio_18
);
// internal signals
@ -191,7 +192,9 @@ module system_top (
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(28)
) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
@ -224,7 +227,9 @@ module system_top (
ad9371_gpio_16, // 33
ad9371_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(17)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(17)
) i_iobuf_bd (
.dio_t (gpio_t[16:0]),
.dio_i (gpio_o[16:0]),
.dio_o (gpio_i[16:0]),
@ -309,6 +314,3 @@ module system_top (
.ref_clk (ref_clk1_bufg));
endmodule
// ***************************************************************************
// ***************************************************************************

14
projects/adrv9371x/zc706/system_top.v
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@ -144,7 +144,8 @@ module system_top (
output [ 0:0] ddr3_odt,
output ddr3_ras_n,
output ddr3_reset_n,
output ddr3_we_n);
output ddr3_we_n
);
// internal signals
@ -198,7 +199,9 @@ module system_top (
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(28)
) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
@ -231,7 +234,9 @@ module system_top (
ad9371_gpio_16, // 33
ad9371_gpio_18})); // 32
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -340,6 +345,3 @@ module system_top (
.ref_clk (ref_clk1_bufg));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/adrv9371x/zcu102/system_top.v
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@ -94,7 +94,8 @@ module system_top (
inout ad9371_gpio_13,
inout ad9371_gpio_17,
inout ad9371_gpio_16,
inout ad9371_gpio_18);
inout ad9371_gpio_18
);
// internal signals
@ -152,7 +153,9 @@ module system_top (
.IB (sysref_n),
.O (sysref));
ad_iobuf #(.DATA_WIDTH(28)) i_iobuf (
ad_iobuf #(
.DATA_WIDTH(28)
) i_iobuf (
.dio_t ({gpio_t[59:32]}),
.dio_i ({gpio_o[59:32]}),
.dio_o ({gpio_i[59:32]}),
@ -238,6 +241,3 @@ module system_top (
.ref_clk (ref_clk1_bufg));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/adv7511/zc702/system_top.v
View File

@ -71,7 +71,8 @@ module system_top (
output spdif,
inout iic_scl,
inout iic_sda);
inout iic_sda
);
// internal signals
@ -81,7 +82,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(16)) i_gpio_bd (
ad_iobuf #(
.DATA_WIDTH(16)
) i_gpio_bd (
.dio_t (gpio_t[15:0]),
.dio_i (gpio_o[15:0]),
.dio_o (gpio_i[15:0]),
@ -142,6 +145,3 @@ module system_top (
.spi1_sdo_o());
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adv7511/zc706/system_top.v
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@ -71,7 +71,8 @@ module system_top (
output spdif,
inout iic_scl,
inout iic_sda);
inout iic_sda
);
// internal signals
@ -144,6 +145,3 @@ module system_top (
.spi1_sdo_o());
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/adv7511/zed/system_top.v
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@ -81,7 +81,8 @@ module system_top (
inout [ 1:0] iic_mux_scl,
inout [ 1:0] iic_mux_sda,
input otg_vbusoc);
input otg_vbusoc
);
// internal signals
@ -188,6 +189,3 @@ module system_top (
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************

4
projects/adv7513/de10nano/system_top.v
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@ -116,7 +116,6 @@ module system_top (
output ltc2308_sclk,
output ltc2308_mosi,
input ltc2308_miso
);
// internal signals
@ -228,6 +227,3 @@ module system_top (
.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
endmodule
// ***************************************************************************
// ***************************************************************************

19
projects/arradio/c5soc/system_top.v
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@ -150,7 +150,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -187,8 +188,17 @@ module system_top (
assign ga0 = 1'b0;
assign ga1 = 1'b0;
ALT_IOBUF scl_iobuf (.i(1'b0), .oe(i2c0_out_clk), .o(i2c0_scl_in_clk), .io(scl));
ALT_IOBUF sda_iobuf (.i(1'b0), .oe(i2c0_out_data), .o(i2c0_sda), .io(sda));
ALT_IOBUF scl_iobuf (
.i(1'b0),
.oe(i2c0_out_clk),
.o(i2c0_scl_in_clk),
.io(scl));
ALT_IOBUF sda_iobuf (
.i(1'b0),
.oe(i2c0_out_data),
.o(i2c0_sda),
.io(sda));
// instantiations
@ -293,6 +303,3 @@ module system_top (
.vga_out_vga_if_vga_vsync(vga_vsync));
endmodule
// ***************************************************************************
// ***************************************************************************

15
projects/cn0363/zed/system_top.v
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@ -88,7 +88,8 @@ module system_top (
output gain0_o,
output gain1_o,
input otg_vbusoc);
input otg_vbusoc
);
// internal signals
@ -119,8 +120,7 @@ module system_top (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd)
);
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
@ -128,8 +128,7 @@ module system_top (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl)
);
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
@ -137,8 +136,7 @@ module system_top (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda)
);
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
@ -211,6 +209,3 @@ module system_top (
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************

8
projects/cn0501/coraz7s/system_top.v
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@ -73,7 +73,8 @@ module system_top (
output spi_csn,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -121,7 +122,7 @@ module system_top (
assign gpio_i[47:44] = gpio_o[47:44];
assign gpio_i[63:53] = gpio_o[63:53];
ad7768_if i_ad7768_if (
ad7768_if i_ad7768_if (
.clk_in (clk_in),
.ready_in (ready_in),
.data_in (data_in),
@ -211,6 +212,3 @@ ad7768_if i_ad7768_if (
.spi1_sdo_o ());
endmodule
// ***************************************************************************
// ***************************************************************************

19
projects/cn0506_mii/a10soc/system_top.v
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@ -210,8 +210,17 @@ module system_top (
assign gpio_i[11: 4] = gpio_bd_i;
assign gpio_bd_o = gpio_o[3:0];
ALT_IOBUF md_iobuf_a (.i(hps_emac_mdo_o_a), .oe(hps_emac_mdo_o_e_a), .o(hps_emac_mdi_i_a), .io(mdio_fmc_a));
ALT_IOBUF md_iobuf_b (.i(hps_emac_mdo_o_b), .oe(hps_emac_mdo_o_e_b), .o(hps_emac_mdi_i_b), .io(mdio_fmc_b));
ALT_IOBUF md_iobuf_a (
.i(hps_emac_mdo_o_a),
.oe(hps_emac_mdo_o_e_a),
.o(hps_emac_mdi_i_a),
.io(mdio_fmc_a));
ALT_IOBUF md_iobuf_b (
.i(hps_emac_mdo_o_b),
.oe(hps_emac_mdo_o_e_b),
.o(hps_emac_mdi_i_b),
.io(mdio_fmc_b));
// peripheral reset
@ -325,10 +334,6 @@ module system_top (
.sys_hps_emac2_gmii_mdi_i (hps_emac_mdi_i_b),
.sys_hps_emac2_md_clk_clk (mdc_fmc_b),
.sys_hps_emac2_rx_clk_in_clk (mii_rx_clk_b),
.sys_hps_emac2_tx_clk_in_clk (mii_tx_clk_b)
);
.sys_hps_emac2_tx_clk_in_clk (mii_tx_clk_b));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/cn0506_mii/zc706/system_top.v
View File

@ -164,7 +164,9 @@ module system_top (
assign gpio_i[33:15] = gpio_o[33:15];
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -250,10 +252,6 @@ module system_top (
.GMII_ETHERNET_1_0_tx_er(),
.GMII_ETHERNET_1_0_txd({mii_txd_extra_b,mii_txd_b}),
.MDIO_ETHERNET_1_0_mdc(mdc_fmc_b),
.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b)
);
.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/cn0506_mii/zcu102/system_top.v
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@ -174,10 +174,6 @@ module system_top (
.GMII_ENET1_0_txd({mii_txd_extra_b,mii_txd_b}),
.GMII_ENET1_0_speed_mode(speed_mode_b_s),
.MDIO_ENET1_0_mdc(mdc_fmc_b),
.MDIO_ENET1_0_mdio_io(mdio_fmc_b)
);
.MDIO_ENET1_0_mdio_io(mdio_fmc_b));
endmodule
// ***************************************************************************
// ***************************************************************************

18
projects/cn0506_mii/zed/system_top.v
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@ -172,19 +172,25 @@ module system_top (
assign gpio_i[35] = link_st_a;
assign gpio_i[34] = link_st_b;
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_bd (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_scl (
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_sda (
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
@ -282,10 +288,6 @@ module system_top (
.GMII_ETHERNET_1_0_tx_er(),
.GMII_ETHERNET_1_0_txd({mii_txd_extra_b,mii_txd_b}),
.MDIO_ETHERNET_1_0_mdc(mdc_fmc_b),
.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b)
);
.MDIO_ETHERNET_1_0_mdio_io(mdio_fmc_b));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/cn0506_rgmii/zc706/system_top.v
View File

@ -164,7 +164,9 @@ module system_top (
assign gpio_i[31:15] = gpio_o[31:15];
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -251,10 +253,6 @@ module system_top (
.RGMII_1_td (rgmii_txd_b),
.RGMII_1_tx_ctl (rgmii_tx_ctl_b),
.RGMII_1_txc (rgmii_txc_b),
.speed_mode_b (speed_mode_b_s)
);
.speed_mode_b (speed_mode_b_s));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/cn0506_rgmii/zcu102/system_top.v
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@ -173,10 +173,6 @@ module system_top (
.RGMII_1_td (rgmii_txd_b),
.RGMII_1_tx_ctl (rgmii_tx_ctl_b),
.RGMII_1_txc (rgmii_txc_b),
.speed_mode_b (speed_mode_b_s)
);
.speed_mode_b (speed_mode_b_s));
endmodule
// ***************************************************************************
// ***************************************************************************

18
projects/cn0506_rgmii/zed/system_top.v
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@ -175,7 +175,9 @@ module system_top (
assign gpio_i[33] = int_n_a;
assign gpio_i[32] = int_n_b;
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_bd (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
@ -186,13 +188,17 @@ module system_top (
.IB (ref_clk_125_n),
.O (ref_clk_125));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_scl (
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_sda (
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
@ -286,10 +292,6 @@ module system_top (
.RGMII_1_td (rgmii_txd_b),
.RGMII_1_tx_ctl (rgmii_tx_ctl_b),
.RGMII_1_txc (rgmii_txc_b),
.speed_mode_b (speed_mode_b_s)
);
.speed_mode_b (speed_mode_b_s));
endmodule
// ***************************************************************************
// ***************************************************************************

10
projects/cn0506_rmii/zc706/system_top.v
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@ -163,7 +163,9 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(15)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(15)
) i_iobuf_bd (
.dio_t (gpio_t[14:0]),
.dio_i (gpio_o[14:0]),
.dio_o (gpio_i[14:0]),
@ -237,10 +239,6 @@ module system_top (
.RMII_PHY_M_1_rx_er (rmii_rx_er_b),
.RMII_PHY_M_1_rxd (rmii_rxd_b),
.RMII_PHY_M_1_tx_en (rmii_tx_en_b),
.RMII_PHY_M_1_txd (rmii_txd_b)
);
.RMII_PHY_M_1_txd (rmii_txd_b));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/cn0506_rmii/zcu102/system_top.v
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@ -163,10 +163,6 @@ module system_top (
.RMII_PHY_M_1_rx_er (rmii_rx_er_b),
.RMII_PHY_M_1_rxd (rmii_rxd_b),
.RMII_PHY_M_1_tx_en (rmii_tx_en_b),
.RMII_PHY_M_1_txd (rmii_txd_b)
);
.RMII_PHY_M_1_txd (rmii_txd_b));
endmodule
// ***************************************************************************
// ***************************************************************************

18
projects/cn0506_rmii/zed/system_top.v
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@ -179,19 +179,25 @@ module system_top (
// instantiations
ad_iobuf #(.DATA_WIDTH(32)) i_iobuf_bd (
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf_bd (
.dio_t (gpio_t[31:0]),
.dio_i (gpio_o[31:0]),
.dio_o (gpio_i[31:0]),
.dio_p (gpio_bd));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_scl (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_scl (
.dio_t ({iic_mux_scl_t_s,iic_mux_scl_t_s}),
.dio_i (iic_mux_scl_o_s),
.dio_o (iic_mux_scl_i_s),
.dio_p (iic_mux_scl));
ad_iobuf #(.DATA_WIDTH(2)) i_iobuf_iic_sda (
ad_iobuf #(
.DATA_WIDTH(2)
) i_iobuf_iic_sda (
.dio_t ({iic_mux_sda_t_s,iic_mux_sda_t_s}),
.dio_i (iic_mux_sda_o_s),
.dio_o (iic_mux_sda_i_s),
@ -277,10 +283,6 @@ module system_top (
.RMII_PHY_M_1_rx_er (rmii_rx_er_b),
.RMII_PHY_M_1_rxd (rmii_rxd_b),
.RMII_PHY_M_1_tx_en (rmii_tx_en_b),
.RMII_PHY_M_1_txd (rmii_txd_b)
);
.RMII_PHY_M_1_txd (rmii_txd_b));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/cn0540/coraz7s/system_top.v
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@ -94,7 +94,8 @@ module system_top (
output cn0540_spi_mosi,
output cn0540_spi_sclk,
output cn0540_spi_cs,
inout cn0540_drdy);
inout cn0540_drdy
);
// internal signals
@ -208,6 +209,3 @@ module system_top (
.xadc_vaux15_v_n (cn0540_ck_an3_n));
endmodule
// ***************************************************************************
// ***************************************************************************

5
projects/cn0540/de10nano/system_top.v
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@ -114,7 +114,6 @@ module system_top (
inout hdmi_i2c_scl,
inout hdmi_i2c_sda,
// cn0540
inout i2c_sda,
@ -181,7 +180,6 @@ module system_top (
assign gpio_i[31:14] = gpio_o[31:14];
assign gpio_i[13:8] = gpio_bd_i[5:0];
// IO Buffers for I2C
ALT_IOBUF scl_iobuf (
@ -299,6 +297,3 @@ module system_top (
.axi_hdmi_tx_0_hdmi_if_h24_data (hdmi_data));
endmodule
// ***************************************************************************
// ***************************************************************************

6
projects/cn0561/coraz7s/system_top.v
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@ -79,7 +79,8 @@ module system_top (
input [ 3:0] cn0561_din,
output cn0561_odr,
inout cn0561_pdn);
inout cn0561_pdn
);
// internal signals
@ -169,6 +170,3 @@ module system_top (
.cn0561_odr (cn0561_odr));
endmodule
// ***************************************************************************
// ***************************************************************************

7
projects/cn0561/zed/system_top.v
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@ -76,7 +76,6 @@ module system_top (
output i2s_sdata_out,
input i2s_sdata_in,
inout iic_scl,
inout iic_sda,
inout [ 1:0] iic_mux_scl,
@ -109,7 +108,8 @@ module system_top (
inout cn0561_gpio4,
inout cn0561_gpio5,
inout cn0561_gpio6,
inout cn0561_gpio7);
inout cn0561_gpio7
);
// internal signals
@ -240,6 +240,3 @@ module system_top (
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************

16
projects/dac_fmc_ebz/a10soc/system_top.v
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@ -36,11 +36,11 @@
`timescale 1ns/100ps
module system_top #(
parameter JESD_L = 4,
parameter MODE = 4,
parameter DEVICE = "AD9172",
parameter DEVICE_CODE = 1
) (
parameter JESD_L = 4,
parameter MODE = 4,
parameter DEVICE = "AD9172",
parameter DEVICE_CODE = 1
) (
// clock and resets
@ -149,7 +149,8 @@ module system_top #(
output spi_csn_dac,
output spi_clk,
output spi_mosi,
input spi_miso);
input spi_miso
);
// internal signals
@ -301,6 +302,3 @@ module system_top #(
.tx_sysref_export (tx_sysref));
endmodule
// ***************************************************************************
// ***************************************************************************

38
projects/dac_fmc_ebz/vcu118/system_top.v
View File

@ -36,17 +36,16 @@
`timescale 1ns/100ps
module system_top #(
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
input sys_rst,
input sys_clk_p,
input sys_clk_n,
input uart_sin,
output uart_sout,
output ddr4_act_n,
output [16:0] ddr4_addr,
output [ 1:0] ddr4_ba,
@ -127,41 +126,35 @@ module system_top #(
assign spi_csn_clk = spi_csn[0]; // HMC7044 AD9508
assign spi_csn_clk2 = spi_csn[2]; // NC ADF4355
/* JESD204 clocks and control signals */
IBUFDS_GTE4 i_ibufds_tx_ref_clk_121 (
.CEB (1'd0),
.I (tx_ref_clk_121_p),
.IB (tx_ref_clk_121_n),
.O (tx_ref_clk_121),
.ODIV2 ()
);
.ODIV2 ());
IBUFDS_GTE4 i_ibufds_tx_ref_clk_126 (
.CEB (1'd0),
.I (tx_ref_clk_126_p),
.IB (tx_ref_clk_126_n),
.O (tx_ref_clk_126),
.ODIV2 ()
);
.ODIV2 ());
IBUFDS i_ibufds_tx_sysref (
.I (tx_sysref_p),
.IB (tx_sysref_n),
.O (tx_sysref)
);
.O (tx_sysref));
IBUFDS i_ibufds_tx_sync_0 (
.I (tx_sync_p[0]),
.IB (tx_sync_n[0]),
.O (tx_sync[0])
);
.O (tx_sync[0]));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_p[1]),
.IB (tx_sync_n[1]),
.O (tx_sync[1])
);
.O (tx_sync[1]));
/* FMC GPIOs */
ad_iobuf #(
@ -172,8 +165,7 @@ module system_top #(
.dio_o (gpio_i[21+:5]),
.dio_p ({
dac_ctrl /* 25 - 21 */
})
);
}));
/*
* Control signals for different FMC boards:
@ -183,7 +175,7 @@ module system_top #(
* 1 C10 NC NC FMC_TXEN_0
* 2 C11 NC NC FMC_TXEN_1
* 3 H14 FMC_TXEN_1 NC NC
* 4 D15 NC FMC_HMC849VCTL NC
* 4 D15 NC FMC_HMC849VCTL NC
*/
assign dac_fifo_bypass = gpio_o[40];
@ -195,8 +187,7 @@ module system_top #(
.dio_t (gpio_t[0+:17]),
.dio_i (gpio_o[0+:17]),
.dio_o (gpio_i[0+:17]),
.dio_p (gpio_bd)
);
.dio_p (gpio_bd));
assign gpio_i[63:26] = gpio_o[63:26];
assign gpio_i[20:17] = gpio_o[20:17];
@ -273,6 +264,3 @@ module system_top #(
assign tx_sysref_loc = (DEVICE_CODE == 3) ? tx_sync[1] : tx_sysref;
endmodule
// ***************************************************************************
// ***************************************************************************

32
projects/dac_fmc_ebz/zc706/system_top.v
View File

@ -36,10 +36,9 @@
`timescale 1ns/100ps
module system_top #(
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
inout [14:0] ddr_addr,
inout [ 2:0] ddr_ba,
inout ddr_cas_n,
@ -100,7 +99,7 @@ module system_top #(
output pmod_spi_mosi,
input pmod_spi_miso,
inout [ 3:0] pmod_gpio
);
);
// internal signals
@ -138,26 +137,22 @@ module system_top #(
.I (tx_ref_clk_p),
.IB (tx_ref_clk_n),
.O (tx_ref_clk),
.ODIV2 ()
);
.ODIV2 ());
IBUFDS i_ibufds_tx_sysref (
.I (tx_sysref_p),
.IB (tx_sysref_n),
.O (tx_sysref)
);
.O (tx_sysref));
IBUFDS i_ibufds_tx_sync_0 (
.I (tx_sync_p[0]),
.IB (tx_sync_n[0]),
.O (tx_sync[0])
);
.O (tx_sync[0]));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_p[1]),
.IB (tx_sync_n[1]),
.O (tx_sync[1])
);
.O (tx_sync[1]));
/* FMC GPIOs */
ad_iobuf #(
@ -168,8 +163,7 @@ module system_top #(
.dio_o (gpio_i[21+:5]),
.dio_p ({
dac_ctrl /* 25 - 21 */
})
);
}));
/*
* Control signals for different FMC boards:
@ -179,7 +173,7 @@ module system_top #(
* 1 C10 NC NC FMC_TXEN_0
* 2 C11 NC NC FMC_TXEN_1
* 3 H14 FMC_TXEN_1 NC NC
* 4 D15 NC FMC_HMC849VCTL NC
* 4 D15 NC FMC_HMC849VCTL NC
*/
assign dac_fifo_bypass = gpio_o[40];
@ -191,8 +185,7 @@ module system_top #(
.dio_t (gpio_t[48+:4]),
.dio_i (gpio_o[48+:4]),
.dio_o (gpio_i[48+:4]),
.dio_p (pmod_gpio)
);
.dio_p (pmod_gpio));
/* PMOD SPI */
assign pmod_spi_clk = spi1_clk;
@ -207,8 +200,7 @@ module system_top #(
.dio_t (gpio_t[0+:15]),
.dio_i (gpio_o[0+:15]),
.dio_o (gpio_i[0+:15]),
.dio_p (gpio_bd)
);
.dio_p (gpio_bd));
assign gpio_i[63:52] = gpio_o[63:52];
assign gpio_i[47:26] = gpio_o[47:26];

31
projects/dac_fmc_ebz/zcu102/system_top.v
View File

@ -80,10 +80,9 @@ tx_sysref_p SYSREF2_P G06 FMC_HPC0_LA00_CC_P Y4 IO_L13P_T2L_
*/
module system_top #(
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
parameter NUM_LINKS = 2,
parameter DEVICE_CODE = 0
) (
input [12:0] gpio_bd_i,
output [ 7:0] gpio_bd_o,
@ -146,26 +145,22 @@ module system_top #(
.I (tx_ref_clk_p),
.IB (tx_ref_clk_n),
.O (tx_ref_clk),
.ODIV2 ()
);
.ODIV2 ());
IBUFDS i_ibufds_tx_sysref (
.I (tx_sysref_p),
.IB (tx_sysref_n),
.O (tx_sysref)
);
.O (tx_sysref));
IBUFDS i_ibufds_tx_sync_0 (
.I (tx_sync_p[0]),
.IB (tx_sync_n[0]),
.O (tx_sync[0])
);
.O (tx_sync[0]));
IBUFDS i_ibufds_tx_sync_1 (
.I (tx_sync_p[1]),
.IB (tx_sync_n[1]),
.O (tx_sync[1])
);
.O (tx_sync[1]));
/* FMC GPIOs */
ad_iobuf #(
@ -176,8 +171,7 @@ module system_top #(
.dio_o (gpio_i[21+:5]),
.dio_p ({
dac_ctrl /* 25 - 21 */
})
);
}));
/*
* Control signals for different FMC boards:
@ -187,7 +181,7 @@ module system_top #(
* 1 C10 NC NC FMC_TXEN_0
* 2 C11 NC NC FMC_TXEN_1
* 3 H14 FMC_TXEN_1 NC NC
* 4 D15 NC FMC_HMC849VCTL NC
* 4 D15 NC FMC_HMC849VCTL NC
*/
assign dac_fifo_bypass = gpio_o[40];
@ -199,8 +193,7 @@ module system_top #(
.dio_t (gpio_t[48+:4]),
.dio_i (gpio_o[48+:4]),
.dio_o (gpio_i[48+:4]),
.dio_p (pmod_gpio)
);
.dio_p (pmod_gpio));
/* PMOD SPI */
assign pmod_spi_csn = spi1_csn[0];
@ -251,8 +244,4 @@ module system_top #(
// The FMC connector instead of SYNC1 has SYSREF connected to it
assign tx_sysref_loc = (DEVICE_CODE == 3) ? tx_sync[1] : tx_sysref;
endmodule
// ***************************************************************************
// ***************************************************************************

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