diff --git a/library/axi_ad9671/axi_ad9671.v b/library/axi_ad9671/axi_ad9671.v index 5549dcbb6..c00c8eec5 100755 --- a/library/axi_ad9671/axi_ad9671.v +++ b/library/axi_ad9671/axi_ad9671.v @@ -377,7 +377,6 @@ module axi_ad9671 ( .drp_locked (1'd0), .up_usr_chanmax (), .adc_usr_chanmax (8'd7), - .dma_bw (32'd128), .up_rstn (up_rstn), .up_clk (up_clk), .up_sel (up_sel_s), diff --git a/projects/usdrx1/common/usdrx1_bd.tcl b/projects/usdrx1/common/usdrx1_bd.tcl index 173f5b6e9..46df71e71 100755 --- a/projects/usdrx1/common/usdrx1_bd.tcl +++ b/projects/usdrx1/common/usdrx1_bd.tcl @@ -82,8 +82,8 @@ set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {512}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {64}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_SRC {512}] $axi_usdrx1_dma +set_property -dict [list CONFIG.C_DMA_DATA_WIDTH_DEST {512}] $axi_usdrx1_dma set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect] set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect @@ -100,16 +100,16 @@ set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi # additions to default configuration -set_property -dict [list CONFIG.NUM_MI {12}] $axi_cpu_interconnect -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $processing_system7_1 +set_property -dict [list CONFIG.NUM_MI {15}] $axi_cpu_interconnect +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $sys_ps7 +set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $sys_ps7 +set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $sys_ps7 set_property LEFT 43 [get_bd_ports GPIO_I] set_property LEFT 43 [get_bd_ports GPIO_O] @@ -126,7 +126,7 @@ connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_u connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_spi/ext_spi_clk] -connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_spi_1_irq [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] [get_bd_pins sys_concat_intc/In3] # connections (gt) @@ -182,7 +182,7 @@ connect_bd_net -net axi_ad9671_dma_adc_dwr [get_bd_pins axi_usdrx1_dma/ connect_bd_net -net axi_ad9671_dma_adc_dsync [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] [get_bd_ports adc_dsync] connect_bd_net -net axi_ad9671_dma_adc_ddata [get_bd_pins axi_usdrx1_dma/fifo_wr_din] [get_bd_ports adc_ddata] connect_bd_net -net axi_ad9671_dma_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] [get_bd_ports adc_dovf] -connect_bd_net -net axi_ad9671_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] +connect_bd_net -net axi_usdrx1_dma_irq [get_bd_pins axi_usdrx1_dma/irq] [get_bd_pins sys_concat_intc/In2] # interconnect (cpu) @@ -230,7 +230,7 @@ connect_bd_net -net sys_100m_resetn [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] # interconnect (gt es) connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi] -connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP3] +connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP3] connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] $sys_100m_clk_source connect_bd_net -net sys_100m_clk [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] $sys_100m_clk_source @@ -250,7 +250,7 @@ set sys_fmc_dma_resetn_source [get_bd_pins sys_ps7/FCLK_RESET2_N] connect_bd_net -net sys_fmc_dma_clk $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_resetn $sys_fmc_dma_resetn_source -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP2] +connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins sys_ps7/S_AXI_HP2] connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] $sys_fmc_dma_clk_source connect_bd_net -net sys_fmc_dma_clk [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] $sys_fmc_dma_clk_source @@ -277,15 +277,15 @@ connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins ila_jesd_rx_mon # address map -create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0 -create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1 -create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2 -create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3 +create_bd_addr_seg -range 0x00010000 -offset 0x44A00000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0 +create_bd_addr_seg -range 0x00010000 -offset 0x44A10000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1 +create_bd_addr_seg -range 0x00010000 -offset 0x44A20000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2 +create_bd_addr_seg -range 0x00010000 -offset 0x44A30000 $sys_addr_cntrl_space [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3 -create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt -create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd -create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma -create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi +create_bd_addr_seg -range 0x00010000 -offset 0x44A60000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt +create_bd_addr_seg -range 0x00001000 -offset 0x44A91000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd +create_bd_addr_seg -range 0x00010000 -offset 0x7c400000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma +create_bd_addr_seg -range 0x00010000 -offset 0x7c420000 $sys_addr_cntrl_space [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_sys_ps7_hp2_ddr_lowocm create_bd_addr_seg -range $sys_mem_size -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs sys_ps7/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_sys_ps7_hp3_ddr_lowocm diff --git a/projects/usdrx1/common/usdrx1_spi.v b/projects/usdrx1/common/usdrx1_spi.v index 552a9536c..a9d293703 100755 --- a/projects/usdrx1/common/usdrx1_spi.v +++ b/projects/usdrx1/common/usdrx1_spi.v @@ -88,7 +88,7 @@ module usdrx1_spi ( assign spi_csn_s = & spi_csn_3_s; assign spi_enable_s = spi_enable & ~spi_csn_s; - always @(posedge spi_clk) begin + always @(posedge spi_clk or posedge spi_csn_s) begin if (spi_csn_s == 1'b1) begin spi_count <= 6'd0; spi_rd_wr_n <= 1'd0; @@ -100,7 +100,7 @@ module usdrx1_spi ( end end - always @(negedge spi_clk) begin + always @(negedge spi_clk or posedge spi_csn_s) begin if (spi_csn_s == 1'b1) begin spi_enable <= 1'b0; end else begin diff --git a/projects/usdrx1/zc706/system_bd.tcl b/projects/usdrx1/zc706/system_bd.tcl index db7a500ee..8450cffa5 100755 --- a/projects/usdrx1/zc706/system_bd.tcl +++ b/projects/usdrx1/zc706/system_bd.tcl @@ -1,434 +1,4 @@ -# create board design -# interface ports - -set DDR [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR] -set FIXED_IO [create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO] -set IIC_MAIN [create_bd_intf_port -mode Master -vlnv xilinx.com:interface:iic_rtl:1.0 IIC_MAIN] - -set GPIO_I [create_bd_port -dir I -from 43 -to 0 GPIO_I] -set GPIO_O [create_bd_port -dir O -from 43 -to 0 GPIO_O] -set GPIO_T [create_bd_port -dir O -from 43 -to 0 GPIO_T] - -# interface ports - -set hdmi_out_clk [create_bd_port -dir O hdmi_out_clk] -set hdmi_hsync [create_bd_port -dir O hdmi_hsync] -set hdmi_vsync [create_bd_port -dir O hdmi_vsync] -set hdmi_data_e [create_bd_port -dir O hdmi_data_e] -set hdmi_data [create_bd_port -dir O -from 23 -to 0 hdmi_data] -set hdmi_int [create_bd_port -dir I hdmi_int] - -set rx_ref_clk [create_bd_port -dir I rx_ref_clk] -set rx_data_p [create_bd_port -dir I -from 7 -to 0 rx_data_p] -set rx_data_n [create_bd_port -dir I -from 7 -to 0 rx_data_n] -set rx_sync [create_bd_port -dir O rx_sync] -set rx_sysref [create_bd_port -dir O rx_sysref] - -set mlo_clk [create_bd_port -dir O mlo_clk] - -set spi_csn_i [create_bd_port -dir I -from 10 -to 0 spi_csn_i] -set spi_csn_o [create_bd_port -dir O -from 10 -to 0 spi_csn_o] -set spi_clk_i [create_bd_port -dir I spi_clk_i] -set spi_clk_o [create_bd_port -dir O spi_clk_o] -set spi_sdo_i [create_bd_port -dir I spi_sdo_i] -set spi_sdo_o [create_bd_port -dir O spi_sdo_o] -set spi_sdi_i [create_bd_port -dir I spi_sdi_i] - -# instance: processing_system7_1 - -set processing_system7_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.3 processing_system7_1] -set_property -dict [list CONFIG.PCW_IMPORT_BOARD_PRESET {ZC706}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_CLK1_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_CLK2_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_CLK3_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_RST1_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_EN_RST2_PORT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA0_PERIPHERAL_FREQMHZ {100.0}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA1_PERIPHERAL_FREQMHZ {200.0}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA2_PERIPHERAL_FREQMHZ {200.0}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_FPGA3_PERIPHERAL_FREQMHZ {40}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_USE_FABRIC_INTERRUPT {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP0 {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP2 {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_USE_S_AXI_HP3 {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_IRQ_F2P_INTR {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1}] $processing_system7_1 -set_property -dict [list CONFIG.PCW_GPIO_EMIO_GPIO_IO {44}] $processing_system7_1 - -set axi_iic_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_iic:2.0 axi_iic_1] -set_property -dict [list CONFIG.USE_BOARD_FLOW {true} CONFIG.IIC_BOARD_INTERFACE {IIC_MAIN}] $axi_iic_1 - -set xlconcat_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 xlconcat_1] -set_property -dict [list CONFIG.NUM_PORTS {5}] $xlconcat_1 - -set axi_interconnect_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_interconnect_1] -set_property -dict [list CONFIG.NUM_MI {12}] $axi_interconnect_1 - -# hdmi peripherals - -set axi_hdmi_clkgen [create_bd_cell -type ip -vlnv analog.com:user:axi_clkgen:1.0 axi_hdmi_clkgen] -set axi_hdmi_core [create_bd_cell -type ip -vlnv analog.com:user:axi_hdmi_tx:1.0 axi_hdmi_core] - -set axi_hdmi_dma [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_vdma:6.1 axi_hdmi_dma] -set_property -dict [list CONFIG.c_m_axis_mm2s_tdata_width {64}] $axi_hdmi_dma -set_property -dict [list CONFIG.c_use_mm2s_fsync {1}] $axi_hdmi_dma -set_property -dict [list CONFIG.c_include_s2mm {0}] $axi_hdmi_dma - -set axi_hdmi_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_hdmi_interconnect] -set_property -dict [list CONFIG.NUM_MI {1}] $axi_hdmi_interconnect - -# ultrasound - -set axi_usdrx1_gt [create_bd_cell -type ip -vlnv analog.com:user:axi_jesd_gt:1.0 axi_usdrx1_gt] -set_property -dict [list CONFIG.PCORE_NUM_OF_LANES {8}] [get_bd_cells axi_usdrx1_gt] - -set axi_usdrx1_jesd [create_bd_cell -type ip -vlnv xilinx.com:ip:jesd204:5.1 axi_usdrx1_jesd] -set_property -dict [list CONFIG.C_NODE_IS_TRANSMIT {0}] $axi_usdrx1_jesd -set_property -dict [list CONFIG.C_LANES {8}] $axi_usdrx1_jesd - -set axi_ad9671_core_0 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_0] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_0] - -set axi_ad9671_core_1 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_1] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_1] - -set axi_ad9671_core_2 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_2] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_2] - -set axi_ad9671_core_3 [create_bd_cell -type ip -vlnv analog.com:user:axi_ad9671:1.0 axi_ad9671_core_3] -set_property -dict [list CONFIG.PCORE_4L_2L_N {0}] [get_bd_cells axi_ad9671_core_3] - -set axi_usdrx1_dma [create_bd_cell -type ip -vlnv analog.com:user:axi_dmac:1.0 axi_usdrx1_dma] -set_property -dict [list CONFIG.C_DMA_TYPE_SRC {2}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_TYPE_DEST {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.PCORE_ID {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_SRC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_AXI_SLICE_DEST {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_CLKS_ASYNC_DEST_REQ {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_SYNC_TRANSFER_START {1}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_DMA_LENGTH_WIDTH {24}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_2D_TRANSFER {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_CYCLIC {0}] $axi_usdrx1_dma -set_property -dict [list CONFIG.C_M_DEST_AXI_DATA_WIDTH {512}] $axi_usdrx1_dma - -set axi_usdrx1_spi [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_quad_spi:3.1 axi_usdrx1_spi] -set_property -dict [list CONFIG.C_USE_STARTUP {0}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_NUM_SS_BITS {11}] $axi_usdrx1_spi -set_property -dict [list CONFIG.C_SCK_RATIO {8}] $axi_usdrx1_spi - -set axi_usdrx1_gt_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_gt_interconnect] -set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_gt_interconnect - -set axi_usdrx1_dma_interconnect [create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_usdrx1_dma_interconnect] -set_property -dict [list CONFIG.NUM_MI {1}] $axi_usdrx1_dma_interconnect - -set dma_concat_data [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_data] -set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_data -set_property -dict [list CONFIG.IN0_WIDTH {128}] $dma_concat_data -set_property -dict [list CONFIG.IN1_WIDTH {128}] $dma_concat_data -set_property -dict [list CONFIG.IN2_WIDTH {128}] $dma_concat_data -set_property -dict [list CONFIG.IN3_WIDTH {128}] $dma_concat_data - -set dma_concat_sync [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_sync] -set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_sync -set_property -dict [list CONFIG.IN0_WIDTH {1}] $dma_concat_sync -set_property -dict [list CONFIG.IN1_WIDTH {1}] $dma_concat_sync -set_property -dict [list CONFIG.IN2_WIDTH {1}] $dma_concat_sync -set_property -dict [list CONFIG.IN3_WIDTH {1}] $dma_concat_sync - -set dma_concat_wr [create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:1.0 dma_concat_wr] -set_property -dict [list CONFIG.NUM_PORTS {4}] $dma_concat_wr -set_property -dict [list CONFIG.IN0_WIDTH {1}] $dma_concat_wr -set_property -dict [list CONFIG.IN1_WIDTH {1}] $dma_concat_wr -set_property -dict [list CONFIG.IN2_WIDTH {1}] $dma_concat_wr -set_property -dict [list CONFIG.IN3_WIDTH {1}] $dma_concat_wr - -set dma_concat_sync_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:1.0 dma_concat_sync_or] -set_property -dict [list CONFIG.C_SIZE {4}] $dma_concat_sync_or -set_property -dict [list CONFIG.C_OPERATION {or}] $dma_concat_sync_or - -set dma_concat_wr_or [create_bd_cell -type ip -vlnv xilinx.com:ip:util_reduced_logic:1.0 dma_concat_wr_or] -set_property -dict [list CONFIG.C_SIZE {4}] $dma_concat_wr_or -set_property -dict [list CONFIG.C_OPERATION {or}] $dma_concat_wr_or - -set gt_slice_data_0 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_0] -set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_0 -set_property -dict [list CONFIG.DIN_FROM {63}] $gt_slice_data_0 -set_property -dict [list CONFIG.DIN_TO {0}] $gt_slice_data_0 - -set gt_slice_data_1 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_1] -set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_1 -set_property -dict [list CONFIG.DIN_FROM {127}] $gt_slice_data_1 -set_property -dict [list CONFIG.DIN_TO {64}] $gt_slice_data_1 - -set gt_slice_data_2 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_2] -set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_2 -set_property -dict [list CONFIG.DIN_FROM {191}] $gt_slice_data_2 -set_property -dict [list CONFIG.DIN_TO {128}] $gt_slice_data_2 - -set gt_slice_data_3 [create_bd_cell -type ip -vlnv xilinx.com:ip:xlslice:1.0 gt_slice_data_3] -set_property -dict [list CONFIG.DIN_WIDTH {256}] $gt_slice_data_3 -set_property -dict [list CONFIG.DIN_FROM {255}] $gt_slice_data_3 -set_property -dict [list CONFIG.DIN_TO {192}] $gt_slice_data_3 - -set ila_jesd_rx_mon [create_bd_cell -type ip -vlnv xilinx.com:ip:ila:3.0 ila_jesd_rx_mon] -set_property -dict [list CONFIG.C_NUM_OF_PROBES {2}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE0_WIDTH {662}] $ila_jesd_rx_mon -set_property -dict [list CONFIG.C_PROBE1_WIDTH {10}] $ila_jesd_rx_mon - -# interface connections - -connect_bd_intf_net -intf_net processing_system7_1_ddr [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_1/DDR] -connect_bd_net -net processing_system7_1_GPIO_I [get_bd_ports GPIO_I] [get_bd_pins processing_system7_1/GPIO_I] -connect_bd_net -net processing_system7_1_GPIO_O [get_bd_ports GPIO_O] [get_bd_pins processing_system7_1/GPIO_O] -connect_bd_net -net processing_system7_1_GPIO_T [get_bd_ports GPIO_T] [get_bd_pins processing_system7_1/GPIO_T] -connect_bd_intf_net -intf_net processing_system7_1_fixed_io [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_1/FIXED_IO] -connect_bd_intf_net -intf_net axi_iic_1_iic [get_bd_intf_ports IIC_MAIN] [get_bd_intf_pins axi_iic_1/iic] - -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk1 [get_bd_pins processing_system7_1/FCLK_CLK1] -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins processing_system7_1/FCLK_CLK2] -connect_bd_net -net processing_system7_1_fclk_clk3 [get_bd_pins processing_system7_1/FCLK_CLK3] [get_bd_ports mlo_clk] - - -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins processing_system7_1/FCLK_RESET2_N] - -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/M_AXI_GP0_ACLK] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] - -connect_bd_intf_net -intf_net axi_interconnect_1_s00_axi [get_bd_intf_pins axi_interconnect_1/S00_AXI] [get_bd_intf_pins processing_system7_1/M_AXI_GP0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] - -connect_bd_intf_net -intf_net axi_interconnect_1_m00_axi [get_bd_intf_pins axi_interconnect_1/M00_AXI] [get_bd_intf_pins axi_iic_1/s_axi] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_iic_1/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_iic_1/s_axi_aresetn] -connect_bd_net -net xlconcat_din_0 [get_bd_pins xlconcat_1/In0] [get_bd_pins axi_iic_1/iic2intc_irpt] - -connect_bd_net -net processing_system7_1_interrupt [get_bd_pins xlconcat_1/dout] [get_bd_pins processing_system7_1/IRQ_F2P] - -# hdmi - -connect_bd_net -net processing_system7_1_fclk_clk1 [get_bd_pins axi_hdmi_clkgen/clk] - -connect_bd_intf_net -intf_net axi_interconnect_1_m01_axi [get_bd_intf_pins axi_interconnect_1/M01_AXI] [get_bd_intf_pins axi_hdmi_clkgen/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m02_axi [get_bd_intf_pins axi_interconnect_1/M02_AXI] [get_bd_intf_pins axi_hdmi_core/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m03_axi [get_bd_intf_pins axi_interconnect_1/M03_AXI] [get_bd_intf_pins axi_hdmi_dma/S_AXI_LITE] - -connect_bd_intf_net -intf_net axi_hdmi_interconnect_s00_axi [get_bd_intf_pins axi_hdmi_interconnect/S00_AXI] [get_bd_intf_pins axi_hdmi_dma/M_AXI_MM2S] -connect_bd_intf_net -intf_net axi_hdmi_interconnect_m00_axi [get_bd_intf_pins axi_hdmi_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP0] - -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M01_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M02_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M03_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_clkgen/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_clkgen/drp_clk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_core/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_core/m_axis_mm2s_clk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/s_axi_lite_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/m_axi_mm2s_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_hdmi_dma/m_axis_mm2s_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/S_AXI_HP0_ACLK] - -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M01_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M02_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M03_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_clkgen/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_core/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_hdmi_dma/axi_resetn] - -connect_bd_net -net axi_hdmi_tx_1_hdmi_clk [get_bd_pins axi_hdmi_core/hdmi_clk] [get_bd_pins axi_hdmi_clkgen/clk_0] -connect_bd_net -net axi_hdmi_tx_1_hdmi_out_clk [get_bd_pins axi_hdmi_core/hdmi_out_clk] [get_bd_ports hdmi_out_clk] -connect_bd_net -net axi_hdmi_tx_1_hdmi_hsync [get_bd_pins axi_hdmi_core/hdmi_24_hsync] [get_bd_ports hdmi_hsync] -connect_bd_net -net axi_hdmi_tx_1_hdmi_vsync [get_bd_pins axi_hdmi_core/hdmi_24_vsync] [get_bd_ports hdmi_vsync] -connect_bd_net -net axi_hdmi_tx_1_hdmi_data_e [get_bd_pins axi_hdmi_core/hdmi_24_data_e] [get_bd_ports hdmi_data_e] -connect_bd_net -net axi_hdmi_tx_1_hdmi_data [get_bd_pins axi_hdmi_core/hdmi_24_data] [get_bd_ports hdmi_data] -connect_bd_net -net axi_hdmi_tx_1_mm2s_tvalid [get_bd_pins axi_hdmi_core/m_axis_mm2s_tvalid] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tvalid] -connect_bd_net -net axi_hdmi_tx_1_mm2s_tdata [get_bd_pins axi_hdmi_core/m_axis_mm2s_tdata] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tdata] -connect_bd_net -net axi_hdmi_tx_1_mm2s_tkeep [get_bd_pins axi_hdmi_core/m_axis_mm2s_tkeep] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tkeep] -connect_bd_net -net axi_hdmi_tx_1_mm2s_tlast [get_bd_pins axi_hdmi_core/m_axis_mm2s_tlast] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tlast] -connect_bd_net -net axi_hdmi_tx_1_mm2s_tready [get_bd_pins axi_hdmi_core/m_axis_mm2s_tready] [get_bd_pins axi_hdmi_dma/m_axis_mm2s_tready] -connect_bd_net -net axi_hdmi_tx_1_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync] [get_bd_pins axi_hdmi_dma/mm2s_fsync] -connect_bd_net -net axi_hdmi_tx_1_mm2s_fsync [get_bd_pins axi_hdmi_core/m_axis_mm2s_fsync_ret] - -connect_bd_net -net xlconcat_din_1 [get_bd_pins xlconcat_1/In1] [get_bd_ports hdmi_int] -connect_bd_net -net xlconcat_din_2 [get_bd_pins xlconcat_1/In2] [get_bd_pins axi_hdmi_dma/mm2s_introut] - -# Ultrasound - -connect_bd_intf_net -intf_net axi_interconnect_1_m04_axi [get_bd_intf_pins axi_interconnect_1/M04_AXI] [get_bd_intf_pins axi_usdrx1_gt/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m05_axi [get_bd_intf_pins axi_interconnect_1/M05_AXI] [get_bd_intf_pins axi_usdrx1_jesd/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m06_axi [get_bd_intf_pins axi_interconnect_1/M06_AXI] [get_bd_intf_pins axi_ad9671_core_0/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m07_axi [get_bd_intf_pins axi_interconnect_1/M07_AXI] [get_bd_intf_pins axi_ad9671_core_1/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m08_axi [get_bd_intf_pins axi_interconnect_1/M08_AXI] [get_bd_intf_pins axi_ad9671_core_2/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m09_axi [get_bd_intf_pins axi_interconnect_1/M09_AXI] [get_bd_intf_pins axi_ad9671_core_3/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m10_axi [get_bd_intf_pins axi_interconnect_1/M10_AXI] [get_bd_intf_pins axi_usdrx1_dma/s_axi] -connect_bd_intf_net -intf_net axi_interconnect_1_m11_axi [get_bd_intf_pins axi_interconnect_1/M11_AXI] [get_bd_intf_pins axi_usdrx1_spi/axi_lite] - -connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_gt/m_axi] -connect_bd_intf_net -intf_net axi_usdrx1_gt_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_gt_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP2] -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_s00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/S00_AXI] [get_bd_intf_pins axi_usdrx1_dma/m_dest_axi] -connect_bd_intf_net -intf_net axi_usdrx1_dma_interconnect_m00_axi [get_bd_intf_pins axi_usdrx1_dma_interconnect/M00_AXI] [get_bd_intf_pins processing_system7_1/S_AXI_HP3] - -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M04_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M05_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M06_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M07_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M08_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M09_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M10_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_interconnect_1/M11_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK0] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins processing_system7_1/S_AXI_HP2_ACLK] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/m_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_gt/drp_clk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_jesd/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_0/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_1/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_2/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_ad9671_core_3/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_dma/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_spi/s_axi_aclk] -connect_bd_net -net processing_system7_1_fclk_clk0 [get_bd_pins axi_usdrx1_spi/ext_spi_clk] - -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2] -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/S00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2] -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma_interconnect/M00_ACLK] [get_bd_pins processing_system7_1/FCLK_CLK2] -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins processing_system7_1/S_AXI_HP3_ACLK] -connect_bd_net -net processing_system7_1_fclk_clk2 [get_bd_pins axi_usdrx1_dma/m_dest_axi_aclk] - -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M04_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M05_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M06_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M07_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M08_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M09_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M10_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_interconnect_1/M11_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET0_N] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_gt/m_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_jesd/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_0/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_1/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_2/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_ad9671_core_3/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_dma/s_axi_aresetn] -connect_bd_net -net processing_system7_1_fclk_reset0_n [get_bd_pins axi_usdrx1_spi/s_axi_aresetn] - -connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N] -connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/S00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N] -connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma_interconnect/M00_ARESETN] [get_bd_pins processing_system7_1/FCLK_RESET2_N] -connect_bd_net -net processing_system7_1_fclk_reset2_n [get_bd_pins axi_usdrx1_dma/m_dest_axi_aresetn] - -connect_bd_net -net xlconcat_din_3 [get_bd_pins xlconcat_1/In3] [get_bd_pins axi_usdrx1_dma/irq] -connect_bd_net -net xlconcat_din_4 [get_bd_pins xlconcat_1/In4] [get_bd_pins axi_usdrx1_spi/ip2intc_irpt] - -connect_bd_net -net axi_ad9671_core_adc_clk [get_bd_pins axi_ad9671_core_0/adc_clk] [get_bd_pins axi_usdrx1_dma/fifo_wr_clk] -connect_bd_net -net axi_ad9671_core_0_adc_dwr [get_bd_pins axi_ad9671_core_0/adc_dwr] [get_bd_pins dma_concat_wr/In0] -connect_bd_net -net axi_ad9671_core_1_adc_dwr [get_bd_pins axi_ad9671_core_1/adc_dwr] [get_bd_pins dma_concat_wr/In1] -connect_bd_net -net axi_ad9671_core_2_adc_dwr [get_bd_pins axi_ad9671_core_2/adc_dwr] [get_bd_pins dma_concat_wr/In2] -connect_bd_net -net axi_ad9671_core_3_adc_dwr [get_bd_pins axi_ad9671_core_3/adc_dwr] [get_bd_pins dma_concat_wr/In3] -connect_bd_net -net axi_ad9671_core_0_adc_dsync [get_bd_pins axi_ad9671_core_0/adc_dsync] [get_bd_pins dma_concat_sync/In0] -connect_bd_net -net axi_ad9671_core_1_adc_dsync [get_bd_pins axi_ad9671_core_1/adc_dsync] [get_bd_pins dma_concat_sync/In1] -connect_bd_net -net axi_ad9671_core_2_adc_dsync [get_bd_pins axi_ad9671_core_2/adc_dsync] [get_bd_pins dma_concat_sync/In2] -connect_bd_net -net axi_ad9671_core_3_adc_dsync [get_bd_pins axi_ad9671_core_3/adc_dsync] [get_bd_pins dma_concat_sync/In3] -connect_bd_net -net axi_ad9671_core_0_adc_ddata [get_bd_pins axi_ad9671_core_0/adc_ddata] [get_bd_pins dma_concat_data/In0] -connect_bd_net -net axi_ad9671_core_1_adc_ddata [get_bd_pins axi_ad9671_core_1/adc_ddata] [get_bd_pins dma_concat_data/In1] -connect_bd_net -net axi_ad9671_core_2_adc_ddata [get_bd_pins axi_ad9671_core_2/adc_ddata] [get_bd_pins dma_concat_data/In2] -connect_bd_net -net axi_ad9671_core_3_adc_ddata [get_bd_pins axi_ad9671_core_3/adc_ddata] [get_bd_pins dma_concat_data/In3] -connect_bd_net -net dma_concat_wr_dout [get_bd_pins dma_concat_wr/dout] [get_bd_pins dma_concat_wr_or/Op1] -connect_bd_net -net dma_concat_sync_dout [get_bd_pins dma_concat_sync/dout] [get_bd_pins dma_concat_sync_or/Op1] -connect_bd_net -net dma_concat_wr_or_res [get_bd_pins dma_concat_wr_or/Res] [get_bd_pins axi_usdrx1_dma/fifo_wr_en] -connect_bd_net -net dma_concat_sync_or_res [get_bd_pins dma_concat_sync_or/Res] [get_bd_pins axi_usdrx1_dma/fifo_wr_sync] -connect_bd_net -net dma_concat_wr_adc_ddata [get_bd_pins dma_concat_data/dout] [get_bd_pins axi_usdrx1_dma/fifo_wr_din] -connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_usdrx1_dma/fifo_wr_overflow] -connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_0/adc_dovf] -connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_1/adc_dovf] -connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_2/adc_dovf] -connect_bd_net -net axi_ad9671_adc_dovf [get_bd_pins axi_ad9671_core_3/adc_dovf] - -connect_bd_net -net axi_usdrx1_gt_rx_rst [get_bd_pins axi_usdrx1_gt/rx_rst] [get_bd_pins axi_usdrx1_jesd/rx_reset] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_usdrx1_gt/rx_clk] [get_bd_pins axi_usdrx1_jesd/rx_core_clk] -connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_pins axi_usdrx1_gt/rx_sysref] [get_bd_pins axi_usdrx1_jesd/rx_sysref] -connect_bd_net -net axi_usdrx1_gt_rx_gt_charisk [get_bd_pins axi_usdrx1_gt/rx_gt_charisk] [get_bd_pins axi_usdrx1_jesd/gt_rxcharisk_in] -connect_bd_net -net axi_usdrx1_gt_rx_gt_disperr [get_bd_pins axi_usdrx1_gt/rx_gt_disperr] [get_bd_pins axi_usdrx1_jesd/gt_rxdisperr_in] -connect_bd_net -net axi_usdrx1_gt_rx_gt_notintable [get_bd_pins axi_usdrx1_gt/rx_gt_notintable] [get_bd_pins axi_usdrx1_jesd/gt_rxnotintable_in] -connect_bd_net -net axi_usdrx1_gt_rx_gt_data [get_bd_pins axi_usdrx1_gt/rx_gt_data] [get_bd_pins axi_usdrx1_jesd/gt_rxdata_in] -connect_bd_net -net axi_usdrx1_gt_rx_rst_done [get_bd_pins axi_usdrx1_gt/rx_rst_done] [get_bd_pins axi_usdrx1_jesd/rx_reset_done] -connect_bd_net -net axi_usdrx1_gt_rx_ip_comma_align [get_bd_pins axi_usdrx1_gt/rx_ip_comma_align] [get_bd_pins axi_usdrx1_jesd/rxencommaalign_out] -connect_bd_net -net axi_usdrx1_gt_rx_ip_sync [get_bd_pins axi_usdrx1_gt/rx_ip_sync] [get_bd_pins axi_usdrx1_jesd/rx_sync] -connect_bd_net -net axi_usdrx1_gt_rx_ip_sof [get_bd_pins axi_usdrx1_gt/rx_ip_sof] [get_bd_pins axi_usdrx1_jesd/rx_start_of_frame] -connect_bd_net -net axi_usdrx1_gt_rx_ip_data [get_bd_pins axi_usdrx1_gt/rx_ip_data] [get_bd_pins axi_usdrx1_jesd/rx_tdata] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_0/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_1/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_2/rx_clk] -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins axi_ad9671_core_3/rx_clk] - -connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins axi_usdrx1_gt/rx_data] -connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_0/Din] -connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_1/Din] -connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_2/Din] -connect_bd_net -net axi_usdrx1_gt_rx_data [get_bd_pins gt_slice_data_3/Din] -connect_bd_net -net gt_slice_data_0_dout [get_bd_pins axi_ad9671_core_0/rx_data] [get_bd_pins gt_slice_data_0/Dout] -connect_bd_net -net gt_slice_data_1_dout [get_bd_pins axi_ad9671_core_1/rx_data] [get_bd_pins gt_slice_data_1/Dout] -connect_bd_net -net gt_slice_data_2_dout [get_bd_pins axi_ad9671_core_2/rx_data] [get_bd_pins gt_slice_data_2/Dout] -connect_bd_net -net gt_slice_data_3_dout [get_bd_pins axi_ad9671_core_3/rx_data] [get_bd_pins gt_slice_data_3/Dout] - -connect_bd_net -net axi_usdrx1_gt_ref_clk_q [get_bd_pins axi_usdrx1_gt/ref_clk_q] [get_bd_ports rx_ref_clk] -connect_bd_net -net axi_usdrx1_gt_rx_data_p [get_bd_pins axi_usdrx1_gt/rx_data_p] [get_bd_ports rx_data_p] -connect_bd_net -net axi_usdrx1_gt_rx_data_n [get_bd_pins axi_usdrx1_gt/rx_data_n] [get_bd_ports rx_data_n] -connect_bd_net -net axi_usdrx1_gt_rx_sync [get_bd_pins axi_usdrx1_gt/rx_sync] [get_bd_ports rx_sync] -connect_bd_net -net axi_usdrx1_gt_rx_sysref [get_bd_ports rx_sysref] - -connect_bd_net -net axi_spi_1_csn_i [get_bd_ports spi_csn_i] [get_bd_pins axi_usdrx1_spi/ss_i] -connect_bd_net -net axi_spi_1_csn_o [get_bd_ports spi_csn_o] [get_bd_pins axi_usdrx1_spi/ss_o] -connect_bd_net -net axi_spi_1_clk_i [get_bd_ports spi_clk_i] [get_bd_pins axi_usdrx1_spi/sck_i] -connect_bd_net -net axi_spi_1_clk_o [get_bd_ports spi_clk_o] [get_bd_pins axi_usdrx1_spi/sck_o] -connect_bd_net -net axi_spi_1_sdo_i [get_bd_ports spi_sdo_i] [get_bd_pins axi_usdrx1_spi/io0_i] -connect_bd_net -net axi_spi_1_sdo_o [get_bd_ports spi_sdo_o] [get_bd_pins axi_usdrx1_spi/io0_o] -connect_bd_net -net axi_spi_1_sdi_i [get_bd_ports spi_sdi_i] [get_bd_pins axi_usdrx1_spi/io1_i] - -# ila - -connect_bd_net -net axi_usdrx1_gt_rx_clk [get_bd_pins ila_jesd_rx_mon/CLK] -connect_bd_net -net axi_usdrx1_gt_rx_mon_data [get_bd_pins axi_usdrx1_gt/rx_mon_data] [get_bd_pins ila_jesd_rx_mon/PROBE0] -connect_bd_net -net axi_usdrx1_gt_rx_mon_trigger [get_bd_pins axi_usdrx1_gt/rx_mon_trigger] [get_bd_pins ila_jesd_rx_mon/PROBE1] - -# address map - -create_bd_addr_seg -range 0x00010000 -offset 0x40800000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_iic_1/s_axi/Reg] SEG_data_iic_1 - -create_bd_addr_seg -range 0x00010000 -offset 0x44a20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_clkgen/s_axi/axi_lite] SEG_data_hdmi_clkgen -create_bd_addr_seg -range 0x00010000 -offset 0x44a80000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_dma/S_AXI_LITE/Reg] SEG_data_hdmi_dma -create_bd_addr_seg -range 0x00010000 -offset 0x44a50000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_hdmi_core/s_axi/axi_lite] SEG_data_hdmi_core - -create_bd_addr_seg -range 0x00010000 -offset 0x43c70000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_gt/s_axi/axi_lite] SEG_data_usdrx1_gt -create_bd_addr_seg -range 0x00001000 -offset 0x43c80000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_jesd/s_axi/Reg] SEG_data_usdrx1_jesd -create_bd_addr_seg -range 0x00010000 -offset 0x43c00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_0/s_axi/axi_lite] SEG_data_ad9671_core_0 -create_bd_addr_seg -range 0x00010000 -offset 0x43c10000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_1/s_axi/axi_lite] SEG_data_ad9671_core_1 -create_bd_addr_seg -range 0x00010000 -offset 0x43c20000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_2/s_axi/axi_lite] SEG_data_ad9671_core_2 -create_bd_addr_seg -range 0x00010000 -offset 0x43c30000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_ad9671_core_3/s_axi/axi_lite] SEG_data_ad9671_core_3 -create_bd_addr_seg -range 0x00010000 -offset 0x43c40000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_dma/s_axi/axi_lite] SEG_data_usdrx1_dma -create_bd_addr_seg -range 0x00010000 -offset 0x41e00000 [get_bd_addr_spaces processing_system7_1/Data] [get_bd_addr_segs axi_usdrx1_spi/axi_lite/Reg] SEG_data_usdrx1_spi - -create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_hdmi_dma/Data_MM2S] [get_bd_addr_segs processing_system7_1/S_AXI_HP0/HP0_DDR_LOWOCM] SEG_processing_system7_1_HP0_DDR_LOWOCM -create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_dma/m_dest_axi] [get_bd_addr_segs processing_system7_1/S_AXI_HP3/HP3_DDR_LOWOCM] SEG_processing_system7_1_HP3_DDR_LOWOCM -create_bd_addr_seg -range 0x40000000 -offset 0x00000000 [get_bd_addr_spaces axi_usdrx1_gt/m_axi] [get_bd_addr_segs processing_system7_1/S_AXI_HP2/HP2_DDR_LOWOCM] SEG_processing_system7_1_HP2_DDR_LOWOCM +source $ad_hdl_dir/projects/common/zc706/zc706_system_bd.tcl +source ../common/usdrx1_bd.tcl diff --git a/projects/usdrx1/zc706/system_constr.xdc b/projects/usdrx1/zc706/system_constr.xdc index 5c2d5f917..97392c994 100755 --- a/projects/usdrx1/zc706/system_constr.xdc +++ b/projects/usdrx1/zc706/system_constr.xdc @@ -1,62 +1,5 @@ # constraints -# hdmi - -set_property -dict {PACKAGE_PIN P28 IOSTANDARD LVCMOS25} [get_ports hdmi_out_clk] -set_property -dict {PACKAGE_PIN U21 IOSTANDARD LVCMOS25} [get_ports hdmi_vsync] -set_property -dict {PACKAGE_PIN R22 IOSTANDARD LVCMOS25} [get_ports hdmi_hsync] -set_property -dict {PACKAGE_PIN V24 IOSTANDARD LVCMOS25} [get_ports hdmi_data_e] -set_property -dict {PACKAGE_PIN U24 IOSTANDARD LVCMOS25} [get_ports hdmi_data[0]] -set_property -dict {PACKAGE_PIN T22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[1]] -set_property -dict {PACKAGE_PIN R23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[2]] -set_property -dict {PACKAGE_PIN AA25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[3]] -set_property -dict {PACKAGE_PIN AE28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[4]] -set_property -dict {PACKAGE_PIN T23 IOSTANDARD LVCMOS25} [get_ports hdmi_data[5]] -set_property -dict {PACKAGE_PIN AB25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[6]] -set_property -dict {PACKAGE_PIN T27 IOSTANDARD LVCMOS25} [get_ports hdmi_data[7]] -set_property -dict {PACKAGE_PIN AD26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[8]] -set_property -dict {PACKAGE_PIN AB26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[9]] -set_property -dict {PACKAGE_PIN AA28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[10]] -set_property -dict {PACKAGE_PIN AC26 IOSTANDARD LVCMOS25} [get_ports hdmi_data[11]] -set_property -dict {PACKAGE_PIN AE30 IOSTANDARD LVCMOS25} [get_ports hdmi_data[12]] -set_property -dict {PACKAGE_PIN Y25 IOSTANDARD LVCMOS25} [get_ports hdmi_data[13]] -set_property -dict {PACKAGE_PIN AA29 IOSTANDARD LVCMOS25} [get_ports hdmi_data[14]] -set_property -dict {PACKAGE_PIN AD30 IOSTANDARD LVCMOS25} [get_ports hdmi_data[15]] -set_property -dict {PACKAGE_PIN Y28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[16]] -set_property -dict {PACKAGE_PIN AF28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[17]] -set_property -dict {PACKAGE_PIN V22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[18]] -set_property -dict {PACKAGE_PIN AA27 IOSTANDARD LVCMOS25} [get_ports hdmi_data[19]] -set_property -dict {PACKAGE_PIN U22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[20]] -set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS25} [get_ports hdmi_data[21]] -set_property -dict {PACKAGE_PIN V21 IOSTANDARD LVCMOS25} [get_ports hdmi_data[22]] -set_property -dict {PACKAGE_PIN AC22 IOSTANDARD LVCMOS25} [get_ports hdmi_data[23]] -set_property -dict {PACKAGE_PIN AC23 IOSTANDARD LVCMOS25} [get_ports hdmi_int] - -# iic - -set_property -dict {PACKAGE_PIN AJ14 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_scl] -set_property -dict {PACKAGE_PIN AJ18 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports iic_sda] - -# gpio (switches, leds and such) - -set_property -dict {PACKAGE_PIN AB17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[0]] ; ## GPIO_DIP_SW0 -set_property -dict {PACKAGE_PIN AC16 IOSTANDARD LVCMOS25} [get_ports gpio_bd[1]] ; ## GPIO_DIP_SW1 -set_property -dict {PACKAGE_PIN AC17 IOSTANDARD LVCMOS25} [get_ports gpio_bd[2]] ; ## GPIO_DIP_SW2 -set_property -dict {PACKAGE_PIN AJ13 IOSTANDARD LVCMOS25} [get_ports gpio_bd[3]] ; ## GPIO_DIP_SW3 -set_property -dict {PACKAGE_PIN AK25 IOSTANDARD LVCMOS25} [get_ports gpio_bd[4]] ; ## GPIO_SW_LEFT -set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[5]] ; ## GPIO_SW_CENTER -set_property -dict {PACKAGE_PIN R27 IOSTANDARD LVCMOS25} [get_ports gpio_bd[6]] ; ## GPIO_SW_RIGHT - -set_property -dict {PACKAGE_PIN Y21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[7]] ; ## GPIO_LED_LEFT -set_property -dict {PACKAGE_PIN G2 IOSTANDARD LVCMOS15} [get_ports gpio_bd[8]] ; ## GPIO_LED_CENTER -set_property -dict {PACKAGE_PIN W21 IOSTANDARD LVCMOS25} [get_ports gpio_bd[9]] ; ## GPIO_LED_RIGHT -set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVCMOS15} [get_ports gpio_bd[10]] ; ## GPIO_LED_0 - -set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[11]] ; ## XADC_GPIO_0 -set_property -dict {PACKAGE_PIN J15 IOSTANDARD LVCMOS15} [get_ports gpio_bd[12]] ; ## XADC_GPIO_1 -set_property -dict {PACKAGE_PIN J16 IOSTANDARD LVCMOS15} [get_ports gpio_bd[13]] ; ## XADC_GPIO_2 -set_property -dict {PACKAGE_PIN J14 IOSTANDARD LVCMOS15} [get_ports gpio_bd[14]] ; ## XADC_GPIO_3 - # ultrasound set_property -dict {PACKAGE_PIN AD10} [get_ports rx_ref_clk_p] ; ## D04 FMC_HPC_GBTCLK0_M2C_P @@ -138,17 +81,17 @@ set_property -dict {PACKAGE_PIN AK17 IOSTANDARD LVCMOS25} [get_ports dac_data # clocks -create_clock -name cpu_clk -period 10.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK0] -create_clock -name m200_clk -period 5.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK1] -create_clock -name dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK2] -create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/processing_system7_1/FCLK_CLK3] -create_clock -name hdmi_clk -period 6.73 [get_nets i_system_wrapper/system_i/axi_clkgen_1/inst/i_mmcm_drp/mmcm_clk_0_s] - create_clock -name rx_ref_clk -period 12.50 [get_ports rx_ref_clk_p] create_clock -name rx_div_clk -period 12.50 [get_nets i_system_wrapper/system_i/axi_usdrx1_gt_rx_clk] +create_clock -name fmc_dma_clk -period 5.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK2] +create_clock -name mlo_clk -period 25.00 [get_pins i_system_wrapper/system_i/sys_ps7/FCLK_CLK3] -set_clock_groups -asynchronous -group {cpu_clk} -set_clock_groups -asynchronous -group {dma_clk} -set_clock_groups -asynchronous -group {hdmi_clk} set_clock_groups -asynchronous -group {rx_div_clk} +set_clock_groups -asynchronous -group {fmc_dma_clk} +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_drp_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_pll_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_gt_tx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_rx_rst_reg/i_rst_reg/PRE] +set_false_path -through [get_pins i_system_wrapper/system_i/axi_usdrx1_gt/inst/i_up_gt/i_tx_rst_reg/i_rst_reg/PRE] diff --git a/projects/usdrx1/zc706/system_project.tcl b/projects/usdrx1/zc706/system_project.tcl index d9f09ba49..1a01c2578 100755 --- a/projects/usdrx1/zc706/system_project.tcl +++ b/projects/usdrx1/zc706/system_project.tcl @@ -1,35 +1,16 @@ -create_project ad_usdrx1_zc706 . -part xc7z045ffg900-2 -force -set_property board xilinx.com:zynq:zc706:1.1 [current_project] -set_property ip_repo_paths ../../../library [current_fileset] -update_ip_catalog -create_bd_design "system" -source system_bd.tcl +source ../../scripts/adi_env.tcl +source $ad_hdl_dir/projects/scripts/adi_project.tcl -generate_target {synthesis implementation} \ - [get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd] +adi_project_create usdrx1_zc706 +adi_project_files usdrx1_zc706 [list \ + "system_top.v" \ + "system_constr.xdc" \ + "../common/usdrx1_spi.v" \ + "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ] -make_wrapper -files [get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd] -top -import_files -force -norecurse -fileset sources_1 ./ad_usdrx1_zc706.srcs/sources_1/bd/system/hdl/system_wrapper.v -add_files -norecurse -fileset sources_1 ../../../library/misc/usdrx1_spi.v -add_files -norecurse -fileset sources_1 system_top.v -add_files -norecurse -fileset constrs_1 system_constr.xdc - -set_property top system_top [current_fileset] - -launch_runs synth_1 -wait_on_run synth_1 -open_run synth_1 -report_timing_summary -file report_timing_summary_synth_1.log - -launch_runs impl_1 -to_step write_bitstream -wait_on_run impl_1 -open_run impl_1 -report_timing_summary -file report_timing_summary_impl_1.log - -export_hardware [get_files ./ad_usdrx1_zc706.srcs/sources_1/bd/system/system.bd] \ - [get_runs impl_1] -bitstream +adi_project_run usdrx1_zc706 diff --git a/projects/usdrx1/zc706/system_top.v b/projects/usdrx1/zc706/system_top.v index 1db6b8d5f..6979d7c62 100755 --- a/projects/usdrx1/zc706/system_top.v +++ b/projects/usdrx1/zc706/system_top.v @@ -71,19 +71,20 @@ module system_top ( hdmi_hsync, hdmi_data_e, hdmi_data, - hdmi_int, + + spdif, iic_scl, iic_sda, rx_ref_clk_p, rx_ref_clk_n, - rx_data_p, - rx_data_n, rx_sysref_p, rx_sysref_n, rx_sync_p, rx_sync_n, + rx_data_p, + rx_data_n, spi_fout_enb_clk, spi_fout_enb_mlo, @@ -150,19 +151,20 @@ module system_top ( output hdmi_hsync; output hdmi_data_e; output [23:0] hdmi_data; - input hdmi_int; + + output spdif; inout iic_scl; inout iic_sda; input rx_ref_clk_p; input rx_ref_clk_n; - input [ 7:0] rx_data_p; - input [ 7:0] rx_data_n; output rx_sysref_p; output rx_sysref_n; output rx_sync_p; output rx_sync_n; + input [ 7:0] rx_data_p; + input [ 7:0] rx_data_n; output spi_fout_enb_clk; output spi_fout_enb_mlo; @@ -211,6 +213,32 @@ module system_top ( wire rx_sync; wire [ 1:0] gpio_open; + wire [511:0] adc_ddata; + wire [127:0] adc_ddata_0; + wire [127:0] adc_ddata_1; + wire [127:0] adc_ddata_2; + wire [127:0] adc_ddata_3; + wire adc_dovf; + wire adc_dovf_0; + wire adc_dovf_1; + wire adc_dovf_2; + wire adc_dovf_3; + wire adc_dsync; + wire adc_dsync_0; + wire adc_dsync_1; + wire adc_dsync_2; + wire adc_dsync_3; + wire adc_dwr; + wire adc_dwr_0; + wire adc_dwr_1; + wire adc_dwr_2; + wire adc_dwr_3; + wire [255:0] gt_rx_data; + wire [63:0] gt_rx_data_0; + wire [63:0] gt_rx_data_1; + wire [63:0] gt_rx_data_2; + wire [63:0] gt_rx_data_3; + // spi assignments assign spi_fout_enb_clk = spi_csn[10:10]; @@ -226,6 +254,22 @@ module system_top ( assign spi_afe_clk = spi_clk; assign spi_clk_clk = spi_clk; + // single dma for all channels + + assign gt_rx_data_3 = gt_rx_data[255:192]; + assign gt_rx_data_2 = gt_rx_data[191:128]; + assign gt_rx_data_1 = gt_rx_data[127: 64]; + assign gt_rx_data_0 = gt_rx_data[ 63: 0]; + + assign adc_dwr = adc_dwr_3 | adc_dwr_2 | adc_dwr_1 | adc_dwr_0; + assign adc_dsync = adc_dsync_3 | adc_dsync_2 | adc_dsync_1 | adc_dsync_0; + assign adc_ddata = {adc_ddata_3, adc_ddata_2, adc_ddata_1, adc_ddata_0}; + + assign adc_dovf_0 = adc_dovf; + assign adc_dovf_1 = adc_dovf; + assign adc_dovf_2 = adc_dovf; + assign adc_dovf_3 = adc_dovf; + // instantiations IBUFDS_GTE2 i_ibufds_rx_ref_clk ( @@ -380,10 +424,34 @@ module system_top ( .GPIO_I (gpio_i), .GPIO_O (gpio_o), .GPIO_T (gpio_t), + .adc_ddata (adc_ddata), + .adc_ddata_0 (adc_ddata_0), + .adc_ddata_1 (adc_ddata_1), + .adc_ddata_2 (adc_ddata_2), + .adc_ddata_3 (adc_ddata_3), + .adc_dovf (adc_dovf), + .adc_dovf_0 (adc_dovf_0), + .adc_dovf_1 (adc_dovf_1), + .adc_dovf_2 (adc_dovf_2), + .adc_dovf_3 (adc_dovf_3), + .adc_dsync (adc_dsync), + .adc_dsync_0 (adc_dsync_0), + .adc_dsync_1 (adc_dsync_1), + .adc_dsync_2 (adc_dsync_2), + .adc_dsync_3 (adc_dsync_3), + .adc_dwr (adc_dwr), + .adc_dwr_0 (adc_dwr_0), + .adc_dwr_1 (adc_dwr_1), + .adc_dwr_2 (adc_dwr_2), + .adc_dwr_3 (adc_dwr_3), + .gt_rx_data (gt_rx_data), + .gt_rx_data_0 (gt_rx_data_0), + .gt_rx_data_1 (gt_rx_data_1), + .gt_rx_data_2 (gt_rx_data_2), + .gt_rx_data_3 (gt_rx_data_3), .hdmi_data (hdmi_data), .hdmi_data_e (hdmi_data_e), .hdmi_hsync (hdmi_hsync), - .hdmi_int (hdmi_int), .hdmi_out_clk (hdmi_out_clk), .hdmi_vsync (hdmi_vsync), .iic_main_scl_io (iic_scl), @@ -394,6 +462,7 @@ module system_top ( .rx_ref_clk (rx_ref_clk), .rx_sync (rx_sync), .rx_sysref (rx_sysref), + .spdif (spdif), .spi_clk_i (spi_clk), .spi_clk_o (spi_clk), .spi_csn_i (spi_csn),