ATofan
parent
e597467447
commit
9676146725
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@ -0,0 +1,4 @@
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source $ad_hdl_dir/projects/common/ac701/ac701_system_bd.tcl
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source ../common/fmcomms2_bd.tcl
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@ -0,0 +1,67 @@
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# constraints
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# ad9361
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set_property -dict {PACKAGE_PIN D18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_p] ; ## G6 FMC_LPC_LA00_CC_P
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set_property -dict {PACKAGE_PIN C18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_clk_in_n] ; ## G7 FMC_LPC_LA00_CC_N
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set_property -dict {PACKAGE_PIN E17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_p] ; ## D8 FMC_LPC_LA01_CC_P
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set_property -dict {PACKAGE_PIN E18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_frame_in_n] ; ## D9 FMC_LPC_LA01_CC_N
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set_property -dict {PACKAGE_PIN H14 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[0]] ; ## H7 FMC_LPC_LA02_P
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set_property -dict {PACKAGE_PIN H15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[0]] ; ## H8 FMC_LPC_LA02_N
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set_property -dict {PACKAGE_PIN G17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[1]] ; ## G9 FMC_LPC_LA03_P
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set_property -dict {PACKAGE_PIN F17 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[1]] ; ## G10 FMC_LPC_LA03_N
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set_property -dict {PACKAGE_PIN F18 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[2]] ; ## H10 FMC_LPC_LA04_P
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set_property -dict {PACKAGE_PIN F19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[2]] ; ## H11 FMC_LPC_LA04_N
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set_property -dict {PACKAGE_PIN G15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[3]] ; ## D11 FMC_LPC_LA05_P
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set_property -dict {PACKAGE_PIN F15 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[3]] ; ## D12 FMC_LPC_LA05_N
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set_property -dict {PACKAGE_PIN G19 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[4]] ; ## C10 FMC_LPC_LA06_P
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set_property -dict {PACKAGE_PIN F20 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[4]] ; ## C11 FMC_LPC_LA06_N
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set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_p[5]] ; ## H13 FMC_LPC_LA07_P
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set_property -dict {PACKAGE_PIN G16 IOSTANDARD LVDS_25 DIFF_TERM TRUE} [get_ports rx_data_in_n[5]] ; ## H14 FMC_LPC_LA07_N
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set_property -dict {PACKAGE_PIN C17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_p] ; ## G12 FMC_LPC_LA08_P
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set_property -dict {PACKAGE_PIN B17 IOSTANDARD LVDS_25} [get_ports tx_clk_out_n] ; ## G13 FMC_LPC_LA08_N
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set_property -dict {PACKAGE_PIN E16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_p] ; ## D14 FMC_LPC_LA09_P
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set_property -dict {PACKAGE_PIN D16 IOSTANDARD LVDS_25} [get_ports tx_frame_out_n] ; ## D15 FMC_LPC_LA09_N
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set_property -dict {PACKAGE_PIN B19 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[0]] ; ## H16 FMC_LPC_LA11_P
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set_property -dict {PACKAGE_PIN A19 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[0]] ; ## H17 FMC_LPC_LA11_N
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set_property -dict {PACKAGE_PIN E20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[1]] ; ## G15 FMC_LPC_LA12_P
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set_property -dict {PACKAGE_PIN D20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[1]] ; ## G16 FMC_LPC_LA12_N
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set_property -dict {PACKAGE_PIN B20 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[2]] ; ## D17 FMC_LPC_LA13_P
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set_property -dict {PACKAGE_PIN A20 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[2]] ; ## D18 FMC_LPC_LA13_N
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set_property -dict {PACKAGE_PIN A17 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[3]] ; ## C14 FMC_LPC_LA10_P
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set_property -dict {PACKAGE_PIN A18 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[3]] ; ## C15 FMC_LPC_LA10_N
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set_property -dict {PACKAGE_PIN C21 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[4]] ; ## C18 FMC_LPC_LA14_P
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set_property -dict {PACKAGE_PIN B21 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[4]] ; ## C19 FMC_LPC_LA14_N
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set_property -dict {PACKAGE_PIN B22 IOSTANDARD LVDS_25} [get_ports tx_data_out_p[5]] ; ## H19 FMC_LPC_LA15_P
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set_property -dict {PACKAGE_PIN A22 IOSTANDARD LVDS_25} [get_ports tx_data_out_n[5]] ; ## H20 FMC_LPC_LA15_N
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set_property -dict {PACKAGE_PIN M16 IOSTANDARD LVCMOS25} [get_ports gpio_status[0]] ; ## G21 FMC_LPC_LA20_P
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set_property -dict {PACKAGE_PIN M17 IOSTANDARD LVCMOS25} [get_ports gpio_status[1]] ; ## G22 FMC_LPC_LA20_N
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set_property -dict {PACKAGE_PIN J19 IOSTANDARD LVCMOS25} [get_ports gpio_status[2]] ; ## H25 FMC_LPC_LA21_P
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set_property -dict {PACKAGE_PIN H19 IOSTANDARD LVCMOS25} [get_ports gpio_status[3]] ; ## H26 FMC_LPC_LA21_N
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set_property -dict {PACKAGE_PIN L17 IOSTANDARD LVCMOS25} [get_ports gpio_status[4]] ; ## G24 FMC_LPC_LA22_P
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set_property -dict {PACKAGE_PIN L18 IOSTANDARD LVCMOS25} [get_ports gpio_status[5]] ; ## G25 FMC_LPC_LA22_N
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set_property -dict {PACKAGE_PIN K20 IOSTANDARD LVCMOS25} [get_ports gpio_status[6]] ; ## D23 FMC_LPC_LA23_P
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set_property -dict {PACKAGE_PIN J20 IOSTANDARD LVCMOS25} [get_ports gpio_status[7]] ; ## D24 FMC_LPC_LA23_N
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set_property -dict {PACKAGE_PIN J18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[0]] ; ## H28 FMC_LPC_LA24_P
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set_property -dict {PACKAGE_PIN H18 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[1]] ; ## H29 FMC_LPC_LA24_N
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set_property -dict {PACKAGE_PIN G22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[2]] ; ## G27 FMC_LPC_LA25_P
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set_property -dict {PACKAGE_PIN F22 IOSTANDARD LVCMOS25} [get_ports gpio_ctl[3]] ; ## G28 FMC_LPC_LA25_N
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set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS25} [get_ports gpio_en_agc] ; ## H22 FMC_LPC_LA19_P
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set_property -dict {PACKAGE_PIN L14 IOSTANDARD LVCMOS25} [get_ports gpio_sync] ; ## H23 FMC_LPC_LA19_N
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set_property -dict {PACKAGE_PIN K22 IOSTANDARD LVCMOS25} [get_ports gpio_resetb] ; ## H31 FMC_LPC_LA28_P
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set_property -dict {PACKAGE_PIN E21 IOSTANDARD LVCMOS25} [get_ports gpio_enable] ; ## G18 FMC_LPC_LA16_P
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set_property -dict {PACKAGE_PIN D21 IOSTANDARD LVCMOS25} [get_ports gpio_txnrx] ; ## G19 FMC_LPC_LA16_N
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set_property -dict {PACKAGE_PIN J24 IOSTANDARD LVCMOS25 PULLTYPE PULLUP} [get_ports spi_csn] ; ## D26 FMC_LPC_LA26_P
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set_property -dict {PACKAGE_PIN H24 IOSTANDARD LVCMOS25} [get_ports spi_clk] ; ## D27 FMC_LPC_LA26_N
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set_property -dict {PACKAGE_PIN F23 IOSTANDARD LVCMOS25} [get_ports spi_mosi] ; ## C26 FMC_LPC_LA27_P
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set_property -dict {PACKAGE_PIN E23 IOSTANDARD LVCMOS25} [get_ports spi_miso] ; ## C27 FMC_LPC_LA27_N
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# clocks
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create_clock -name rx_clk -period 5 [get_ports rx_clk_in_p]
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create_clock -name ad9361_clk -period 5 [get_pins i_system_wrapper/system_i/axi_ad9361/clk]
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set_clock_groups -asynchronous -group {ad9361_clk}
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source ../../scripts/adi_env.tcl
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source $ad_hdl_dir/projects/scripts/adi_project.tcl
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adi_project_create fmcomms2_ac701
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adi_project_files fmcomms2_ac701 [list \
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"system_top.v" \
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"system_constr.xdc"\
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"$ad_hdl_dir/projects/common/ac701/ac701_system_constr.xdc" ]
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adi_project_run fmcomms2_ac701
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// ***************************************************************************
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// ***************************************************************************
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// Copyright 2011(c) Analog Devices, Inc.
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//
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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// - Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// - Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in
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// the documentation and/or other materials provided with the
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// distribution.
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// - Neither the name of Analog Devices, Inc. nor the names of its
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// contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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// - The use of this software may or may not infringe the patent rights
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// of one or more patent holders. This license does not release you
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// from the requirement that you obtain separate licenses from these
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// patent holders to use this software.
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// - Use of the software either in source or binary form, must be run
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// on or directly connected to an Analog Devices Inc. component.
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//
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// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
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// PARTICULAR PURPOSE ARE DISCLAIMED.
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//
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// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
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// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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// ***************************************************************************
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`timescale 1ns/100ps
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module system_top (
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sys_rst,
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sys_clk_p,
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sys_clk_n,
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uart_sin,
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uart_sout,
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ddr3_addr,
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ddr3_ba,
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ddr3_cas_n,
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ddr3_ck_n,
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ddr3_ck_p,
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ddr3_cke,
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ddr3_cs_n,
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ddr3_dm,
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ddr3_dq,
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ddr3_dqs_n,
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ddr3_dqs_p,
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ddr3_odt,
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ddr3_ras_n,
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ddr3_reset_n,
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ddr3_we_n,
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phy_reset_n,
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phy_mdc,
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phy_mdio,
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phy_tx_clk,
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phy_tx_ctrl,
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phy_tx_data,
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phy_rx_clk,
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phy_rx_ctrl,
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phy_rx_data,
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fan_pwm,
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gpio_lcd,
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gpio_led,
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gpio_sw,
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iic_rstn,
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iic_scl,
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iic_sda,
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hdmi_out_clk,
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hdmi_hsync,
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hdmi_vsync,
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hdmi_data_e,
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hdmi_data,
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spdif,
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rx_clk_in_p,
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rx_clk_in_n,
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rx_frame_in_p,
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rx_frame_in_n,
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rx_data_in_p,
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rx_data_in_n,
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tx_clk_out_p,
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tx_clk_out_n,
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tx_frame_out_p,
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tx_frame_out_n,
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tx_data_out_p,
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tx_data_out_n,
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gpio_txnrx,
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gpio_enable,
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gpio_resetb,
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gpio_sync,
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gpio_en_agc,
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gpio_ctl,
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gpio_status,
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spi_csn,
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spi_clk,
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spi_mosi,
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spi_miso
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);
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input sys_rst;
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input sys_clk_p;
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input sys_clk_n;
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input uart_sin;
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output uart_sout;
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output [13:0] ddr3_addr;
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output [ 2:0] ddr3_ba;
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output ddr3_cas_n;
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output [ 0:0] ddr3_ck_n;
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output [ 0:0] ddr3_ck_p;
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output [ 0:0] ddr3_cke;
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output [ 0:0] ddr3_cs_n;
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output [ 7:0] ddr3_dm;
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inout [63:0] ddr3_dq;
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inout [ 7:0] ddr3_dqs_n;
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inout [ 7:0] ddr3_dqs_p;
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output [ 0:0] ddr3_odt;
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output ddr3_ras_n;
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output ddr3_reset_n;
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output ddr3_we_n;
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output phy_reset_n;
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output phy_mdc;
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inout phy_mdio;
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output phy_tx_clk;
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output phy_tx_ctrl;
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output [ 3:0] phy_tx_data;
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input phy_rx_clk;
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input phy_rx_ctrl;
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input [ 3:0] phy_rx_data;
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output fan_pwm;
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inout [ 6:0] gpio_lcd;
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inout [ 3:0] gpio_led;
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inout [ 8:0] gpio_sw;
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output iic_rstn;
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inout iic_scl;
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inout iic_sda;
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output hdmi_out_clk;
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output hdmi_hsync;
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output hdmi_vsync;
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output hdmi_data_e;
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output [23:0] hdmi_data;
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output spdif;
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input rx_clk_in_p;
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input rx_clk_in_n;
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input rx_frame_in_p;
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input rx_frame_in_n;
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input [ 5:0] rx_data_in_p;
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input [ 5:0] rx_data_in_n;
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output tx_clk_out_p;
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output tx_clk_out_n;
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output tx_frame_out_p;
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output tx_frame_out_n;
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output [ 5:0] tx_data_out_p;
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output [ 5:0] tx_data_out_n;
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inout gpio_txnrx;
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inout gpio_enable;
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inout gpio_resetb;
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inout gpio_sync;
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inout gpio_en_agc;
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inout [ 3:0] gpio_ctl;
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inout [ 7:0] gpio_status;
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output spi_csn;
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output spi_clk;
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output spi_mosi;
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input spi_miso;
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// instantiations
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// internal signals
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wire [16:0] gpio_i;
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wire [16:0] gpio_o;
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wire [16:0] gpio_t;
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|
|
||||||
|
// instantiations
|
||||||
|
|
||||||
|
IOBUF i_iobuf_gpio_txnrx (
|
||||||
|
.I (gpio_o[16]),
|
||||||
|
.O (gpio_i[16]),
|
||||||
|
.T (gpio_t[16]),
|
||||||
|
.IO (gpio_txnrx));
|
||||||
|
|
||||||
|
IOBUF i_iobuf_gpio_enable (
|
||||||
|
.I (gpio_o[15]),
|
||||||
|
.O (gpio_i[15]),
|
||||||
|
.T (gpio_t[15]),
|
||||||
|
.IO (gpio_enable));
|
||||||
|
|
||||||
|
IOBUF i_iobuf_gpio_resetb (
|
||||||
|
.I (gpio_o[14]),
|
||||||
|
.O (gpio_i[14]),
|
||||||
|
.T (gpio_t[14]),
|
||||||
|
.IO (gpio_resetb));
|
||||||
|
|
||||||
|
IOBUF i_iobuf_gpio_sync (
|
||||||
|
.I (gpio_o[13]),
|
||||||
|
.O (gpio_i[13]),
|
||||||
|
.T (gpio_t[13]),
|
||||||
|
.IO (gpio_sync));
|
||||||
|
|
||||||
|
IOBUF i_iobuf_gpio_en_agc (
|
||||||
|
.I (gpio_o[12]),
|
||||||
|
.O (gpio_i[12]),
|
||||||
|
.T (gpio_t[12]),
|
||||||
|
.IO (gpio_en_agc));
|
||||||
|
|
||||||
|
genvar n;
|
||||||
|
generate
|
||||||
|
for (n = 0; n <= 3; n = n + 1) begin: g_iobuf_gpio_ctl
|
||||||
|
IOBUF i_iobuf_gpio_ctl (
|
||||||
|
.I (gpio_o[8+n]),
|
||||||
|
.O (gpio_i[8+n]),
|
||||||
|
.T (gpio_t[8+n]),
|
||||||
|
.IO (gpio_ctl[n]));
|
||||||
|
end
|
||||||
|
for (n = 0; n <= 7; n = n + 1) begin: g_iobuf_gpio_status
|
||||||
|
IOBUF i_iobuf_gpio_status (
|
||||||
|
.I (gpio_o[0+n]),
|
||||||
|
.O (gpio_i[0+n]),
|
||||||
|
.T (gpio_t[0+n]),
|
||||||
|
.IO (gpio_status[n]));
|
||||||
|
end
|
||||||
|
|
||||||
|
endgenerate
|
||||||
|
|
||||||
|
system_wrapper i_system_wrapper (
|
||||||
|
.ddr3_addr (ddr3_addr),
|
||||||
|
.ddr3_ba (ddr3_ba),
|
||||||
|
.ddr3_cas_n (ddr3_cas_n),
|
||||||
|
.ddr3_ck_n (ddr3_ck_n),
|
||||||
|
.ddr3_ck_p (ddr3_ck_p),
|
||||||
|
.ddr3_cke (ddr3_cke),
|
||||||
|
.ddr3_cs_n (ddr3_cs_n),
|
||||||
|
.ddr3_dm (ddr3_dm),
|
||||||
|
.ddr3_dq (ddr3_dq),
|
||||||
|
.ddr3_dqs_n (ddr3_dqs_n),
|
||||||
|
.ddr3_dqs_p (ddr3_dqs_p),
|
||||||
|
.ddr3_odt (ddr3_odt),
|
||||||
|
.ddr3_ras_n (ddr3_ras_n),
|
||||||
|
.ddr3_reset_n (ddr3_reset_n),
|
||||||
|
.ddr3_we_n (ddr3_we_n),
|
||||||
|
.fan_pwm (fan_pwm),
|
||||||
|
.gpio_lcd_tri_io (gpio_lcd),
|
||||||
|
.gpio_led_tri_io (gpio_led),
|
||||||
|
.gpio_sw_tri_io (gpio_sw),
|
||||||
|
.gpio_fmcomms2_i (gpio_i),
|
||||||
|
.gpio_fmcomms2_o (gpio_o),
|
||||||
|
.gpio_fmcomms2_t (gpio_t),
|
||||||
|
.hdmi_data (hdmi_data),
|
||||||
|
.hdmi_data_e (hdmi_data_e),
|
||||||
|
.hdmi_hsync (hdmi_hsync),
|
||||||
|
.hdmi_out_clk (hdmi_out_clk),
|
||||||
|
.hdmi_vsync (hdmi_vsync),
|
||||||
|
.iic_main_scl_io (iic_scl),
|
||||||
|
.iic_main_sda_io (iic_sda),
|
||||||
|
.iic_rstn (iic_rstn),
|
||||||
|
.mdio_io (phy_mdio),
|
||||||
|
.mdio_mdc (phy_mdc),
|
||||||
|
.phy_rst_n (phy_reset_n),
|
||||||
|
.rgmii_rd (phy_rx_data),
|
||||||
|
.rgmii_rx_ctl (phy_rx_ctrl),
|
||||||
|
.rgmii_rxc (phy_rx_clk),
|
||||||
|
.rgmii_td (phy_tx_data),
|
||||||
|
.rgmii_tx_ctl (phy_tx_ctrl),
|
||||||
|
.rgmii_txc (phy_tx_clk),
|
||||||
|
.spdif (spdif),
|
||||||
|
.sys_clk_n (sys_clk_n),
|
||||||
|
.sys_clk_p (sys_clk_p),
|
||||||
|
.sys_rst (sys_rst),
|
||||||
|
.spi_csn_i (1'b1),
|
||||||
|
.spi_csn_o (spi_csn),
|
||||||
|
.spi_miso_i (spi_miso),
|
||||||
|
.spi_mosi_i (1'b0),
|
||||||
|
.spi_mosi_o (spi_mosi),
|
||||||
|
.spi_sclk_i (1'b0),
|
||||||
|
.spi_sclk_o (spi_clk),
|
||||||
|
.rx_clk_in_n (rx_clk_in_n),
|
||||||
|
.rx_clk_in_p (rx_clk_in_p),
|
||||||
|
.rx_data_in_n (rx_data_in_n),
|
||||||
|
.rx_data_in_p (rx_data_in_p),
|
||||||
|
.rx_frame_in_n (rx_frame_in_n),
|
||||||
|
.rx_frame_in_p (rx_frame_in_p),
|
||||||
|
.tx_clk_out_n (tx_clk_out_n),
|
||||||
|
.tx_clk_out_p (tx_clk_out_p),
|
||||||
|
.tx_data_out_n (tx_data_out_n),
|
||||||
|
.tx_data_out_p (tx_data_out_p),
|
||||||
|
.tx_frame_out_n (tx_frame_out_n),
|
||||||
|
.tx_frame_out_p (tx_frame_out_p),
|
||||||
|
.uart_sin (uart_sin),
|
||||||
|
.uart_sout (uart_sout),
|
||||||
|
.unc_int4 (1'b0));
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|
||||||
|
// ***************************************************************************
|
||||||
|
// ***************************************************************************
|
||||||
Loading…
Reference in New Issue