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util_upack2: bundle AXIS signals into bus for Intel

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Laszlo Nagy 2019-05-16 08:09:49 +01:00 committed by Laszlo Nagy
parent 9273cde33f
commit 96769c92bb
1 changed files with 6 additions and 3 deletions
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9
library/util_pack/util_upack2/util_upack2_hw.tcl
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@ -74,9 +74,12 @@ proc util_upack_elab {} {
# This is a temporary hack and should be removed once all projects have been
# updated to use the AXI streaming interface to connect the the upack
if {$interface_type == 0} {
ad_alt_intf signal s_axis_valid input 1 valid
ad_alt_intf signal s_axis_ready output 1 ready
ad_alt_intf signal s_axis_data input $total_data_width data
add_interface s_axis axi4stream end
set_interface_property s_axis associatedClock clk
set_interface_property s_axis associatedReset reset
add_interface_port s_axis s_axis_valid tvalid Input 1
add_interface_port s_axis s_axis_ready tready Output 1
add_interface_port s_axis s_axis_data tdata Input $total_data_width
} else {
ad_alt_intf signal packed_fifo_rd_en output 1 valid
set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"