util_upack2: bundle AXIS signals into bus for Intel
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9273cde33f
commit
96769c92bb
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@ -74,9 +74,12 @@ proc util_upack_elab {} {
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# This is a temporary hack and should be removed once all projects have been
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# This is a temporary hack and should be removed once all projects have been
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# updated to use the AXI streaming interface to connect the the upack
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# updated to use the AXI streaming interface to connect the the upack
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if {$interface_type == 0} {
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if {$interface_type == 0} {
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ad_alt_intf signal s_axis_valid input 1 valid
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add_interface s_axis axi4stream end
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ad_alt_intf signal s_axis_ready output 1 ready
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set_interface_property s_axis associatedClock clk
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ad_alt_intf signal s_axis_data input $total_data_width data
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set_interface_property s_axis associatedReset reset
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add_interface_port s_axis s_axis_valid tvalid Input 1
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add_interface_port s_axis s_axis_ready tready Output 1
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add_interface_port s_axis s_axis_data tdata Input $total_data_width
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} else {
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} else {
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ad_alt_intf signal packed_fifo_rd_en output 1 valid
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ad_alt_intf signal packed_fifo_rd_en output 1 valid
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set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"
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set_port_property packed_fifo_rd_en fragment_list "s_axis_ready"
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