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util_dacfifo_bypass: Update comments

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Istvan Csomortani 2018-06-06 12:54:48 +01:00 committed by István Csomortáni
parent 5d3b2b1550
commit 97800745db
2 changed files with 14 additions and 13 deletions
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11
library/altera/avl_dacfifo/util_dacfifo_bypass.v
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@ -40,7 +40,7 @@ module util_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64, parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64) ( parameter DMA_DATA_WIDTH = 64) (
// dma fifo interface // DMA FIFO interface
input dma_clk, input dma_clk,
input [(DMA_DATA_WIDTH-1):0] dma_data, input [(DMA_DATA_WIDTH-1):0] dma_data,
@ -48,7 +48,7 @@ module util_dacfifo_bypass #(
output reg dma_ready_out, output reg dma_ready_out,
input dma_valid, input dma_valid,
// request and syncronizaiton // request and synchronization
input dma_xfer_req, input dma_xfer_req,
@ -61,7 +61,7 @@ module util_dacfifo_bypass #(
output reg dac_dunf output reg dac_dunf
); );
// suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1 // supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH : localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
DAC_DATA_WIDTH/DMA_DATA_WIDTH; DAC_DATA_WIDTH/DMA_DATA_WIDTH;
@ -225,7 +225,7 @@ module util_dacfifo_bypass #(
.din (dac_mem_raddr), .din (dac_mem_raddr),
.dout (dac_mem_raddr_b2g_s)); .dout (dac_mem_raddr_b2g_s));
// The memory module is ready if it's not empty // transfer the write address into the DAC's clock domain
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin if (dac_rst == 1'b1) begin
@ -261,7 +261,8 @@ module util_dacfifo_bypass #(
end end
end end
// DAC data output logic // DAC data output logic - make sure that the data output is zero between
// transfers
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_dunf == 1'b1) begin if (dac_dunf == 1'b1) begin

16
library/xilinx/axi_dacfifo/util_dacfifo_bypass.v
View File

@ -40,7 +40,7 @@ module util_dacfifo_bypass #(
parameter DAC_DATA_WIDTH = 64, parameter DAC_DATA_WIDTH = 64,
parameter DMA_DATA_WIDTH = 64) ( parameter DMA_DATA_WIDTH = 64) (
// dma fifo interface // DMA FIFO interface
input dma_clk, input dma_clk,
input [(DMA_DATA_WIDTH-1):0] dma_data, input [(DMA_DATA_WIDTH-1):0] dma_data,
@ -52,7 +52,7 @@ module util_dacfifo_bypass #(
input dma_xfer_req, input dma_xfer_req,
// dac fifo interface // DAC FIFO interface
input dac_clk, input dac_clk,
input dac_rst, input dac_rst,
@ -105,7 +105,7 @@ module util_dacfifo_bypass #(
wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s; wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s; wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
// An asymmetric memory to transfer data from DMAC interface to DAC interface // an asymmetric memory, storage element of the FIFO
ad_mem_asym #( ad_mem_asym #(
.A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH), .A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
@ -121,14 +121,14 @@ module util_dacfifo_bypass #(
.addrb (dac_mem_raddr), .addrb (dac_mem_raddr),
.doutb (dac_mem_rdata_s)); .doutb (dac_mem_rdata_s));
// dma reset is brought from dac domain // DMA reset is brought from dac domain
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
dma_rst_m1 <= dac_rst; dma_rst_m1 <= dac_rst;
dma_rst <= dma_rst_m1; dma_rst <= dma_rst_m1;
end end
// Write address generation for the asymmetric memory // write address generation for the asymmetric FIFO
assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready; assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
@ -150,7 +150,7 @@ module util_dacfifo_bypass #(
.din (dma_mem_waddr), .din (dma_mem_waddr),
.dout (dma_mem_waddr_b2g_s)); .dout (dma_mem_waddr_b2g_s));
// The memory module request data until reaches the high threshold. // FIFO request data until reaches the high threshold.
always @(posedge dma_clk) begin always @(posedge dma_clk) begin
if (dma_rst == 1'b1) begin if (dma_rst == 1'b1) begin
@ -178,7 +178,7 @@ module util_dacfifo_bypass #(
.din (dma_mem_raddr_m2), .din (dma_mem_raddr_m2),
.dout (dma_mem_raddr_m2_g2b_s)); .dout (dma_mem_raddr_m2_g2b_s));
// relative address offset on dma domain // relative address offset on DMA domain
assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s; assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ? assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
((MEM_RATIO == 1) ? (dma_mem_raddr) : ((MEM_RATIO == 1) ? (dma_mem_raddr) :
@ -224,7 +224,7 @@ module util_dacfifo_bypass #(
.din (dac_mem_raddr), .din (dac_mem_raddr),
.dout (dac_mem_raddr_b2g_s)); .dout (dac_mem_raddr_b2g_s));
// The memory module is ready if it's not empty // transfer the write address into the DAC's clock domain
always @(posedge dac_clk) begin always @(posedge dac_clk) begin
if (dac_rst == 1'b1) begin if (dac_rst == 1'b1) begin