util_dacfifo_bypass: Update comments
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5d3b2b1550
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97800745db
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@ -40,7 +40,7 @@ module util_dacfifo_bypass #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64) (
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parameter DMA_DATA_WIDTH = 64) (
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// dma fifo interface
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// DMA FIFO interface
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input dma_clk,
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input dma_clk,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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@ -48,7 +48,7 @@ module util_dacfifo_bypass #(
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output reg dma_ready_out,
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output reg dma_ready_out,
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input dma_valid,
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input dma_valid,
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// request and syncronizaiton
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// request and synchronization
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input dma_xfer_req,
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input dma_xfer_req,
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@ -61,7 +61,7 @@ module util_dacfifo_bypass #(
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output reg dac_dunf
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output reg dac_dunf
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);
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);
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// suported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
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// supported ratios: 1:1 / 1:2 / 1:4 / 1:8 / 2:1 / 4:1 / 8:1
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localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
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localparam MEM_RATIO = (DMA_DATA_WIDTH > DAC_DATA_WIDTH) ? DMA_DATA_WIDTH/DAC_DATA_WIDTH :
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DAC_DATA_WIDTH/DMA_DATA_WIDTH;
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DAC_DATA_WIDTH/DMA_DATA_WIDTH;
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@ -225,7 +225,7 @@ module util_dacfifo_bypass #(
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.din (dac_mem_raddr),
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.din (dac_mem_raddr),
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.dout (dac_mem_raddr_b2g_s));
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.dout (dac_mem_raddr_b2g_s));
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// The memory module is ready if it's not empty
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// transfer the write address into the DAC's clock domain
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always @(posedge dac_clk) begin
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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if (dac_rst == 1'b1) begin
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@ -261,7 +261,8 @@ module util_dacfifo_bypass #(
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end
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end
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end
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end
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// DAC data output logic
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// DAC data output logic - make sure that the data output is zero between
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// transfers
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always @(posedge dac_clk) begin
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always @(posedge dac_clk) begin
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if (dac_dunf == 1'b1) begin
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if (dac_dunf == 1'b1) begin
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@ -40,7 +40,7 @@ module util_dacfifo_bypass #(
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parameter DAC_DATA_WIDTH = 64,
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parameter DAC_DATA_WIDTH = 64,
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parameter DMA_DATA_WIDTH = 64) (
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parameter DMA_DATA_WIDTH = 64) (
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// dma fifo interface
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// DMA FIFO interface
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input dma_clk,
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input dma_clk,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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input [(DMA_DATA_WIDTH-1):0] dma_data,
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@ -52,7 +52,7 @@ module util_dacfifo_bypass #(
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input dma_xfer_req,
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input dma_xfer_req,
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// dac fifo interface
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// DAC FIFO interface
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input dac_clk,
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input dac_clk,
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input dac_rst,
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input dac_rst,
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@ -105,7 +105,7 @@ module util_dacfifo_bypass #(
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wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
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wire [(DAC_ADDRESS_WIDTH-1):0] dma_mem_raddr_m2_g2b_s;
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wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
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wire [(DMA_ADDRESS_WIDTH-1):0] dac_mem_waddr_m2_g2b_s;
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// An asymmetric memory to transfer data from DMAC interface to DAC interface
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// an asymmetric memory, storage element of the FIFO
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ad_mem_asym #(
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ad_mem_asym #(
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.A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
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.A_ADDRESS_WIDTH (DMA_ADDRESS_WIDTH),
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@ -121,14 +121,14 @@ module util_dacfifo_bypass #(
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.addrb (dac_mem_raddr),
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.addrb (dac_mem_raddr),
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.doutb (dac_mem_rdata_s));
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.doutb (dac_mem_rdata_s));
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// dma reset is brought from dac domain
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// DMA reset is brought from dac domain
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always @(posedge dma_clk) begin
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always @(posedge dma_clk) begin
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dma_rst_m1 <= dac_rst;
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dma_rst_m1 <= dac_rst;
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dma_rst <= dma_rst_m1;
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dma_rst <= dma_rst_m1;
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end
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end
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// Write address generation for the asymmetric memory
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// write address generation for the asymmetric FIFO
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assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
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assign dma_mem_wea_s = dma_xfer_req & dma_valid & dma_ready;
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@ -150,7 +150,7 @@ module util_dacfifo_bypass #(
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.din (dma_mem_waddr),
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.din (dma_mem_waddr),
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.dout (dma_mem_waddr_b2g_s));
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.dout (dma_mem_waddr_b2g_s));
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// The memory module request data until reaches the high threshold.
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// FIFO request data until reaches the high threshold.
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always @(posedge dma_clk) begin
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always @(posedge dma_clk) begin
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if (dma_rst == 1'b1) begin
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if (dma_rst == 1'b1) begin
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@ -178,7 +178,7 @@ module util_dacfifo_bypass #(
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.din (dma_mem_raddr_m2),
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.din (dma_mem_raddr_m2),
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.dout (dma_mem_raddr_m2_g2b_s));
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.dout (dma_mem_raddr_m2_g2b_s));
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// relative address offset on dma domain
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// relative address offset on DMA domain
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assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
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assign dma_address_diff_s = {1'b1, dma_mem_waddr} - dma_mem_raddr_s;
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assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
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assign dma_mem_raddr_s = (DMA_DATA_WIDTH>DAC_DATA_WIDTH) ?
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((MEM_RATIO == 1) ? (dma_mem_raddr) :
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((MEM_RATIO == 1) ? (dma_mem_raddr) :
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@ -224,7 +224,7 @@ module util_dacfifo_bypass #(
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.din (dac_mem_raddr),
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.din (dac_mem_raddr),
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.dout (dac_mem_raddr_b2g_s));
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.dout (dac_mem_raddr_b2g_s));
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// The memory module is ready if it's not empty
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// transfer the write address into the DAC's clock domain
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always @(posedge dac_clk) begin
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always @(posedge dac_clk) begin
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if (dac_rst == 1'b1) begin
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if (dac_rst == 1'b1) begin
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