axi_hdmi_rx: Update constraint file and fix reset line
parent
10977e9589
commit
97a9ecfc9a
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@ -1,46 +0,0 @@
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set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
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set hdmi_rx_clk [get_clocks -of_objects [get_ports hdmi_rx_clk]]
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set_property ASYNC_REG TRUE \
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[get_cells -hier *toggle_m1_reg*] \
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[get_cells -hier *toggle_m2_reg*] \
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[get_cells -hier *state_m1_reg*] \
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[get_cells -hier *state_m2_reg*]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $hdmi_rx_clk]
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set_false_path \
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-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_false_path \
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-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
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set_max_delay -datapath_only \
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-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
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-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
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[get_property PERIOD $up_clk]
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set_false_path \
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-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]
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@ -5,6 +5,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
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adi_ip_create axi_hdmi_rx
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adi_ip_create axi_hdmi_rx
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adi_ip_files axi_hdmi_rx [list \
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adi_ip_files axi_hdmi_rx [list \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/ad_rst.v" \
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"$ad_hdl_dir/library/common/ad_csc_1.v" \
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"$ad_hdl_dir/library/common/ad_csc_1.v" \
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"$ad_hdl_dir/library/common/ad_csc_1_mul.v" \
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"$ad_hdl_dir/library/common/ad_csc_1_mul.v" \
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@ -24,7 +25,8 @@ adi_ip_files axi_hdmi_rx [list \
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adi_ip_properties axi_hdmi_rx
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adi_ip_properties axi_hdmi_rx
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adi_ip_constraints axi_hdmi_rx [list \
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adi_ip_constraints axi_hdmi_rx [list \
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"axi_hdmi_rx_constr.xdc" ]
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"axi_hdmi_rx_constr.xdc" \
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"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
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ipx::save_core [ipx::current_core]
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ipx::save_core [ipx::current_core]
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@ -112,7 +112,8 @@ module up_hdmi_rx (
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// internal registers
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// internal registers
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reg up_preset = 'd0;
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reg up_core_preset = 'd0;
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reg up_resetn = 'd0;
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reg up_wack = 'd0;
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reg up_wack = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg [31:0] up_scratch = 'd0;
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reg up_edge_sel = 'd0;
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reg up_edge_sel = 'd0;
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@ -154,7 +155,8 @@ module up_hdmi_rx (
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always @(negedge up_rstn or posedge up_clk) begin
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always @(negedge up_rstn or posedge up_clk) begin
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if (up_rstn == 0) begin
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if (up_rstn == 0) begin
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up_preset <= 1'd1;
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up_core_preset <= 1'd1;
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up_resetn <= 'd0;
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up_wack <= 'd0;
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up_wack <= 'd0;
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up_scratch <= 'd0;
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up_scratch <= 'd0;
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up_edge_sel <= 'd0;
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up_edge_sel <= 'd0;
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@ -172,11 +174,12 @@ module up_hdmi_rx (
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up_hs_count <= 'd0;
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up_hs_count <= 'd0;
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end else begin
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end else begin
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up_wack <= up_wreq_s;
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up_wack <= up_wreq_s;
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up_core_preset <= ~up_resetn;
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
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up_scratch <= up_wdata;
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up_scratch <= up_wdata;
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
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up_preset <= ~up_wdata[0];
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up_resetn <= up_wdata[0];
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end
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end
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
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if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
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up_edge_sel <= up_wdata[3];
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up_edge_sel <= up_wdata[3];
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@ -239,7 +242,7 @@ module up_hdmi_rx (
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12'h000: up_rdata <= PCORE_VERSION;
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12'h000: up_rdata <= PCORE_VERSION;
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12'h001: up_rdata <= ID;
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12'h001: up_rdata <= ID;
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12'h002: up_rdata <= up_scratch;
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12'h002: up_rdata <= up_scratch;
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12'h010: up_rdata <= {31'h0, ~up_preset};
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12'h010: up_rdata <= {31'h0, up_resetn};
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12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
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12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
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12'h015: up_rdata <= up_clk_count_s;
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12'h015: up_rdata <= up_clk_count_s;
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12'h016: up_rdata <= hdmi_clk_ratio;
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12'h016: up_rdata <= hdmi_clk_ratio;
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@ -258,7 +261,7 @@ module up_hdmi_rx (
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// resets
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// resets
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ad_rst i_hdmi_rst_reg (
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ad_rst i_hdmi_rst_reg (
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.preset (up_preset),
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.preset (up_core_preset),
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.clk (hdmi_clk),
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.clk (hdmi_clk),
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.rst (hdmi_rst));
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.rst (hdmi_rst));
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