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axi_hdmi_rx: Update constraint file and fix reset line

main
Istvan Csomortani 2015-09-29 18:49:30 +03:00
parent 10977e9589
commit 97a9ecfc9a
3 changed files with 11 additions and 52 deletions
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46
library/axi_hdmi_rx/axi_hdmi_rx_constr.xdc
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@ -1,46 +0,0 @@
set up_clk [get_clocks -of_objects [get_ports s_axi_aclk]]
set hdmi_rx_clk [get_clocks -of_objects [get_ports hdmi_rx_clk]]
set_property ASYNC_REG TRUE \
[get_cells -hier *toggle_m1_reg*] \
[get_cells -hier *toggle_m2_reg*] \
[get_cells -hier *state_m1_reg*] \
[get_cells -hier *state_m2_reg*]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier up_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_data_cntrl_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $hdmi_rx_clk]
set_false_path \
-from [get_cells -hier d_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_xfer_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier up_xfer_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_xfer_state_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_xfer_data_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_data_status_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-from [get_cells -hier up_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier d_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_false_path \
-from [get_cells -hier d_count_toggle_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_count_toggle_m1_reg* -filter {primitive_subgroup == flop}]
set_max_delay -datapath_only \
-from [get_cells -hier d_count_hold_reg* -filter {primitive_subgroup == flop}] \
-to [get_cells -hier up_d_count_reg* -filter {primitive_subgroup == flop}] \
[get_property PERIOD $up_clk]
set_false_path \
-to [get_pins -hier */PRE -filter {NAME =~ *i_*rst_reg*}]

4
library/axi_hdmi_rx/axi_hdmi_rx_ip.tcl
View File

@ -5,6 +5,7 @@ source $ad_hdl_dir/library/scripts/adi_ip.tcl
adi_ip_create axi_hdmi_rx
adi_ip_files axi_hdmi_rx [list \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" \
"$ad_hdl_dir/library/common/ad_rst.v" \
"$ad_hdl_dir/library/common/ad_csc_1.v" \
"$ad_hdl_dir/library/common/ad_csc_1_mul.v" \
@ -24,7 +25,8 @@ adi_ip_files axi_hdmi_rx [list \
adi_ip_properties axi_hdmi_rx
adi_ip_constraints axi_hdmi_rx [list \
"axi_hdmi_rx_constr.xdc" ]
"axi_hdmi_rx_constr.xdc" \
"$ad_hdl_dir/library/common/ad_axi_ip_constr.xdc" ]
ipx::save_core [ipx::current_core]

13
library/common/up_hdmi_rx.v
View File

@ -112,7 +112,8 @@ module up_hdmi_rx (
// internal registers
reg up_preset = 'd0;
reg up_core_preset = 'd0;
reg up_resetn = 'd0;
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_edge_sel = 'd0;
@ -154,7 +155,8 @@ module up_hdmi_rx (
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_preset <= 1'd1;
up_core_preset <= 1'd1;
up_resetn <= 'd0;
up_wack <= 'd0;
up_scratch <= 'd0;
up_edge_sel <= 'd0;
@ -172,11 +174,12 @@ module up_hdmi_rx (
up_hs_count <= 'd0;
end else begin
up_wack <= up_wreq_s;
up_core_preset <= ~up_resetn;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_preset <= ~up_wdata[0];
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_edge_sel <= up_wdata[3];
@ -239,7 +242,7 @@ module up_hdmi_rx (
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'h0, ~up_preset};
12'h010: up_rdata <= {31'h0, up_resetn};
12'h011: up_rdata <= {28'h0, up_edge_sel, up_bgr, up_packed, up_csc_bypass};
12'h015: up_rdata <= up_clk_count_s;
12'h016: up_rdata <= hdmi_clk_ratio;
@ -258,7 +261,7 @@ module up_hdmi_rx (
// resets
ad_rst i_hdmi_rst_reg (
.preset (up_preset),
.preset (up_core_preset),
.clk (hdmi_clk),
.rst (hdmi_rst));